Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	745917396	4531510	0	0
wdog_bark_thold_rd_A	745917396	21328	0	0
wdog_bite_thold_rd_A	745917396	18867	0	0
wdog_ctrl_rd_A	745917396	19225	0	0
wdog_regwen_rd_A	745917396	21862	0	0
wkup_ctrl_rd_A	745917396	18670	0	0
wkup_thold_hi_rd_A	745917396	21174	0	0
wkup_thold_lo_rd_A	745917396	19636	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	4531510	0	0
T1	296514	81585	0	0
T2	285100	0	0	0
T3	703951	256973	0	0
T4	186706	0	0	0
T5	443238	0	0	0
T6	435489	165291	0	0
T7	205298	54458	0	0
T8	35158	0	0	0
T9	12288	0	0	0
T10	10778	0	0	0
T29	0	25983	0	0
T36	0	140744	0	0
T37	0	73724	0	0
T38	0	50220	0	0
T39	0	48657	0	0
T40	0	64536	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	21328	0	0
T29	115144	1602	0	0
T35	0	45	0	0
T39	0	4138	0	0
T40	0	6237	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	537	0	0
T74	0	5475	0	0
T75	0	2538	0	0
T76	0	10	0	0
T77	0	84	0	0
T78	0	20	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	18867	0	0
T29	115144	1328	0	0
T35	0	41	0	0
T39	0	3727	0	0
T40	0	5608	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	434	0	0
T74	0	4882	0	0
T75	0	2036	0	0
T76	0	2	0	0
T77	0	48	0	0
T78	0	48	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	19225	0	0
T29	115144	1311	0	0
T35	0	46	0	0
T39	0	4000	0	0
T40	0	5583	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	479	0	0
T74	0	4881	0	0
T75	0	2000	0	0
T76	0	17	0	0
T77	0	77	0	0
T78	0	46	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	21862	0	0
T29	115144	1527	0	0
T35	0	44	0	0
T39	0	4281	0	0
T40	0	6139	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	530	0	0
T74	0	5677	0	0
T75	0	2414	0	0
T76	0	13	0	0
T77	0	69	0	0
T78	0	62	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	18670	0	0
T29	115144	1202	0	0
T35	0	60	0	0
T39	0	3931	0	0
T40	0	5249	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	473	0	0
T74	0	4735	0	0
T75	0	2094	0	0
T76	0	23	0	0
T77	0	70	0	0
T78	0	39	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	21174	0	0
T29	115144	1489	0	0
T35	0	30	0	0
T39	0	4266	0	0
T40	0	6122	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	480	0	0
T74	0	5600	0	0
T75	0	2395	0	0
T76	0	14	0	0
T77	0	52	0	0
T78	0	33	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	745917396	19636	0	0
T29	115144	1317	0	0
T35	0	26	0	0
T39	0	4060	0	0
T40	0	5684	0	0
T42	100447	0	0	0
T43	49795	0	0	0
T73	0	554	0	0
T74	0	5028	0	0
T75	0	2178	0	0
T76	0	6	0	0
T77	0	80	0	0
T78	0	25	0	0
T79	25657	0	0	0
T80	9490	0	0	0
T81	11741	0	0	0
T82	26998	0	0	0
T83	352975	0	0	0
T84	935620	0	0	0
T85	133559	0	0	0