Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313683	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3793238	1		T1	16		T2	16405		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1009290	1		T1	1		T2	4428		T3	1
values[0x0]	1453671	1		T1	9		T2	6224		T3	8
values[0x1]	1643960	1		T1	12		T2	7125		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141323	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3965598	1		T1	17		T2	17185		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16543	1		T1	3		T4	1		T7	927
valid_sources[0x01]	15261	1		T2	51		T7	1175		T8	272
valid_sources[0x02]	15972	1		T7	991		T8	856		T10	120
valid_sources[0x03]	15774	1		T7	1216		T8	416		T10	126
valid_sources[0x04]	16473	1		T2	204		T7	1047		T8	1048
valid_sources[0x05]	15779	1		T2	255		T7	970		T8	313
valid_sources[0x06]	17126	1		T7	1223		T8	389		T10	862
valid_sources[0x07]	16976	1		T2	9		T7	958		T8	387
valid_sources[0x08]	15918	1		T2	103		T7	934		T8	551
valid_sources[0x09]	17130	1		T2	2		T7	1015		T8	916
valid_sources[0x0a]	16065	1		T1	1		T7	1185		T8	362
valid_sources[0x0b]	16758	1		T2	54		T7	993		T8	273
valid_sources[0x0c]	15111	1		T2	276		T7	962		T8	376
valid_sources[0x0d]	16026	1		T2	76		T5	2		T7	1127
valid_sources[0x0e]	15595	1		T7	921		T8	197		T10	278
valid_sources[0x0f]	18188	1		T2	6		T7	943		T8	840
valid_sources[0x10]	15383	1		T2	3		T7	1129		T8	251
valid_sources[0x11]	16287	1		T2	1		T7	965		T8	1006
valid_sources[0x12]	16349	1		T7	838		T8	1561		T10	103
valid_sources[0x13]	15769	1		T2	145		T7	855		T8	429
valid_sources[0x14]	17307	1		T7	876		T8	289		T10	321
valid_sources[0x15]	15802	1		T2	155		T7	1018		T8	633
valid_sources[0x16]	15565	1		T7	822		T8	534		T10	392
valid_sources[0x17]	16396	1		T7	965		T8	1002		T10	394
valid_sources[0x18]	17426	1		T2	167		T7	1007		T8	677
valid_sources[0x19]	15783	1		T2	172		T7	1155		T8	622
valid_sources[0x1a]	17182	1		T2	155		T7	1148		T8	1075
valid_sources[0x1b]	15987	1		T7	1148		T8	556		T10	126
valid_sources[0x1c]	15366	1		T5	1		T7	1102		T8	303
valid_sources[0x1d]	16962	1		T2	6		T7	1048		T8	709
valid_sources[0x1e]	15390	1		T7	1090		T8	353		T10	193
valid_sources[0x1f]	16097	1		T2	1		T7	989		T8	348
valid_sources[0x20]	16094	1		T7	931		T8	793		T10	261
valid_sources[0x21]	16739	1		T2	171		T7	957		T8	586
valid_sources[0x22]	15611	1		T2	89		T7	1191		T8	49
valid_sources[0x23]	14549	1		T2	1		T7	916		T8	333
valid_sources[0x24]	16821	1		T2	168		T7	969		T8	518
valid_sources[0x25]	16798	1		T7	1087		T8	317		T10	326
valid_sources[0x26]	15771	1		T7	1028		T8	604		T10	105
valid_sources[0x27]	15132	1		T7	968		T8	434		T10	29
valid_sources[0x28]	16364	1		T2	126		T7	895		T8	281
valid_sources[0x29]	15503	1		T2	8		T7	1036		T8	380
valid_sources[0x2a]	17076	1		T2	161		T7	1033		T8	201
valid_sources[0x2b]	15569	1		T7	853		T8	573		T10	322
valid_sources[0x2c]	17370	1		T7	1025		T8	165		T10	543
valid_sources[0x2d]	14907	1		T7	802		T8	483		T10	183
valid_sources[0x2e]	15912	1		T7	1068		T8	404		T10	217
valid_sources[0x2f]	15834	1		T7	1097		T8	410		T10	98
valid_sources[0x30]	16309	1		T7	1067		T8	532		T10	10
valid_sources[0x31]	16910	1		T7	1241		T8	873		T10	209
valid_sources[0x32]	15812	1		T2	168		T7	1143		T8	734
valid_sources[0x33]	17393	1		T2	76		T7	1251		T8	403
valid_sources[0x34]	16238	1		T2	2		T7	960		T8	654
valid_sources[0x35]	15594	1		T7	906		T8	363		T10	335
valid_sources[0x36]	16329	1		T2	57		T7	1151		T8	289
valid_sources[0x37]	16146	1		T7	1030		T8	587		T10	259
valid_sources[0x38]	17515	1		T2	17		T7	1051		T8	847
valid_sources[0x39]	16417	1		T2	51		T7	1007		T8	295
valid_sources[0x3a]	15690	1		T4	1		T7	1093		T8	635
valid_sources[0x3b]	15555	1		T2	27		T7	965		T8	527
valid_sources[0x3c]	16154	1		T2	240		T7	1181		T8	227
valid_sources[0x3d]	16192	1		T2	7		T7	923		T8	488
valid_sources[0x3e]	16055	1		T5	2		T7	1049		T8	392
valid_sources[0x3f]	15784	1		T2	94		T7	843		T8	388
valid_sources[0x40]	16254	1		T7	1115		T8	691		T10	309
valid_sources[0x41]	15566	1		T7	1084		T8	325		T10	72
valid_sources[0x42]	15886	1		T2	315		T7	1068		T8	365
valid_sources[0x43]	16716	1		T2	183		T7	998		T8	140
valid_sources[0x44]	16624	1		T2	81		T7	1087		T8	174
valid_sources[0x45]	14733	1		T2	101		T7	970		T8	37
valid_sources[0x46]	14579	1		T3	22		T7	971		T8	221
valid_sources[0x47]	16169	1		T2	169		T4	1		T7	1049
valid_sources[0x48]	15652	1		T7	851		T8	168		T10	357
valid_sources[0x49]	15769	1		T7	1049		T8	377		T10	245
valid_sources[0x4a]	14917	1		T2	210		T7	1155		T8	475
valid_sources[0x4b]	15950	1		T2	202		T7	797		T8	537
valid_sources[0x4c]	14895	1		T2	45		T7	935		T8	266
valid_sources[0x4d]	15811	1		T7	1005		T8	490		T10	200
valid_sources[0x4e]	16665	1		T2	115		T7	957		T8	495
valid_sources[0x4f]	15905	1		T2	9		T7	903		T8	699
valid_sources[0x50]	16087	1		T2	84		T7	1020		T8	431
valid_sources[0x51]	16510	1		T2	146		T7	981		T8	546
valid_sources[0x52]	16861	1		T4	1		T7	1093		T8	480
valid_sources[0x53]	15241	1		T2	28		T7	997		T8	485
valid_sources[0x54]	16661	1		T7	890		T8	400		T10	723
valid_sources[0x55]	15731	1		T2	2		T7	979		T8	187
valid_sources[0x56]	15780	1		T2	133		T7	956		T8	336
valid_sources[0x57]	16347	1		T2	260		T7	1046		T8	168
valid_sources[0x58]	15531	1		T2	258		T7	1061		T8	29
valid_sources[0x59]	16031	1		T2	281		T7	930		T8	409
valid_sources[0x5a]	16763	1		T5	1		T7	942		T8	982
valid_sources[0x5b]	15664	1		T2	5		T4	5		T7	1021
valid_sources[0x5c]	15930	1		T2	5		T7	1020		T8	481
valid_sources[0x5d]	16247	1		T7	1174		T8	149		T10	268
valid_sources[0x5e]	16311	1		T2	117		T7	1138		T8	178
valid_sources[0x5f]	16255	1		T7	976		T8	676		T10	385
valid_sources[0x60]	15130	1		T7	941		T8	405		T10	516
valid_sources[0x61]	17009	1		T7	979		T8	750		T10	317
valid_sources[0x62]	16314	1		T2	97		T7	844		T8	235
valid_sources[0x63]	15647	1		T2	2		T7	1023		T8	606
valid_sources[0x64]	16327	1		T2	171		T7	1109		T8	442
valid_sources[0x65]	15868	1		T5	2		T7	1044		T8	202
valid_sources[0x66]	15829	1		T2	71		T5	1		T7	1061
valid_sources[0x67]	16346	1		T2	41		T7	1230		T8	275
valid_sources[0x68]	15921	1		T1	5		T2	1		T5	1
valid_sources[0x69]	15537	1		T7	1004		T8	318		T10	296
valid_sources[0x6a]	16081	1		T2	15		T7	908		T8	319
valid_sources[0x6b]	16162	1		T2	96		T7	1014		T8	421
valid_sources[0x6c]	17838	1		T7	1102		T8	745		T10	524
valid_sources[0x6d]	15739	1		T2	1		T7	755		T8	489
valid_sources[0x6e]	16558	1		T2	164		T7	882		T8	185
valid_sources[0x6f]	15242	1		T7	911		T8	515		T10	301
valid_sources[0x70]	15572	1		T2	188		T7	947		T8	349
valid_sources[0x71]	15916	1		T2	2		T7	873		T8	687
valid_sources[0x72]	15142	1		T2	93		T7	950		T8	213
valid_sources[0x73]	15206	1		T7	922		T8	247		T10	112
valid_sources[0x74]	16046	1		T2	67		T7	954		T8	226
valid_sources[0x75]	16592	1		T2	41		T7	1059		T8	1056
valid_sources[0x76]	16168	1		T2	140		T7	1158		T8	249
valid_sources[0x77]	16423	1		T7	848		T8	668		T10	235
valid_sources[0x78]	15754	1		T7	862		T8	254		T10	176
valid_sources[0x79]	15853	1		T2	1		T7	958		T8	243
valid_sources[0x7a]	16361	1		T7	1007		T8	504		T10	113
valid_sources[0x7b]	15649	1		T7	1030		T8	45		T10	401
valid_sources[0x7c]	15767	1		T7	983		T8	567		T10	202
valid_sources[0x7d]	16054	1		T2	199		T7	957		T8	728
valid_sources[0x7e]	16116	1		T2	286		T7	922		T8	130
valid_sources[0x7f]	15437	1		T2	79		T7	962		T8	134
valid_sources[0x80]	15566	1		T5	1		T7	1024		T8	417

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

945357

1

T1

1

T2

4097

T3

1

values[0x0]

all_enables

biggest_size

1426013

1

T1

8

T2

6108

T3

4

values[0x1]

all_enables

biggest_size

1421868

1

T1

7

T2

6200

T3

9