Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	826272370	4490794	0	0
wdog_bark_thold_rd_A	826272370	110121	0	0
wdog_bite_thold_rd_A	826272370	97101	0	0
wdog_ctrl_rd_A	826272370	94975	0	0
wdog_regwen_rd_A	826272370	110589	0	0
wkup_ctrl_rd_A	826272370	96674	0	0
wkup_thold_hi_rd_A	826272370	108968	0	0
wkup_thold_lo_rd_A	826272370	97523	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	4490794	0	0
T2	804616	21242	0	0
T3	29684	0	0	0
T4	42757	0	0	0
T5	11654	0	0	0
T6	238438	0	0	0
T7	109167	296002	0	0
T8	805523	125090	0	0
T9	25637	0	0	0
T10	425331	81149	0	0
T16	43557	0	0	0
T25	0	55682	0	0
T32	0	25228	0	0
T38	0	133822	0	0
T39	0	66999	0	0
T40	0	36280	0	0
T41	0	87941	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	110121	0	0
T10	425331	8427	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	13755	0	0
T40	0	3735	0	0
T41	0	4857	0	0
T42	36927	0	0	0
T80	0	7585	0	0
T81	0	6134	0	0
T82	0	7438	0	0
T83	0	9654	0	0
T84	0	17250	0	0
T85	0	10639	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	97101	0	0
T10	425331	6848	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	11871	0	0
T40	0	3275	0	0
T41	0	4296	0	0
T42	36927	0	0	0
T80	0	6581	0	0
T81	0	5222	0	0
T82	0	6477	0	0
T83	0	8235	0	0
T84	0	15555	0	0
T85	0	9409	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	94975	0	0
T10	425331	7234	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	11332	0	0
T40	0	3373	0	0
T41	0	4280	0	0
T42	36927	0	0	0
T80	0	6629	0	0
T81	0	4671	0	0
T82	0	6438	0	0
T83	0	8082	0	0
T84	0	15083	0	0
T85	0	9504	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	110589	0	0
T10	425331	8274	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	13378	0	0
T40	0	3832	0	0
T41	0	4831	0	0
T42	36927	0	0	0
T80	0	7653	0	0
T81	0	5772	0	0
T82	0	7523	0	0
T83	0	9447	0	0
T84	0	17518	0	0
T85	0	10897	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	96674	0	0
T10	425331	7407	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	12014	0	0
T40	0	3233	0	0
T41	0	4034	0	0
T42	36927	0	0	0
T80	0	6522	0	0
T81	0	4991	0	0
T82	0	6432	0	0
T83	0	8652	0	0
T84	0	14734	0	0
T85	0	9412	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	108968	0	0
T10	425331	8247	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	13470	0	0
T40	0	3556	0	0
T41	0	4773	0	0
T42	36927	0	0	0
T80	0	7612	0	0
T81	0	5611	0	0
T82	0	7674	0	0
T83	0	9594	0	0
T84	0	16882	0	0
T85	0	10613	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	826272370	97523	0	0
T10	425331	7252	0	0
T11	339576	0	0	0
T12	49728	0	0	0
T13	843879	0	0	0
T14	658113	0	0	0
T15	132891	0	0	0
T16	43557	0	0	0
T31	23624	0	0	0
T32	161520	0	0	0
T38	0	12621	0	0
T40	0	3413	0	0
T41	0	4185	0	0
T42	36927	0	0	0
T80	0	6502	0	0
T81	0	5248	0	0
T82	0	6190	0	0
T83	0	8477	0	0
T84	0	15164	0	0
T85	0	9727	0	0