Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	130	43	24.86

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	32	2	5.88	100	1	1	0
bite_thold_cp	34	32	2	5.88	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	64	2	3.03	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[1]	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[9]	0	1	1
bark[10]	0	1	1
bark[11]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[22]	0	1	1
bark[23]	0	1	1
bark[24]	0	1	1
bark[25]	0	1	1
bark[26]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[30]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	53712	1		T1	14		T2	14		T3	227
bark_0	4701	1		T1	7		T2	7		T3	7

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[1]	0	1	1
bite[2]	0	1	1
bite[3]	0	1	1
bite[4]	0	1	1
bite[5]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[8]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[14]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[17]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[27]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1
bite[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	53199	1		T1	13		T2	13		T3	226
bite_0	5214	1		T1	8		T2	8		T3	8

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	58413	1		T1	21		T2	21		T3	234

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	1235	1		T10	9		T19	19		T28	58
prescale[1]	1580	1		T3	19		T20	19		T47	19
prescale[2]	1417	1		T8	84		T19	2		T41	37
prescale[3]	1084	1		T8	32		T20	123		T41	19
prescale[4]	748	1		T3	9		T19	55		T52	19
prescale[5]	1308	1		T52	24		T47	141		T48	48
prescale[6]	881	1		T11	23		T19	2		T101	23
prescale[7]	1038	1		T11	19		T19	2		T41	9
prescale[8]	944	1		T3	19		T8	2		T11	19
prescale[9]	1563	1		T3	19		T8	53		T12	44
prescale[10]	1089	1		T8	2		T14	23		T40	32
prescale[11]	1217	1		T8	20		T11	19		T20	19
prescale[12]	805	1		T15	9		T19	23		T41	58
prescale[13]	1134	1		T8	39		T20	2		T40	23
prescale[14]	1376	1		T19	19		T40	19		T49	85
prescale[15]	1065	1		T11	19		T12	37		T14	19
prescale[16]	1184	1		T12	19		T88	9		T20	2
prescale[17]	727	1		T12	41		T19	35		T20	19
prescale[18]	480	1		T3	19		T102	9		T47	12
prescale[19]	714	1		T40	9		T50	2		T28	2
prescale[20]	397	1		T8	2		T17	9		T52	28
prescale[21]	1083	1		T3	19		T20	19		T41	2
prescale[22]	754	1		T20	19		T40	40		T41	73
prescale[23]	828	1		T11	23		T48	28		T103	28
prescale[24]	904	1		T8	2		T20	75		T48	28
prescale[25]	784	1		T20	2		T101	19		T41	63
prescale[26]	659	1		T3	33		T19	2		T52	77
prescale[27]	917	1		T40	19		T47	37		T104	9
prescale[28]	702	1		T8	2		T14	19		T101	32
prescale[29]	965	1		T7	9		T9	9		T19	2
prescale[30]	1144	1		T3	24		T19	2		T101	38
prescale[31]	1562	1		T19	121		T40	19		T41	28
prescale_0	26125	1		T1	21		T2	21		T3	73

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	44439	1		T1	21		T2	9		T3	149
auto[1]	13974	1		T2	12		T3	85		T4	12

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	58413	1		T1	21		T2	21		T3	234

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	64	2	3.03

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[2]	0	1	1
wkup[3]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[6]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[9]	0	1	1
wkup[10]	0	1	1
wkup[11]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[16]	0	1	1
wkup[17]	0	1	1
wkup[18]	0	1	1
wkup[19]	0	1	1
wkup[20]	0	1	1
wkup[21]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[24]	0	1	1
wkup[25]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[28]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1
wkup[32]	0	1	1
wkup[33]	0	1	1
wkup[34]	0	1	1
wkup[35]	0	1	1
wkup[36]	0	1	1
wkup[37]	0	1	1
wkup[38]	0	1	1
wkup[39]	0	1	1
wkup[40]	0	1	1
wkup[41]	0	1	1
wkup[42]	0	1	1
wkup[43]	0	1	1
wkup[44]	0	1	1
wkup[45]	0	1	1
wkup[46]	0	1	1
wkup[47]	0	1	1
wkup[48]	0	1	1
wkup[49]	0	1	1
wkup[50]	0	1	1
wkup[51]	0	1	1
wkup[52]	0	1	1
wkup[53]	0	1	1
wkup[54]	0	1	1
wkup[55]	0	1	1
wkup[56]	0	1	1
wkup[57]	0	1	1
wkup[58]	0	1	1
wkup[59]	0	1	1
wkup[60]	0	1	1
wkup[61]	0	1	1
wkup[62]	0	1	1
wkup[63]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	54737	1		T1	16		T2	16		T3	229
wkup_0	3676	1		T1	5		T2	5		T3	5