Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4150 1 T1 1 T2 1 T3 23
all_values[1] 4150 1 T1 1 T2 1 T3 23



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6823 1 T1 1 T3 34 T5 1
auto[1] 1477 1 T1 1 T2 2 T3 12



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4687 1 T1 1 T2 2 T3 21
auto[1] 3613 1 T1 1 T3 25 T4 1



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 1772 1 T3 5 T8 24 T11 6
all_values[0] auto[0] auto[1] 1195 1 T3 7 T8 18 T11 2
all_values[0] auto[1] auto[0] 146 1 T2 1 T8 1 T11 2
all_values[0] auto[1] auto[1] 1037 1 T1 1 T3 11 T4 1
all_values[1] auto[0] auto[0] 2637 1 T1 1 T3 15 T5 1
all_values[1] auto[0] auto[1] 1219 1 T3 7 T8 14 T11 4
all_values[1] auto[1] auto[0] 132 1 T2 1 T3 1 T4 1
all_values[1] auto[1] auto[1] 162 1 T8 1 T11 3 T12 2

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