Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T42 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2784578483 Apr 15 03:35:09 PM PDT 24 Apr 15 03:35:12 PM PDT 24 1176385894 ps
T282 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1535851929 Apr 15 03:35:41 PM PDT 24 Apr 15 03:35:42 PM PDT 24 524282655 ps
T111 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1690668433 Apr 15 03:35:09 PM PDT 24 Apr 15 03:35:11 PM PDT 24 615646598 ps
T283 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.281281532 Apr 15 03:35:41 PM PDT 24 Apr 15 03:35:42 PM PDT 24 389395217 ps
T77 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.440736059 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:19 PM PDT 24 2905477582 ps
T78 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.291266129 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:36 PM PDT 24 2356372701 ps
T284 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1313207896 Apr 15 03:35:45 PM PDT 24 Apr 15 03:35:46 PM PDT 24 457068273 ps
T285 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1714484506 Apr 15 03:35:33 PM PDT 24 Apr 15 03:35:35 PM PDT 24 505207670 ps
T79 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1115743792 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:33 PM PDT 24 2824609304 ps
T43 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3171835282 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:13 PM PDT 24 7869853260 ps
T44 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1118616078 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:10 PM PDT 24 4160776845 ps
T113 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3559435497 Apr 15 03:35:17 PM PDT 24 Apr 15 03:35:18 PM PDT 24 387033007 ps
T286 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3766538597 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:09 PM PDT 24 368847585 ps
T287 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2085322451 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:35 PM PDT 24 756153666 ps
T288 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1079068323 Apr 15 03:35:37 PM PDT 24 Apr 15 03:35:40 PM PDT 24 399090920 ps
T80 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.777410179 Apr 15 03:35:12 PM PDT 24 Apr 15 03:35:15 PM PDT 24 1418554065 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1199631638 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:09 PM PDT 24 478582140 ps
T81 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2868255655 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:24 PM PDT 24 1806710583 ps
T45 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2297750504 Apr 15 03:35:37 PM PDT 24 Apr 15 03:35:40 PM PDT 24 3893273517 ps
T82 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3553759378 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:36 PM PDT 24 2503460858 ps
T83 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3584561228 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:20 PM PDT 24 1184693795 ps
T290 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3026230390 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:13 PM PDT 24 514161502 ps
T291 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1807602148 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:41 PM PDT 24 553980305 ps
T292 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3181697029 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:13 PM PDT 24 418847355 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4186071563 Apr 15 03:35:14 PM PDT 24 Apr 15 03:35:16 PM PDT 24 302217819 ps
T294 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3321117215 Apr 15 03:35:41 PM PDT 24 Apr 15 03:35:42 PM PDT 24 493176148 ps
T112 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1713626949 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:42 PM PDT 24 486631744 ps
T105 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1171856186 Apr 15 03:35:19 PM PDT 24 Apr 15 03:35:27 PM PDT 24 4202372630 ps
T106 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.207214324 Apr 15 03:35:37 PM PDT 24 Apr 15 03:35:51 PM PDT 24 8242188453 ps
T65 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2074139026 Apr 15 03:35:24 PM PDT 24 Apr 15 03:35:25 PM PDT 24 424421615 ps
T295 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1603064334 Apr 15 03:35:48 PM PDT 24 Apr 15 03:35:49 PM PDT 24 366524322 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1271951727 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:10 PM PDT 24 475303531 ps
T66 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1655720992 Apr 15 03:35:12 PM PDT 24 Apr 15 03:35:27 PM PDT 24 13475826497 ps
T297 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2477182411 Apr 15 03:35:44 PM PDT 24 Apr 15 03:35:45 PM PDT 24 367739805 ps
T298 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2077183334 Apr 15 03:35:24 PM PDT 24 Apr 15 03:35:26 PM PDT 24 503796545 ps
T299 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1313194664 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:19 PM PDT 24 465855883 ps
T300 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3308581753 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:40 PM PDT 24 531415319 ps
T301 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1328865011 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:37 PM PDT 24 713537462 ps
T302 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3068650371 Apr 15 03:35:23 PM PDT 24 Apr 15 03:35:24 PM PDT 24 286585704 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.20630517 Apr 15 03:35:01 PM PDT 24 Apr 15 03:35:04 PM PDT 24 484842738 ps
T304 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1897452467 Apr 15 03:35:15 PM PDT 24 Apr 15 03:35:17 PM PDT 24 606284124 ps
T305 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.33512397 Apr 15 03:35:24 PM PDT 24 Apr 15 03:35:25 PM PDT 24 412225911 ps
T306 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4123593450 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:36 PM PDT 24 354350555 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2909971192 Apr 15 03:35:03 PM PDT 24 Apr 15 03:35:04 PM PDT 24 546019192 ps
T308 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2977886109 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:42 PM PDT 24 331540701 ps
T309 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3139698796 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:19 PM PDT 24 485068597 ps
T310 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4135558736 Apr 15 03:35:03 PM PDT 24 Apr 15 03:35:05 PM PDT 24 404095961 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1300922919 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:19 PM PDT 24 564966715 ps
T312 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3162112364 Apr 15 03:35:39 PM PDT 24 Apr 15 03:35:40 PM PDT 24 498670203 ps
T313 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2441502554 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:10 PM PDT 24 455809636 ps
T108 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2754017887 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:21 PM PDT 24 8592278493 ps
T84 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3054168408 Apr 15 03:35:04 PM PDT 24 Apr 15 03:35:06 PM PDT 24 1514137080 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.783478548 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:15 PM PDT 24 4580660508 ps
T315 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1746334272 Apr 15 03:35:26 PM PDT 24 Apr 15 03:35:27 PM PDT 24 455551372 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.159830221 Apr 15 03:35:05 PM PDT 24 Apr 15 03:35:07 PM PDT 24 570203165 ps
T316 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.157302992 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:33 PM PDT 24 273023095 ps
T317 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2099857514 Apr 15 03:35:29 PM PDT 24 Apr 15 03:35:35 PM PDT 24 4547223561 ps
T318 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2848689629 Apr 15 03:35:14 PM PDT 24 Apr 15 03:35:16 PM PDT 24 391942607 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1096512615 Apr 15 03:35:12 PM PDT 24 Apr 15 03:35:15 PM PDT 24 582616706 ps
T320 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1744410170 Apr 15 03:35:36 PM PDT 24 Apr 15 03:35:39 PM PDT 24 403862601 ps
T321 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.803544708 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:40 PM PDT 24 284822520 ps
T322 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1410623106 Apr 15 03:35:42 PM PDT 24 Apr 15 03:35:43 PM PDT 24 1242350820 ps
T68 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3769224647 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:24 PM PDT 24 13493861079 ps
T323 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2764320708 Apr 15 03:35:43 PM PDT 24 Apr 15 03:35:45 PM PDT 24 507930867 ps
T69 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4008682728 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:18 PM PDT 24 409724498 ps
T324 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3142701395 Apr 15 03:35:28 PM PDT 24 Apr 15 03:35:30 PM PDT 24 288800580 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1446045265 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:08 PM PDT 24 426560537 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3333075757 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:13 PM PDT 24 2530348353 ps
T73 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2464000485 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:13 PM PDT 24 1124195054 ps
T326 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3137869673 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:41 PM PDT 24 2657074223 ps
T327 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2155630386 Apr 15 03:35:46 PM PDT 24 Apr 15 03:35:48 PM PDT 24 513088458 ps
T328 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2678730516 Apr 15 03:35:36 PM PDT 24 Apr 15 03:35:39 PM PDT 24 396064594 ps
T329 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2476166595 Apr 15 03:35:20 PM PDT 24 Apr 15 03:35:21 PM PDT 24 494818704 ps
T330 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1504076167 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:20 PM PDT 24 357277691 ps
T331 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1440510471 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:37 PM PDT 24 2727974395 ps
T332 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.900892449 Apr 15 03:35:43 PM PDT 24 Apr 15 03:35:44 PM PDT 24 285819686 ps
T333 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2333031261 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:36 PM PDT 24 461505555 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3841035646 Apr 15 03:35:05 PM PDT 24 Apr 15 03:35:07 PM PDT 24 1116648538 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3412407270 Apr 15 03:35:04 PM PDT 24 Apr 15 03:35:07 PM PDT 24 359230515 ps
T335 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.287975058 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:34 PM PDT 24 959971675 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.938565822 Apr 15 03:35:19 PM PDT 24 Apr 15 03:35:21 PM PDT 24 428477041 ps
T337 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.858149530 Apr 15 03:35:09 PM PDT 24 Apr 15 03:35:11 PM PDT 24 470790982 ps
T107 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3036530877 Apr 15 03:35:26 PM PDT 24 Apr 15 03:35:41 PM PDT 24 8685156215 ps
T338 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3026428686 Apr 15 03:35:33 PM PDT 24 Apr 15 03:35:34 PM PDT 24 498509465 ps
T339 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2362737127 Apr 15 03:35:23 PM PDT 24 Apr 15 03:35:28 PM PDT 24 4410626866 ps
T340 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3790481846 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:23 PM PDT 24 13844373261 ps
T341 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.540496675 Apr 15 03:35:42 PM PDT 24 Apr 15 03:35:44 PM PDT 24 300716484 ps
T342 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3283773563 Apr 15 03:35:10 PM PDT 24 Apr 15 03:35:12 PM PDT 24 408165435 ps
T343 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1436119293 Apr 15 03:35:43 PM PDT 24 Apr 15 03:35:45 PM PDT 24 330424192 ps
T344 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.915931031 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:33 PM PDT 24 457122106 ps
T345 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1953176830 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:37 PM PDT 24 318954986 ps
T346 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.78534535 Apr 15 03:35:28 PM PDT 24 Apr 15 03:35:29 PM PDT 24 476951838 ps
T347 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3362166809 Apr 15 03:35:28 PM PDT 24 Apr 15 03:35:31 PM PDT 24 512024662 ps
T348 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4133570424 Apr 15 03:35:26 PM PDT 24 Apr 15 03:35:28 PM PDT 24 605534161 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.891511547 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:46 PM PDT 24 8391919163 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2914757365 Apr 15 03:35:27 PM PDT 24 Apr 15 03:35:28 PM PDT 24 547412688 ps
T351 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1953394113 Apr 15 03:35:17 PM PDT 24 Apr 15 03:35:19 PM PDT 24 295064602 ps
T109 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2491637108 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:21 PM PDT 24 8975782022 ps
T352 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.273112763 Apr 15 03:35:22 PM PDT 24 Apr 15 03:35:24 PM PDT 24 531258178 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3719381261 Apr 15 03:35:09 PM PDT 24 Apr 15 03:35:12 PM PDT 24 523925008 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4291395824 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:36 PM PDT 24 690765584 ps
T355 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1979534487 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:42 PM PDT 24 512291520 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1634678995 Apr 15 03:35:19 PM PDT 24 Apr 15 03:35:20 PM PDT 24 574317141 ps
T357 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.756452110 Apr 15 03:35:24 PM PDT 24 Apr 15 03:35:27 PM PDT 24 1383589773 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1434337238 Apr 15 03:35:09 PM PDT 24 Apr 15 03:35:11 PM PDT 24 513865896 ps
T359 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1570729621 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:41 PM PDT 24 494124659 ps
T360 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.227268083 Apr 15 03:35:23 PM PDT 24 Apr 15 03:35:24 PM PDT 24 472572272 ps
T361 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.857672970 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:36 PM PDT 24 438912411 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2769745721 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:09 PM PDT 24 796675300 ps
T363 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1321519096 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:18 PM PDT 24 323260825 ps
T364 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3830278771 Apr 15 03:35:44 PM PDT 24 Apr 15 03:35:46 PM PDT 24 480137967 ps
T365 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2753086623 Apr 15 03:35:41 PM PDT 24 Apr 15 03:35:43 PM PDT 24 459330709 ps
T366 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2719858847 Apr 15 03:35:05 PM PDT 24 Apr 15 03:35:06 PM PDT 24 434175320 ps
T75 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3985977527 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:36 PM PDT 24 499469115 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.867763115 Apr 15 03:35:12 PM PDT 24 Apr 15 03:35:15 PM PDT 24 411902775 ps
T368 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.211152037 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:38 PM PDT 24 2402777036 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1546749593 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:10 PM PDT 24 459178266 ps
T370 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3858325632 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:41 PM PDT 24 289383388 ps
T371 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2768668915 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:36 PM PDT 24 417807017 ps
T110 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.789407593 Apr 15 03:35:23 PM PDT 24 Apr 15 03:35:32 PM PDT 24 8500058193 ps
T372 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1248835934 Apr 15 03:35:31 PM PDT 24 Apr 15 03:35:35 PM PDT 24 1967098520 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3061353147 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:14 PM PDT 24 4748356124 ps
T374 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3790257848 Apr 15 03:35:23 PM PDT 24 Apr 15 03:35:30 PM PDT 24 4290285059 ps
T375 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.868426148 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:31 PM PDT 24 1129442855 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.55000700 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:09 PM PDT 24 296428482 ps
T377 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.855318022 Apr 15 03:35:41 PM PDT 24 Apr 15 03:35:42 PM PDT 24 414056423 ps
T378 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1134307443 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:39 PM PDT 24 399177371 ps
T76 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3909082057 Apr 15 03:35:15 PM PDT 24 Apr 15 03:35:27 PM PDT 24 14005019697 ps
T379 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2031209791 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:42 PM PDT 24 467481934 ps
T380 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.175360917 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:40 PM PDT 24 422065600 ps
T381 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.388076003 Apr 15 03:35:25 PM PDT 24 Apr 15 03:35:26 PM PDT 24 364879865 ps
T382 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1765858362 Apr 15 03:35:04 PM PDT 24 Apr 15 03:35:06 PM PDT 24 491079878 ps
T383 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2119489782 Apr 15 03:35:48 PM PDT 24 Apr 15 03:35:49 PM PDT 24 380406329 ps
T384 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2480919129 Apr 15 03:35:46 PM PDT 24 Apr 15 03:35:47 PM PDT 24 345419462 ps
T385 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3932755352 Apr 15 03:35:43 PM PDT 24 Apr 15 03:35:44 PM PDT 24 420017810 ps
T386 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2933111294 Apr 15 03:35:22 PM PDT 24 Apr 15 03:35:25 PM PDT 24 2869933293 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1298355993 Apr 15 03:35:14 PM PDT 24 Apr 15 03:35:15 PM PDT 24 302761926 ps
T388 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2014984291 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:40 PM PDT 24 469589134 ps
T389 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1587611681 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:31 PM PDT 24 374898470 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3358892173 Apr 15 03:35:25 PM PDT 24 Apr 15 03:35:27 PM PDT 24 5168801752 ps
T391 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1719527720 Apr 15 03:35:21 PM PDT 24 Apr 15 03:35:22 PM PDT 24 389749662 ps
T392 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.715843472 Apr 15 03:35:24 PM PDT 24 Apr 15 03:35:25 PM PDT 24 563694117 ps
T393 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2819146748 Apr 15 03:35:39 PM PDT 24 Apr 15 03:35:40 PM PDT 24 517473718 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.964969724 Apr 15 03:35:31 PM PDT 24 Apr 15 03:35:33 PM PDT 24 499090229 ps
T395 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1143645259 Apr 15 03:35:29 PM PDT 24 Apr 15 03:35:31 PM PDT 24 461719294 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.206624376 Apr 15 03:35:07 PM PDT 24 Apr 15 03:35:15 PM PDT 24 8654240080 ps
T397 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.329705154 Apr 15 03:35:15 PM PDT 24 Apr 15 03:35:16 PM PDT 24 624557586 ps
T398 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.961545599 Apr 15 03:35:44 PM PDT 24 Apr 15 03:35:45 PM PDT 24 287686502 ps
T399 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4253106148 Apr 15 03:35:28 PM PDT 24 Apr 15 03:35:31 PM PDT 24 4195323030 ps
T400 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2936088131 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:42 PM PDT 24 443392939 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2881628920 Apr 15 03:35:20 PM PDT 24 Apr 15 03:35:21 PM PDT 24 453514855 ps
T402 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2688740487 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:17 PM PDT 24 352235853 ps
T403 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2203385625 Apr 15 03:35:40 PM PDT 24 Apr 15 03:35:41 PM PDT 24 357249755 ps
T404 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.664267272 Apr 15 03:35:20 PM PDT 24 Apr 15 03:35:23 PM PDT 24 512722687 ps
T405 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1073182878 Apr 15 03:35:35 PM PDT 24 Apr 15 03:35:38 PM PDT 24 1174067939 ps
T406 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2265718147 Apr 15 03:35:32 PM PDT 24 Apr 15 03:35:33 PM PDT 24 395089961 ps
T407 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.924369797 Apr 15 03:35:11 PM PDT 24 Apr 15 03:35:13 PM PDT 24 406814340 ps
T408 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3799867081 Apr 15 03:35:16 PM PDT 24 Apr 15 03:35:19 PM PDT 24 893255561 ps
T409 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2826814118 Apr 15 03:35:34 PM PDT 24 Apr 15 03:35:35 PM PDT 24 443210530 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.695127143 Apr 15 03:35:06 PM PDT 24 Apr 15 03:35:09 PM PDT 24 7353023111 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2801143317 Apr 15 03:35:05 PM PDT 24 Apr 15 03:35:08 PM PDT 24 513919847 ps
T412 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3831469735 Apr 15 03:35:18 PM PDT 24 Apr 15 03:35:21 PM PDT 24 1297780830 ps
T413 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.630330873 Apr 15 03:35:08 PM PDT 24 Apr 15 03:35:09 PM PDT 24 302942197 ps
T414 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3458317562 Apr 15 03:35:38 PM PDT 24 Apr 15 03:35:52 PM PDT 24 8978205734 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3511388832 Apr 15 03:35:26 PM PDT 24 Apr 15 03:35:29 PM PDT 24 350668761 ps
T416 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3271351221 Apr 15 03:35:12 PM PDT 24 Apr 15 03:35:17 PM PDT 24 2442346645 ps
T417 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1958881159 Apr 15 03:35:22 PM PDT 24 Apr 15 03:35:25 PM PDT 24 600408310 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3289078881 Apr 15 03:35:13 PM PDT 24 Apr 15 03:35:14 PM PDT 24 295695432 ps
T419 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2461775996 Apr 15 03:35:43 PM PDT 24 Apr 15 03:35:45 PM PDT 24 439544629 ps
T420 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3689110717 Apr 15 03:35:30 PM PDT 24 Apr 15 03:35:44 PM PDT 24 8147967666 ps

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2281285336
Short name T8
Test name
Test status
Simulation time 78102691238 ps
CPU time 264.92 seconds
Started Apr 15 12:30:04 PM PDT 24
Finished Apr 15 12:34:29 PM PDT 24
Peak memory 198092 kb
Host smart-9b74fc94-63b6-46dc-8c8e-a2c462c4d546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281285336 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2281285336
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.688461007
Short name T20
Test name
Test status
Simulation time 66530003930 ps
CPU time 193.74 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 198204 kb
Host smart-4f36da44-e8d6-4379-a936-5746cd5fb47b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688461007 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.688461007
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3171835282
Short name T43
Test name
Test status
Simulation time 7869853260 ps
CPU time 3.95 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 198408 kb
Host smart-f8fbc643-a569-4f50-8ffe-fe111e4763dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171835282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3171835282
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3256689513
Short name T19
Test name
Test status
Simulation time 188251064271 ps
CPU time 1257.87 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:49:20 PM PDT 24
Peak memory 206132 kb
Host smart-a18b7cec-3e0b-47e4-a9d5-fbd6cf0938a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256689513 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3256689513
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2046788483
Short name T38
Test name
Test status
Simulation time 537306342 ps
CPU time 0.8 seconds
Started Apr 15 03:35:17 PM PDT 24
Finished Apr 15 03:35:18 PM PDT 24
Peak memory 193456 kb
Host smart-06311279-9896-4354-b188-536da2d0d036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046788483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2046788483
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3060702016
Short name T11
Test name
Test status
Simulation time 132296869411 ps
CPU time 189.25 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:31:34 PM PDT 24
Peak memory 194616 kb
Host smart-12f622a9-6612-47fb-90f4-b5f23c16b9b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060702016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3060702016
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.813514436
Short name T24
Test name
Test status
Simulation time 7867572489 ps
CPU time 2.93 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:27:49 PM PDT 24
Peak memory 215028 kb
Host smart-69cb6de1-334a-46cd-937a-c0c9cf99f523
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813514436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.813514436
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2782925855
Short name T28
Test name
Test status
Simulation time 341101155660 ps
CPU time 343.35 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:34:08 PM PDT 24
Peak memory 198096 kb
Host smart-a5cfa36f-576b-44f4-8f67-619f940d6755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782925855 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2782925855
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3769224647
Short name T68
Test name
Test status
Simulation time 13493861079 ps
CPU time 16.08 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:24 PM PDT 24
Peak memory 192516 kb
Host smart-60ea3b26-bde2-4c57-9543-02f8cd62b438
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769224647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3769224647
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.206624376
Short name T396
Test name
Test status
Simulation time 8654240080 ps
CPU time 6.91 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 198336 kb
Host smart-4dd0c52d-7517-4179-994e-5059a6b36cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206624376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.206624376
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2754017887
Short name T108
Test name
Test status
Simulation time 8592278493 ps
CPU time 4.3 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 198308 kb
Host smart-2318c82c-18cb-4f79-81bb-248a971d78f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754017887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2754017887
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.159830221
Short name T67
Test name
Test status
Simulation time 570203165 ps
CPU time 1.44 seconds
Started Apr 15 03:35:05 PM PDT 24
Finished Apr 15 03:35:07 PM PDT 24
Peak memory 194556 kb
Host smart-0ac1b32a-d3ff-4a4a-be6f-1c14ef09b370
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159830221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.159830221
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3841035646
Short name T74
Test name
Test status
Simulation time 1116648538 ps
CPU time 0.8 seconds
Started Apr 15 03:35:05 PM PDT 24
Finished Apr 15 03:35:07 PM PDT 24
Peak memory 184056 kb
Host smart-b45fc1bd-add8-4aba-b1b8-9f952db26d53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841035646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3841035646
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2801143317
Short name T411
Test name
Test status
Simulation time 513919847 ps
CPU time 1.52 seconds
Started Apr 15 03:35:05 PM PDT 24
Finished Apr 15 03:35:08 PM PDT 24
Peak memory 196684 kb
Host smart-e3fde111-27b3-4feb-a1cd-25a9b205dc19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801143317 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2801143317
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2909971192
Short name T307
Test name
Test status
Simulation time 546019192 ps
CPU time 0.77 seconds
Started Apr 15 03:35:03 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 183964 kb
Host smart-52bbbb8b-d2ad-40da-a08f-9bc0e9ef945d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909971192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2909971192
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.4135558736
Short name T310
Test name
Test status
Simulation time 404095961 ps
CPU time 1.11 seconds
Started Apr 15 03:35:03 PM PDT 24
Finished Apr 15 03:35:05 PM PDT 24
Peak memory 183896 kb
Host smart-f8c691d9-ccdc-46a7-b8bd-f449809c94ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135558736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.4135558736
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2719858847
Short name T366
Test name
Test status
Simulation time 434175320 ps
CPU time 0.73 seconds
Started Apr 15 03:35:05 PM PDT 24
Finished Apr 15 03:35:06 PM PDT 24
Peak memory 183876 kb
Host smart-ebc35a56-8bed-423f-8803-a23d227d4765
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719858847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2719858847
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.55000700
Short name T376
Test name
Test status
Simulation time 296428482 ps
CPU time 0.95 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 183888 kb
Host smart-58f9cfae-16f0-46e2-8306-7a898eb0cd50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55000700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wal
k.55000700
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3054168408
Short name T84
Test name
Test status
Simulation time 1514137080 ps
CPU time 1.1 seconds
Started Apr 15 03:35:04 PM PDT 24
Finished Apr 15 03:35:06 PM PDT 24
Peak memory 193716 kb
Host smart-322c261d-6d7f-40b1-b074-4cb852a3a8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054168408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3054168408
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.20630517
Short name T303
Test name
Test status
Simulation time 484842738 ps
CPU time 2.19 seconds
Started Apr 15 03:35:01 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 198844 kb
Host smart-dfec0eab-a116-4c02-ab9c-992c6c8b2093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20630517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.20630517
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3629003284
Short name T37
Test name
Test status
Simulation time 644618028 ps
CPU time 1.02 seconds
Started Apr 15 03:35:06 PM PDT 24
Finished Apr 15 03:35:08 PM PDT 24
Peak memory 192224 kb
Host smart-0605a62e-4176-4f4d-89ae-6d9531f60b25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629003284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3629003284
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.695127143
Short name T410
Test name
Test status
Simulation time 7353023111 ps
CPU time 2.37 seconds
Started Apr 15 03:35:06 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 195948 kb
Host smart-b1ba5961-c45e-4e56-a8ef-09e58a1ade60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695127143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.695127143
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2769745721
Short name T362
Test name
Test status
Simulation time 796675300 ps
CPU time 0.9 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 184048 kb
Host smart-beee3e62-28b5-4771-b831-a11b9730cbd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769745721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2769745721
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1546749593
Short name T369
Test name
Test status
Simulation time 459178266 ps
CPU time 0.98 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:10 PM PDT 24
Peak memory 195200 kb
Host smart-85aeea05-8459-4f84-b465-9dd0f6a85ef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546749593 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1546749593
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.630330873
Short name T413
Test name
Test status
Simulation time 302942197 ps
CPU time 0.65 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 183972 kb
Host smart-bcb5b02a-b69f-4592-a6b2-d56f07ae904b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630330873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.630330873
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1765858362
Short name T382
Test name
Test status
Simulation time 491079878 ps
CPU time 1.25 seconds
Started Apr 15 03:35:04 PM PDT 24
Finished Apr 15 03:35:06 PM PDT 24
Peak memory 183836 kb
Host smart-41466c4c-cd8c-4a12-a471-9815d50d8661
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765858362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1765858362
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1199631638
Short name T289
Test name
Test status
Simulation time 478582140 ps
CPU time 0.66 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 183884 kb
Host smart-940c142e-05b5-4054-ae9e-4a5c28c221b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199631638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1199631638
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3766538597
Short name T286
Test name
Test status
Simulation time 368847585 ps
CPU time 0.63 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 183880 kb
Host smart-9a38e398-5564-451b-8356-f960bb7164e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766538597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3766538597
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3333075757
Short name T325
Test name
Test status
Simulation time 2530348353 ps
CPU time 5.86 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 194744 kb
Host smart-81456f7f-b0e2-4a59-9294-d000a569b55d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333075757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3333075757
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3412407270
Short name T334
Test name
Test status
Simulation time 359230515 ps
CPU time 2.44 seconds
Started Apr 15 03:35:04 PM PDT 24
Finished Apr 15 03:35:07 PM PDT 24
Peak memory 198920 kb
Host smart-68309603-dac9-484e-b2d6-18b5756a8453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412407270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3412407270
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4133570424
Short name T348
Test name
Test status
Simulation time 605534161 ps
CPU time 1.58 seconds
Started Apr 15 03:35:26 PM PDT 24
Finished Apr 15 03:35:28 PM PDT 24
Peak memory 196436 kb
Host smart-14490e84-5c8a-4831-9ef5-269f161d2594
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133570424 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4133570424
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2074139026
Short name T65
Test name
Test status
Simulation time 424421615 ps
CPU time 0.74 seconds
Started Apr 15 03:35:24 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 193392 kb
Host smart-1e2249e7-38eb-4b24-b3bf-3ec4e0e221c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074139026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2074139026
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.1719527720
Short name T391
Test name
Test status
Simulation time 389749662 ps
CPU time 0.58 seconds
Started Apr 15 03:35:21 PM PDT 24
Finished Apr 15 03:35:22 PM PDT 24
Peak memory 183992 kb
Host smart-9bf7195d-3553-439b-a525-9436a891c97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719527720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.1719527720
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.287975058
Short name T335
Test name
Test status
Simulation time 959971675 ps
CPU time 2.45 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:34 PM PDT 24
Peak memory 184104 kb
Host smart-0c69bee4-c033-4a51-8557-4c8618fb884e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287975058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.287975058
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.664267272
Short name T404
Test name
Test status
Simulation time 512722687 ps
CPU time 2.18 seconds
Started Apr 15 03:35:20 PM PDT 24
Finished Apr 15 03:35:23 PM PDT 24
Peak memory 198824 kb
Host smart-a1330fbe-e751-451c-ae9d-32c5cfa271f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664267272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.664267272
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2362737127
Short name T339
Test name
Test status
Simulation time 4410626866 ps
CPU time 4.87 seconds
Started Apr 15 03:35:23 PM PDT 24
Finished Apr 15 03:35:28 PM PDT 24
Peak memory 197824 kb
Host smart-ac6b69c2-4709-4892-a663-d77a615189ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362737127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2362737127
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.227268083
Short name T360
Test name
Test status
Simulation time 472572272 ps
CPU time 0.87 seconds
Started Apr 15 03:35:23 PM PDT 24
Finished Apr 15 03:35:24 PM PDT 24
Peak memory 195932 kb
Host smart-a07723c4-93bc-477f-a946-51811e17069b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227268083 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.227268083
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.915931031
Short name T344
Test name
Test status
Simulation time 457122106 ps
CPU time 0.72 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 193276 kb
Host smart-7b5fb572-4f74-4227-840f-6e281fdc8e69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915931031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.915931031
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1746334272
Short name T315
Test name
Test status
Simulation time 455551372 ps
CPU time 0.88 seconds
Started Apr 15 03:35:26 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 183976 kb
Host smart-57fa8fe2-01cf-427f-b831-7c8e1deff69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746334272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1746334272
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1440510471
Short name T331
Test name
Test status
Simulation time 2727974395 ps
CPU time 4.54 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:37 PM PDT 24
Peak memory 195120 kb
Host smart-7f44c768-4fae-4351-b28e-df854bd9d953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440510471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1440510471
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3511388832
Short name T415
Test name
Test status
Simulation time 350668761 ps
CPU time 2.3 seconds
Started Apr 15 03:35:26 PM PDT 24
Finished Apr 15 03:35:29 PM PDT 24
Peak memory 198900 kb
Host smart-f921dca4-1f38-4a25-940b-ee239f1a057b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511388832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3511388832
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3358892173
Short name T390
Test name
Test status
Simulation time 5168801752 ps
CPU time 1.51 seconds
Started Apr 15 03:35:25 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 196740 kb
Host smart-e6dbc705-7416-4c03-8a39-cfdcd64450be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358892173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3358892173
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1143645259
Short name T395
Test name
Test status
Simulation time 461719294 ps
CPU time 1.39 seconds
Started Apr 15 03:35:29 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 196152 kb
Host smart-1535ff3d-6e46-4944-9e46-ff8aa4efc24d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143645259 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1143645259
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4266109651
Short name T39
Test name
Test status
Simulation time 501672185 ps
CPU time 1.3 seconds
Started Apr 15 03:35:33 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 193424 kb
Host smart-62f14b77-e002-4b0d-bb09-d0b8ba34b989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266109651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4266109651
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.157302992
Short name T316
Test name
Test status
Simulation time 273023095 ps
CPU time 0.99 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 183956 kb
Host smart-187d67b8-9cd5-4fc3-94d2-ec8e98d7f87c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157302992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.157302992
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1248835934
Short name T372
Test name
Test status
Simulation time 1967098520 ps
CPU time 3.52 seconds
Started Apr 15 03:35:31 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 194656 kb
Host smart-68d5c7bd-0402-44c4-9887-7656d1cf378c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248835934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1248835934
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.756452110
Short name T357
Test name
Test status
Simulation time 1383589773 ps
CPU time 1.59 seconds
Started Apr 15 03:35:24 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 198840 kb
Host smart-2d4ad8ce-9fee-481b-9b0e-58a833dac260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756452110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.756452110
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3790257848
Short name T374
Test name
Test status
Simulation time 4290285059 ps
CPU time 6.79 seconds
Started Apr 15 03:35:23 PM PDT 24
Finished Apr 15 03:35:30 PM PDT 24
Peak memory 197624 kb
Host smart-55bbbf3b-2ef0-4575-b481-119857eb2d63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790257848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3790257848
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2914757365
Short name T350
Test name
Test status
Simulation time 547412688 ps
CPU time 0.65 seconds
Started Apr 15 03:35:27 PM PDT 24
Finished Apr 15 03:35:28 PM PDT 24
Peak memory 196132 kb
Host smart-e1ef62c1-aa68-4ea3-a54b-0750cc3c0a09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914757365 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2914757365
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3142701395
Short name T324
Test name
Test status
Simulation time 288800580 ps
CPU time 0.96 seconds
Started Apr 15 03:35:28 PM PDT 24
Finished Apr 15 03:35:30 PM PDT 24
Peak memory 184204 kb
Host smart-2a265755-bd8d-453e-aaf4-31053738f58c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142701395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3142701395
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1587611681
Short name T389
Test name
Test status
Simulation time 374898470 ps
CPU time 0.66 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 183988 kb
Host smart-ad4e6f31-fcf6-40e3-a0f8-652074f5681c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587611681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1587611681
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.291266129
Short name T78
Test name
Test status
Simulation time 2356372701 ps
CPU time 5.15 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 195008 kb
Host smart-d1cb0d5e-ebc1-402f-b63b-7af1d2745c1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291266129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.291266129
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2085322451
Short name T287
Test name
Test status
Simulation time 756153666 ps
CPU time 2.56 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 198824 kb
Host smart-063f4ad0-3eb1-498c-81f7-0706279fa51e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085322451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2085322451
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2099857514
Short name T317
Test name
Test status
Simulation time 4547223561 ps
CPU time 6 seconds
Started Apr 15 03:35:29 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 196568 kb
Host smart-c8c774e1-e0d6-4093-b886-63eb3674818b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099857514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2099857514
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.78534535
Short name T346
Test name
Test status
Simulation time 476951838 ps
CPU time 1.29 seconds
Started Apr 15 03:35:28 PM PDT 24
Finished Apr 15 03:35:29 PM PDT 24
Peak memory 196088 kb
Host smart-22ae09b4-0739-4e81-98e6-979521b423a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78534535 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.78534535
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2265718147
Short name T406
Test name
Test status
Simulation time 395089961 ps
CPU time 0.79 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 193324 kb
Host smart-d9a49b45-cc99-4067-96a1-544afc14b6a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265718147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2265718147
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1714484506
Short name T285
Test name
Test status
Simulation time 505207670 ps
CPU time 0.88 seconds
Started Apr 15 03:35:33 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 183916 kb
Host smart-5c04d8bc-b17e-4a0c-9884-a25e7f61c3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714484506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1714484506
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1115743792
Short name T79
Test name
Test status
Simulation time 2824609304 ps
CPU time 2.2 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 194940 kb
Host smart-919609d4-304d-40bb-ac16-501cfdc012c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115743792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1115743792
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3362166809
Short name T347
Test name
Test status
Simulation time 512024662 ps
CPU time 1.7 seconds
Started Apr 15 03:35:28 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 198892 kb
Host smart-5ef8e915-ffdc-4444-a0d9-9468e05c4656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362166809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3362166809
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3689110717
Short name T420
Test name
Test status
Simulation time 8147967666 ps
CPU time 13.15 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:44 PM PDT 24
Peak memory 198320 kb
Host smart-c917081f-615c-4e08-a008-be0cae9a4136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689110717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3689110717
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2333031261
Short name T333
Test name
Test status
Simulation time 461505555 ps
CPU time 0.79 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 196112 kb
Host smart-90be95bc-bbf6-4474-b2e0-83899e18e4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333031261 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2333031261
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.964969724
Short name T394
Test name
Test status
Simulation time 499090229 ps
CPU time 1.26 seconds
Started Apr 15 03:35:31 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 183988 kb
Host smart-effece49-da9d-4286-8f68-7993eb723172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964969724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.964969724
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1953176830
Short name T345
Test name
Test status
Simulation time 318954986 ps
CPU time 0.67 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:37 PM PDT 24
Peak memory 183948 kb
Host smart-f6ef2c85-1ece-486c-9e4f-96b0c5b98504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953176830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1953176830
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1073182878
Short name T405
Test name
Test status
Simulation time 1174067939 ps
CPU time 1.99 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:38 PM PDT 24
Peak memory 184036 kb
Host smart-387212f1-b934-4ccc-b5e5-c9c04a70381a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073182878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1073182878
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1866023414
Short name T280
Test name
Test status
Simulation time 423175159 ps
CPU time 1.33 seconds
Started Apr 15 03:35:29 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 198848 kb
Host smart-c8579fc6-8871-40b7-b0c6-d1c2cda7c440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866023414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1866023414
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4253106148
Short name T399
Test name
Test status
Simulation time 4195323030 ps
CPU time 1.9 seconds
Started Apr 15 03:35:28 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 197960 kb
Host smart-3c7f716e-3194-43a0-b021-c87adacee623
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253106148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4253106148
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3308581753
Short name T300
Test name
Test status
Simulation time 531415319 ps
CPU time 1.44 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 197040 kb
Host smart-684fa1fb-5b3c-4fcb-a7f9-149d92359d2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308581753 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3308581753
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3026428686
Short name T338
Test name
Test status
Simulation time 498509465 ps
CPU time 0.63 seconds
Started Apr 15 03:35:33 PM PDT 24
Finished Apr 15 03:35:34 PM PDT 24
Peak memory 193464 kb
Host smart-34335933-1af3-4e74-a72c-cd1f433aedaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026428686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3026428686
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.4123593450
Short name T306
Test name
Test status
Simulation time 354350555 ps
CPU time 0.79 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 183948 kb
Host smart-3f06be30-ed0c-48de-8fb8-b3ab24f3bb3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123593450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.4123593450
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3553759378
Short name T82
Test name
Test status
Simulation time 2503460858 ps
CPU time 1.4 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 195020 kb
Host smart-6e2a495a-af40-455d-8149-ba411c5be332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553759378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3553759378
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1079068323
Short name T288
Test name
Test status
Simulation time 399090920 ps
CPU time 2.16 seconds
Started Apr 15 03:35:37 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 198856 kb
Host smart-a44b1e67-b10c-4fc3-af72-66ae94d6e382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079068323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1079068323
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.891511547
Short name T349
Test name
Test status
Simulation time 8391919163 ps
CPU time 13.95 seconds
Started Apr 15 03:35:32 PM PDT 24
Finished Apr 15 03:35:46 PM PDT 24
Peak memory 198380 kb
Host smart-379cf5d5-f363-435c-ad86-d46e70475023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891511547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.891511547
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.2768668915
Short name T371
Test name
Test status
Simulation time 417807017 ps
CPU time 0.82 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 196912 kb
Host smart-92c05aed-492e-4771-85d7-1d46281d8d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768668915 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.2768668915
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3985977527
Short name T75
Test name
Test status
Simulation time 499469115 ps
CPU time 0.72 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 193268 kb
Host smart-a47d494b-858c-4d5e-b893-dacd7826182c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985977527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3985977527
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2826814118
Short name T409
Test name
Test status
Simulation time 443210530 ps
CPU time 0.88 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 183944 kb
Host smart-b63d6444-ed9e-436c-9a40-985ca8aa33ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826814118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2826814118
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3137869673
Short name T326
Test name
Test status
Simulation time 2657074223 ps
CPU time 5.5 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 195104 kb
Host smart-91254436-5ae6-4799-a224-3e458d14f76d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137869673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3137869673
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2678730516
Short name T328
Test name
Test status
Simulation time 396064594 ps
CPU time 1.46 seconds
Started Apr 15 03:35:36 PM PDT 24
Finished Apr 15 03:35:39 PM PDT 24
Peak memory 198864 kb
Host smart-b5845daa-4094-40e7-90c9-7fe576dcd447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678730516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2678730516
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3458317562
Short name T414
Test name
Test status
Simulation time 8978205734 ps
CPU time 13.27 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:52 PM PDT 24
Peak memory 198128 kb
Host smart-7b8e5394-04cc-48b9-aa1c-b0a9e6e771b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458317562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3458317562
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.175360917
Short name T380
Test name
Test status
Simulation time 422065600 ps
CPU time 0.82 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 196712 kb
Host smart-e21b1d49-66c1-4589-9de8-6411b41022c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175360917 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.175360917
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.803544708
Short name T321
Test name
Test status
Simulation time 284822520 ps
CPU time 0.94 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 192224 kb
Host smart-2468f317-2507-4525-bba7-dcd77d90eb24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803544708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.803544708
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2819146748
Short name T393
Test name
Test status
Simulation time 517473718 ps
CPU time 0.85 seconds
Started Apr 15 03:35:39 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 183940 kb
Host smart-d8d2332c-a0c0-484d-8768-2ca777b2b1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819146748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2819146748
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1410623106
Short name T322
Test name
Test status
Simulation time 1242350820 ps
CPU time 1.15 seconds
Started Apr 15 03:35:42 PM PDT 24
Finished Apr 15 03:35:43 PM PDT 24
Peak memory 193740 kb
Host smart-3081e882-b5d7-48a6-9856-476b40c5d6b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410623106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1410623106
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1744410170
Short name T320
Test name
Test status
Simulation time 403862601 ps
CPU time 2.62 seconds
Started Apr 15 03:35:36 PM PDT 24
Finished Apr 15 03:35:39 PM PDT 24
Peak memory 198832 kb
Host smart-22393919-5f86-4d9a-a66d-14a95d9a7b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744410170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1744410170
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.207214324
Short name T106
Test name
Test status
Simulation time 8242188453 ps
CPU time 13.46 seconds
Started Apr 15 03:35:37 PM PDT 24
Finished Apr 15 03:35:51 PM PDT 24
Peak memory 198164 kb
Host smart-b0f93289-e8d1-44d4-8b59-300e9218c5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207214324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.207214324
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1328865011
Short name T301
Test name
Test status
Simulation time 713537462 ps
CPU time 1.15 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:37 PM PDT 24
Peak memory 198768 kb
Host smart-713857b5-4dce-4f39-a74e-0107431eae5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328865011 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1328865011
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1713626949
Short name T112
Test name
Test status
Simulation time 486631744 ps
CPU time 0.83 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 193340 kb
Host smart-2e47ddfc-a57c-466b-af26-9ff3aaf19b35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713626949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1713626949
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.857672970
Short name T361
Test name
Test status
Simulation time 438912411 ps
CPU time 1.15 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 183956 kb
Host smart-890bcc9e-b1de-403d-b5d4-225134a1386b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857672970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.857672970
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.211152037
Short name T368
Test name
Test status
Simulation time 2402777036 ps
CPU time 2.1 seconds
Started Apr 15 03:35:35 PM PDT 24
Finished Apr 15 03:35:38 PM PDT 24
Peak memory 194852 kb
Host smart-192cde3f-0d4d-4afe-aa16-4e8c4afd4553
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211152037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon
_timer_same_csr_outstanding.211152037
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4291395824
Short name T354
Test name
Test status
Simulation time 690765584 ps
CPU time 1.65 seconds
Started Apr 15 03:35:34 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 198836 kb
Host smart-c5cd581e-7a49-405e-b41c-05950bc514cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291395824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4291395824
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2297750504
Short name T45
Test name
Test status
Simulation time 3893273517 ps
CPU time 2 seconds
Started Apr 15 03:35:37 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 197732 kb
Host smart-bd0a3a03-6fd9-4f90-8285-fc824ee1b8b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297750504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2297750504
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4008682728
Short name T69
Test name
Test status
Simulation time 409724498 ps
CPU time 1.44 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:18 PM PDT 24
Peak memory 183968 kb
Host smart-eeb4ed91-165f-4aec-b888-bb1e58571219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008682728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4008682728
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3790481846
Short name T340
Test name
Test status
Simulation time 13844373261 ps
CPU time 15.2 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:23 PM PDT 24
Peak memory 192468 kb
Host smart-dd841ffe-486c-4065-b690-e4848f87af53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790481846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3790481846
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2784578483
Short name T42
Test name
Test status
Simulation time 1176385894 ps
CPU time 2.04 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:12 PM PDT 24
Peak memory 193480 kb
Host smart-b3f463a6-d3ba-432b-a642-7f5dcee3225b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784578483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2784578483
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1690668433
Short name T111
Test name
Test status
Simulation time 615646598 ps
CPU time 0.9 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 196352 kb
Host smart-1f8eed27-e13c-4ede-9a30-43c1c7f5cb58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690668433 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1690668433
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1446045265
Short name T72
Test name
Test status
Simulation time 426560537 ps
CPU time 0.7 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:08 PM PDT 24
Peak memory 184124 kb
Host smart-0c16c1de-e8fa-4b47-bc75-6f0cb7ae651a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446045265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1446045265
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1271951727
Short name T296
Test name
Test status
Simulation time 475303531 ps
CPU time 0.85 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:10 PM PDT 24
Peak memory 183952 kb
Host smart-4f3b55d0-fcd6-42ca-bb5d-1d5b4447e19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271951727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1271951727
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3283773563
Short name T342
Test name
Test status
Simulation time 408165435 ps
CPU time 0.93 seconds
Started Apr 15 03:35:10 PM PDT 24
Finished Apr 15 03:35:12 PM PDT 24
Peak memory 183828 kb
Host smart-e246d083-3391-4f6c-ae2a-49567f5022e5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283773563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3283773563
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1434337238
Short name T358
Test name
Test status
Simulation time 513865896 ps
CPU time 0.73 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 183852 kb
Host smart-c49054ca-95f0-485c-820a-07658f6b7266
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434337238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1434337238
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3271351221
Short name T416
Test name
Test status
Simulation time 2442346645 ps
CPU time 4.03 seconds
Started Apr 15 03:35:12 PM PDT 24
Finished Apr 15 03:35:17 PM PDT 24
Peak memory 194776 kb
Host smart-05ecf5d7-e5bf-422e-abe8-dd91bbcad03b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271351221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3271351221
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3719381261
Short name T353
Test name
Test status
Simulation time 523925008 ps
CPU time 2.7 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:12 PM PDT 24
Peak memory 198872 kb
Host smart-4e9d8482-dcf6-470f-8022-a1d68616f404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719381261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3719381261
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1118616078
Short name T44
Test name
Test status
Simulation time 4160776845 ps
CPU time 2.48 seconds
Started Apr 15 03:35:07 PM PDT 24
Finished Apr 15 03:35:10 PM PDT 24
Peak memory 196456 kb
Host smart-87e4672a-d602-477e-b18a-4e50e9009efe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118616078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1118616078
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1134307443
Short name T378
Test name
Test status
Simulation time 399177371 ps
CPU time 0.84 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:39 PM PDT 24
Peak memory 183884 kb
Host smart-9c3b09f2-8e13-4326-b9f2-317189325ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134307443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1134307443
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1313207896
Short name T284
Test name
Test status
Simulation time 457068273 ps
CPU time 0.94 seconds
Started Apr 15 03:35:45 PM PDT 24
Finished Apr 15 03:35:46 PM PDT 24
Peak memory 183936 kb
Host smart-37232c5e-4b2a-4497-9ccb-c6667bee3163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313207896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1313207896
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2461775996
Short name T419
Test name
Test status
Simulation time 439544629 ps
CPU time 1.28 seconds
Started Apr 15 03:35:43 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 183940 kb
Host smart-51331b2a-4130-4986-9e4d-a811fca26692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461775996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2461775996
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2977886109
Short name T308
Test name
Test status
Simulation time 331540701 ps
CPU time 0.78 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183956 kb
Host smart-4d4a1254-46e9-482e-acca-d6d7a580e09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977886109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2977886109
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3162112364
Short name T312
Test name
Test status
Simulation time 498670203 ps
CPU time 0.88 seconds
Started Apr 15 03:35:39 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 183976 kb
Host smart-d3f20eb6-783b-4fb1-9dbc-98be2447182e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162112364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3162112364
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2014984291
Short name T388
Test name
Test status
Simulation time 469589134 ps
CPU time 1.19 seconds
Started Apr 15 03:35:38 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 183904 kb
Host smart-602e05f8-ecff-4605-86dd-d0898f0bc291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014984291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2014984291
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2936088131
Short name T400
Test name
Test status
Simulation time 443392939 ps
CPU time 1.23 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183908 kb
Host smart-d225d75e-9533-4c92-bb00-49235d1d3969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936088131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2936088131
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1535851929
Short name T282
Test name
Test status
Simulation time 524282655 ps
CPU time 0.7 seconds
Started Apr 15 03:35:41 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183964 kb
Host smart-7c1c2a85-6eea-44c5-8f65-8a176398dc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535851929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1535851929
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2764320708
Short name T323
Test name
Test status
Simulation time 507930867 ps
CPU time 1.47 seconds
Started Apr 15 03:35:43 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 183940 kb
Host smart-e3e03ce3-9153-4a65-8946-2252a31bef72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764320708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2764320708
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1979534487
Short name T355
Test name
Test status
Simulation time 512291520 ps
CPU time 0.92 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183956 kb
Host smart-85700ffe-1a10-491b-b570-2d737e6dd842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979534487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1979534487
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1096512615
Short name T319
Test name
Test status
Simulation time 582616706 ps
CPU time 1.88 seconds
Started Apr 15 03:35:12 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 183960 kb
Host smart-857e32d9-3f7b-4b37-8ffe-ec0c7783d122
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096512615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1096512615
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1655720992
Short name T66
Test name
Test status
Simulation time 13475826497 ps
CPU time 14.26 seconds
Started Apr 15 03:35:12 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 192328 kb
Host smart-4b9f83f2-c63e-4b18-a682-8de6e85dca2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655720992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1655720992
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2464000485
Short name T73
Test name
Test status
Simulation time 1124195054 ps
CPU time 0.97 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 193460 kb
Host smart-cf4fddfe-92c4-4698-a5ef-ee81ee6733ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464000485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2464000485
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3181697029
Short name T292
Test name
Test status
Simulation time 418847355 ps
CPU time 1.25 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 195956 kb
Host smart-f1b5278f-d9c6-45ff-b23f-fc88f428b944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181697029 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3181697029
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3289078881
Short name T418
Test name
Test status
Simulation time 295695432 ps
CPU time 0.84 seconds
Started Apr 15 03:35:13 PM PDT 24
Finished Apr 15 03:35:14 PM PDT 24
Peak memory 192296 kb
Host smart-2a28acef-a432-4a18-84ec-cd383842637a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289078881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3289078881
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.858149530
Short name T337
Test name
Test status
Simulation time 470790982 ps
CPU time 1.2 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 183952 kb
Host smart-da929aff-c260-4a65-ade0-db5b67c5bf18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858149530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.858149530
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.924369797
Short name T407
Test name
Test status
Simulation time 406814340 ps
CPU time 1 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 183860 kb
Host smart-0cd46ef8-7b9e-4534-b847-1c0f8fb33a55
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924369797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.924369797
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.380119533
Short name T281
Test name
Test status
Simulation time 319415463 ps
CPU time 0.73 seconds
Started Apr 15 03:35:09 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 183888 kb
Host smart-7884f063-e097-4471-8f83-11504ff6c3ac
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380119533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.380119533
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.777410179
Short name T80
Test name
Test status
Simulation time 1418554065 ps
CPU time 3.31 seconds
Started Apr 15 03:35:12 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 193520 kb
Host smart-67c94d12-3277-4aaa-9c13-cc1e04e35d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777410179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.777410179
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2441502554
Short name T313
Test name
Test status
Simulation time 455809636 ps
CPU time 1.72 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:10 PM PDT 24
Peak memory 198572 kb
Host smart-bd9fc4c0-051c-46ce-8ea8-72ea354e62ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441502554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2441502554
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.783478548
Short name T314
Test name
Test status
Simulation time 4580660508 ps
CPU time 4.21 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 197916 kb
Host smart-768e9b15-ca8c-4ac1-a6bf-ad8f12bcd14a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783478548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.783478548
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2203385625
Short name T403
Test name
Test status
Simulation time 357249755 ps
CPU time 0.58 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 183960 kb
Host smart-ab31a8b9-6fac-4055-8be9-4b1f0dc45101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203385625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2203385625
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2753086623
Short name T365
Test name
Test status
Simulation time 459330709 ps
CPU time 1.25 seconds
Started Apr 15 03:35:41 PM PDT 24
Finished Apr 15 03:35:43 PM PDT 24
Peak memory 183940 kb
Host smart-d58cf296-a073-4a45-89c8-10db69dbedfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753086623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2753086623
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.961545599
Short name T398
Test name
Test status
Simulation time 287686502 ps
CPU time 0.75 seconds
Started Apr 15 03:35:44 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 183936 kb
Host smart-c9a0dbbc-1eb2-4add-86cc-690bfb2ef596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961545599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.961545599
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.855318022
Short name T377
Test name
Test status
Simulation time 414056423 ps
CPU time 0.85 seconds
Started Apr 15 03:35:41 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183952 kb
Host smart-1aa711cc-253f-44b2-abf6-0c39449117b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855318022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.855318022
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3858325632
Short name T370
Test name
Test status
Simulation time 289383388 ps
CPU time 0.91 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 183952 kb
Host smart-6f903b09-70d4-4f96-9a77-5b29f9624214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858325632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3858325632
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1807602148
Short name T291
Test name
Test status
Simulation time 553980305 ps
CPU time 0.62 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 183960 kb
Host smart-a91aff77-9b18-4780-a406-0156861f01ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807602148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1807602148
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1570729621
Short name T359
Test name
Test status
Simulation time 494124659 ps
CPU time 0.7 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 183976 kb
Host smart-bab94772-a74b-4380-a49c-a52160bca78a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570729621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1570729621
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2031209791
Short name T379
Test name
Test status
Simulation time 467481934 ps
CPU time 1.21 seconds
Started Apr 15 03:35:40 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183952 kb
Host smart-71dc7dc4-db27-4987-b208-e9ce81095de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031209791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2031209791
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.281281532
Short name T283
Test name
Test status
Simulation time 389395217 ps
CPU time 0.66 seconds
Started Apr 15 03:35:41 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183964 kb
Host smart-a202f07e-dc2e-4b00-9726-c61831c525e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281281532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.281281532
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2480919129
Short name T384
Test name
Test status
Simulation time 345419462 ps
CPU time 1.16 seconds
Started Apr 15 03:35:46 PM PDT 24
Finished Apr 15 03:35:47 PM PDT 24
Peak memory 183908 kb
Host smart-654a5c7e-d2b9-4850-b536-82f375bca6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480919129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2480919129
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2848689629
Short name T318
Test name
Test status
Simulation time 391942607 ps
CPU time 0.87 seconds
Started Apr 15 03:35:14 PM PDT 24
Finished Apr 15 03:35:16 PM PDT 24
Peak memory 193424 kb
Host smart-1c5f404e-780e-4577-92d7-cc228b70a10d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848689629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2848689629
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3909082057
Short name T76
Test name
Test status
Simulation time 14005019697 ps
CPU time 11.43 seconds
Started Apr 15 03:35:15 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 192604 kb
Host smart-c29eb270-21ee-423b-aba8-b6406cac0184
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909082057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3909082057
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3799867081
Short name T408
Test name
Test status
Simulation time 893255561 ps
CPU time 2.03 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 183980 kb
Host smart-bb7c17c8-bb52-4d2e-94a4-4f5bbb743c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799867081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3799867081
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1300922919
Short name T311
Test name
Test status
Simulation time 564966715 ps
CPU time 0.88 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 198352 kb
Host smart-8df5d093-49a1-4238-bf9d-36a87a6626b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300922919 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1300922919
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1298355993
Short name T387
Test name
Test status
Simulation time 302761926 ps
CPU time 0.77 seconds
Started Apr 15 03:35:14 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 193228 kb
Host smart-603a1e09-24c0-4331-86ed-5fc692790cff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298355993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1298355993
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3026230390
Short name T290
Test name
Test status
Simulation time 514161502 ps
CPU time 1.28 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 183936 kb
Host smart-547d2ada-95a9-458f-a973-62b99cb4429a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026230390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3026230390
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4186071563
Short name T293
Test name
Test status
Simulation time 302217819 ps
CPU time 1.02 seconds
Started Apr 15 03:35:14 PM PDT 24
Finished Apr 15 03:35:16 PM PDT 24
Peak memory 183876 kb
Host smart-826ca649-370b-44d4-a63a-e5f5d1d30c89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186071563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4186071563
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1504076167
Short name T330
Test name
Test status
Simulation time 357277691 ps
CPU time 1.08 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 183908 kb
Host smart-c37c064c-5373-4a13-842a-07ea719259cc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504076167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1504076167
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.440736059
Short name T77
Test name
Test status
Simulation time 2905477582 ps
CPU time 2.24 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 184260 kb
Host smart-f6363e97-5cbf-4558-815f-c313be73760d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440736059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.440736059
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.867763115
Short name T367
Test name
Test status
Simulation time 411902775 ps
CPU time 1.52 seconds
Started Apr 15 03:35:12 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 198200 kb
Host smart-de11b63d-d21d-40a3-90b2-0f2d3054afa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867763115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.867763115
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3061353147
Short name T373
Test name
Test status
Simulation time 4748356124 ps
CPU time 2.69 seconds
Started Apr 15 03:35:11 PM PDT 24
Finished Apr 15 03:35:14 PM PDT 24
Peak memory 197788 kb
Host smart-60d00f8f-578e-4799-9e11-fce24d16da33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061353147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3061353147
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.900892449
Short name T332
Test name
Test status
Simulation time 285819686 ps
CPU time 0.65 seconds
Started Apr 15 03:35:43 PM PDT 24
Finished Apr 15 03:35:44 PM PDT 24
Peak memory 183972 kb
Host smart-d9e3c801-35b2-491a-8b5d-19c024977ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900892449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.900892449
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2119489782
Short name T383
Test name
Test status
Simulation time 380406329 ps
CPU time 0.61 seconds
Started Apr 15 03:35:48 PM PDT 24
Finished Apr 15 03:35:49 PM PDT 24
Peak memory 183928 kb
Host smart-76b162c0-c928-4027-a95d-962e6f022687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119489782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2119489782
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3932755352
Short name T385
Test name
Test status
Simulation time 420017810 ps
CPU time 0.78 seconds
Started Apr 15 03:35:43 PM PDT 24
Finished Apr 15 03:35:44 PM PDT 24
Peak memory 183968 kb
Host smart-763ef61a-77e1-4947-9384-51cbc1463d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932755352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3932755352
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3321117215
Short name T294
Test name
Test status
Simulation time 493176148 ps
CPU time 0.68 seconds
Started Apr 15 03:35:41 PM PDT 24
Finished Apr 15 03:35:42 PM PDT 24
Peak memory 183972 kb
Host smart-5e03cf80-c7f4-433c-8c5c-4ab48c0eaefd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321117215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3321117215
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.540496675
Short name T341
Test name
Test status
Simulation time 300716484 ps
CPU time 1.03 seconds
Started Apr 15 03:35:42 PM PDT 24
Finished Apr 15 03:35:44 PM PDT 24
Peak memory 183896 kb
Host smart-3d2288cc-edfd-44b0-a8c4-eaf5e1a05605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540496675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.540496675
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1603064334
Short name T295
Test name
Test status
Simulation time 366524322 ps
CPU time 0.66 seconds
Started Apr 15 03:35:48 PM PDT 24
Finished Apr 15 03:35:49 PM PDT 24
Peak memory 183928 kb
Host smart-a4065ea7-bf82-4b93-9865-5a0872557ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603064334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1603064334
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1436119293
Short name T343
Test name
Test status
Simulation time 330424192 ps
CPU time 1.06 seconds
Started Apr 15 03:35:43 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 183972 kb
Host smart-2bf169be-54bd-48d9-bb7d-08b6c0b7fc50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436119293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1436119293
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2155630386
Short name T327
Test name
Test status
Simulation time 513088458 ps
CPU time 1.27 seconds
Started Apr 15 03:35:46 PM PDT 24
Finished Apr 15 03:35:48 PM PDT 24
Peak memory 183904 kb
Host smart-77d0d0fb-7676-48dc-893e-02a413b7e84f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155630386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2155630386
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3830278771
Short name T364
Test name
Test status
Simulation time 480137967 ps
CPU time 0.7 seconds
Started Apr 15 03:35:44 PM PDT 24
Finished Apr 15 03:35:46 PM PDT 24
Peak memory 183964 kb
Host smart-9b85b313-5676-4bbe-aa96-78b1c1faec72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830278771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3830278771
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2477182411
Short name T297
Test name
Test status
Simulation time 367739805 ps
CPU time 1.01 seconds
Started Apr 15 03:35:44 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 183964 kb
Host smart-49dd7ac4-c4c1-4125-8b13-90e60991a7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477182411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2477182411
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.329705154
Short name T397
Test name
Test status
Simulation time 624557586 ps
CPU time 1 seconds
Started Apr 15 03:35:15 PM PDT 24
Finished Apr 15 03:35:16 PM PDT 24
Peak memory 197532 kb
Host smart-5ed0cfcd-c9f9-4f46-895d-173bfedb319d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329705154 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.329705154
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1321519096
Short name T363
Test name
Test status
Simulation time 323260825 ps
CPU time 0.99 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:18 PM PDT 24
Peak memory 183964 kb
Host smart-a5f6c1ba-dba5-47bb-a596-ab986c05ba7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321519096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1321519096
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2688740487
Short name T402
Test name
Test status
Simulation time 352235853 ps
CPU time 0.66 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:17 PM PDT 24
Peak memory 183948 kb
Host smart-09b21f29-16cb-409e-bb87-608ad6c8b36b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688740487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2688740487
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3831469735
Short name T412
Test name
Test status
Simulation time 1297780830 ps
CPU time 2.33 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 193632 kb
Host smart-1dbc45e2-f38a-4e6c-b6c9-241c26d410c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831469735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3831469735
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1897452467
Short name T304
Test name
Test status
Simulation time 606284124 ps
CPU time 1.28 seconds
Started Apr 15 03:35:15 PM PDT 24
Finished Apr 15 03:35:17 PM PDT 24
Peak memory 198584 kb
Host smart-8259251b-7d31-4e23-a24d-ed97b350a57b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897452467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1897452467
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2881628920
Short name T401
Test name
Test status
Simulation time 453514855 ps
CPU time 0.77 seconds
Started Apr 15 03:35:20 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 195816 kb
Host smart-08b953a1-6737-4036-ace1-caa300ba8749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881628920 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2881628920
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2476166595
Short name T329
Test name
Test status
Simulation time 494818704 ps
CPU time 0.69 seconds
Started Apr 15 03:35:20 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 183988 kb
Host smart-c0583ebe-e4de-49f9-a288-f2783e55dcc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476166595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2476166595
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3584561228
Short name T83
Test name
Test status
Simulation time 1184693795 ps
CPU time 0.8 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 193636 kb
Host smart-ea2b591e-9a57-4b10-91df-a1c6757dc84d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584561228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3584561228
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1958881159
Short name T417
Test name
Test status
Simulation time 600408310 ps
CPU time 2.14 seconds
Started Apr 15 03:35:22 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 198864 kb
Host smart-7f1fe2df-2a61-49e2-b16b-38e15853b929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958881159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1958881159
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3036530877
Short name T107
Test name
Test status
Simulation time 8685156215 ps
CPU time 14.6 seconds
Started Apr 15 03:35:26 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 198264 kb
Host smart-78448be9-5779-4467-ba33-b9bfbcd79ea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036530877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3036530877
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1634678995
Short name T356
Test name
Test status
Simulation time 574317141 ps
CPU time 0.97 seconds
Started Apr 15 03:35:19 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 196628 kb
Host smart-7cddf917-502a-4b42-8288-b5478bb9bbb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634678995 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1634678995
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3559435497
Short name T113
Test name
Test status
Simulation time 387033007 ps
CPU time 0.78 seconds
Started Apr 15 03:35:17 PM PDT 24
Finished Apr 15 03:35:18 PM PDT 24
Peak memory 193248 kb
Host smart-f8a89969-78c5-4f50-8340-c03a260a6164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559435497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3559435497
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3139698796
Short name T309
Test name
Test status
Simulation time 485068597 ps
CPU time 0.73 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 183956 kb
Host smart-5d7dc2ff-d0c5-4b5d-85d1-3a587e0916d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139698796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3139698796
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2868255655
Short name T81
Test name
Test status
Simulation time 1806710583 ps
CPU time 5.27 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:24 PM PDT 24
Peak memory 184048 kb
Host smart-1b3d7941-f52e-42bc-b07f-e334de8e914e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868255655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2868255655
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1953394113
Short name T351
Test name
Test status
Simulation time 295064602 ps
CPU time 1.34 seconds
Started Apr 15 03:35:17 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 198436 kb
Host smart-0cd9650e-47b9-4fbf-8da6-d6d017e697ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953394113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1953394113
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1171856186
Short name T105
Test name
Test status
Simulation time 4202372630 ps
CPU time 7.7 seconds
Started Apr 15 03:35:19 PM PDT 24
Finished Apr 15 03:35:27 PM PDT 24
Peak memory 197828 kb
Host smart-8871fcdb-bd13-4e03-b9e8-5cb51a50c385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171856186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1171856186
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.388076003
Short name T381
Test name
Test status
Simulation time 364879865 ps
CPU time 0.8 seconds
Started Apr 15 03:35:25 PM PDT 24
Finished Apr 15 03:35:26 PM PDT 24
Peak memory 194932 kb
Host smart-fa4fd784-cb86-4daa-8615-1083f235a6c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388076003 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.388076003
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.33512397
Short name T305
Test name
Test status
Simulation time 412225911 ps
CPU time 1.17 seconds
Started Apr 15 03:35:24 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 183932 kb
Host smart-6517ea66-cc5f-4dde-a30d-c63dbb3c34cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33512397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.33512397
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3068650371
Short name T302
Test name
Test status
Simulation time 286585704 ps
CPU time 0.67 seconds
Started Apr 15 03:35:23 PM PDT 24
Finished Apr 15 03:35:24 PM PDT 24
Peak memory 183980 kb
Host smart-aa92c243-c1fe-4462-820a-7b96661aa7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068650371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3068650371
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.868426148
Short name T375
Test name
Test status
Simulation time 1129442855 ps
CPU time 0.89 seconds
Started Apr 15 03:35:30 PM PDT 24
Finished Apr 15 03:35:31 PM PDT 24
Peak memory 193628 kb
Host smart-f78ba0d9-3611-4a7d-a7d5-16dffd004264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868426148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.868426148
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1313194664
Short name T299
Test name
Test status
Simulation time 465855883 ps
CPU time 2.01 seconds
Started Apr 15 03:35:16 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 198924 kb
Host smart-7e277262-2cb2-4c47-a410-edc2b7d59abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313194664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1313194664
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2491637108
Short name T109
Test name
Test status
Simulation time 8975782022 ps
CPU time 3.02 seconds
Started Apr 15 03:35:18 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 198248 kb
Host smart-00e3856e-f35c-4322-ae22-f018716f30ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491637108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2491637108
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.273112763
Short name T352
Test name
Test status
Simulation time 531258178 ps
CPU time 1.43 seconds
Started Apr 15 03:35:22 PM PDT 24
Finished Apr 15 03:35:24 PM PDT 24
Peak memory 196136 kb
Host smart-056906de-51cb-4add-a4c7-5e4391d29dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273112763 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.273112763
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.715843472
Short name T392
Test name
Test status
Simulation time 563694117 ps
CPU time 0.72 seconds
Started Apr 15 03:35:24 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 193276 kb
Host smart-90a43aa6-5883-4747-a054-9fd9813bfc7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715843472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.715843472
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.938565822
Short name T336
Test name
Test status
Simulation time 428477041 ps
CPU time 1.01 seconds
Started Apr 15 03:35:19 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 183976 kb
Host smart-a914c874-98c4-4ea0-b540-d839dd254e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938565822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.938565822
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2933111294
Short name T386
Test name
Test status
Simulation time 2869933293 ps
CPU time 1.91 seconds
Started Apr 15 03:35:22 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 194752 kb
Host smart-76922032-17c5-4f79-909e-27a7171982d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933111294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2933111294
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2077183334
Short name T298
Test name
Test status
Simulation time 503796545 ps
CPU time 1.79 seconds
Started Apr 15 03:35:24 PM PDT 24
Finished Apr 15 03:35:26 PM PDT 24
Peak memory 198824 kb
Host smart-f6cf155f-a020-40cb-8b9c-7a95e0074cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077183334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2077183334
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.789407593
Short name T110
Test name
Test status
Simulation time 8500058193 ps
CPU time 8.34 seconds
Started Apr 15 03:35:23 PM PDT 24
Finished Apr 15 03:35:32 PM PDT 24
Peak memory 198392 kb
Host smart-4ae050fb-6de6-4bec-a4df-cbfd9012cfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789407593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.789407593
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1168708404
Short name T236
Test name
Test status
Simulation time 537252106 ps
CPU time 0.92 seconds
Started Apr 15 12:27:44 PM PDT 24
Finished Apr 15 12:27:46 PM PDT 24
Peak memory 183132 kb
Host smart-288fb55b-f7ac-4b1e-a8d6-67e4a714d1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168708404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1168708404
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1811771338
Short name T226
Test name
Test status
Simulation time 11051660597 ps
CPU time 4.36 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:27:50 PM PDT 24
Peak memory 183216 kb
Host smart-f46faf68-1120-46ed-8347-0a618d6cc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811771338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1811771338
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.41211400
Short name T213
Test name
Test status
Simulation time 467776544 ps
CPU time 0.87 seconds
Started Apr 15 12:27:41 PM PDT 24
Finished Apr 15 12:27:43 PM PDT 24
Peak memory 183152 kb
Host smart-f2247611-670d-4560-8291-e1853f100d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41211400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.41211400
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1398196025
Short name T258
Test name
Test status
Simulation time 90056380975 ps
CPU time 14.8 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:28:00 PM PDT 24
Peak memory 194956 kb
Host smart-2253d4f2-4e22-407e-947e-a3cf6cafde19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398196025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1398196025
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2935195066
Short name T99
Test name
Test status
Simulation time 130964504252 ps
CPU time 280.8 seconds
Started Apr 15 12:27:41 PM PDT 24
Finished Apr 15 12:32:23 PM PDT 24
Peak memory 198156 kb
Host smart-4f4e0348-dff2-4779-b3a1-2b8520d0ad92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935195066 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2935195066
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2494229252
Short name T248
Test name
Test status
Simulation time 360962765 ps
CPU time 0.69 seconds
Started Apr 15 12:27:42 PM PDT 24
Finished Apr 15 12:27:44 PM PDT 24
Peak memory 183120 kb
Host smart-ec056078-78cf-4d6a-9c7f-ffd4190ebfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494229252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2494229252
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.573968246
Short name T263
Test name
Test status
Simulation time 30639701620 ps
CPU time 12.65 seconds
Started Apr 15 12:27:44 PM PDT 24
Finished Apr 15 12:27:57 PM PDT 24
Peak memory 183192 kb
Host smart-45599403-cce3-48c6-ad7f-d990056af710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573968246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.573968246
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2546013575
Short name T23
Test name
Test status
Simulation time 4834667336 ps
CPU time 8.09 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:27:55 PM PDT 24
Peak memory 214936 kb
Host smart-d5ab8879-aa65-4bb0-927f-6a2f4e3822ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546013575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2546013575
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.848960938
Short name T145
Test name
Test status
Simulation time 388004219 ps
CPU time 0.81 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:27:46 PM PDT 24
Peak memory 183120 kb
Host smart-8b373dac-0253-44e4-9456-60817c153fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848960938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.848960938
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1725796281
Short name T175
Test name
Test status
Simulation time 125921061594 ps
CPU time 109.58 seconds
Started Apr 15 12:27:42 PM PDT 24
Finished Apr 15 12:29:32 PM PDT 24
Peak memory 183220 kb
Host smart-40a6f192-c43f-4852-b08e-2d670f7e8e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725796281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1725796281
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.104205414
Short name T95
Test name
Test status
Simulation time 633005602957 ps
CPU time 1170.74 seconds
Started Apr 15 12:27:43 PM PDT 24
Finished Apr 15 12:47:15 PM PDT 24
Peak memory 205308 kb
Host smart-c4eac724-3f87-42a0-b9f2-43c27b499bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104205414 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.104205414
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2808511187
Short name T136
Test name
Test status
Simulation time 430420547 ps
CPU time 0.7 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:28:02 PM PDT 24
Peak memory 183140 kb
Host smart-8b5fd98b-122b-478a-90fb-ac37e1a3f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808511187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2808511187
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1212487257
Short name T102
Test name
Test status
Simulation time 35275825796 ps
CPU time 58.13 seconds
Started Apr 15 12:28:01 PM PDT 24
Finished Apr 15 12:29:00 PM PDT 24
Peak memory 183124 kb
Host smart-5de00767-99c9-4a01-8a16-0a56defdbd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212487257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1212487257
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2434460164
Short name T192
Test name
Test status
Simulation time 562760509 ps
CPU time 1.35 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:28:02 PM PDT 24
Peak memory 183144 kb
Host smart-09724634-d9ec-4c92-b9e2-c5c0f16e0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434460164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2434460164
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3087819762
Short name T255
Test name
Test status
Simulation time 169856473508 ps
CPU time 151.14 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:30:38 PM PDT 24
Peak memory 194648 kb
Host smart-4526a9f7-23e5-4626-bf6f-770c67f457ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087819762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3087819762
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3082640900
Short name T100
Test name
Test status
Simulation time 528184954964 ps
CPU time 287.08 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:32:54 PM PDT 24
Peak memory 198188 kb
Host smart-a4874941-53c5-4dc0-aae8-d06cd31b48d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082640900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3082640900
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.589914106
Short name T1
Test name
Test status
Simulation time 582882733 ps
CPU time 0.81 seconds
Started Apr 15 12:28:03 PM PDT 24
Finished Apr 15 12:28:05 PM PDT 24
Peak memory 183152 kb
Host smart-8fef31f5-0334-4e4b-81a5-1faed92b3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589914106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.589914106
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2990355193
Short name T217
Test name
Test status
Simulation time 38246630651 ps
CPU time 14.29 seconds
Started Apr 15 12:28:01 PM PDT 24
Finished Apr 15 12:28:16 PM PDT 24
Peak memory 183152 kb
Host smart-91b2e5e0-34e7-4429-9aac-3d3d092566f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990355193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2990355193
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3059328042
Short name T132
Test name
Test status
Simulation time 548653249 ps
CPU time 0.9 seconds
Started Apr 15 12:28:03 PM PDT 24
Finished Apr 15 12:28:05 PM PDT 24
Peak memory 183128 kb
Host smart-e8c2c602-1037-4d02-8243-68cc1440717e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059328042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3059328042
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1610266916
Short name T158
Test name
Test status
Simulation time 25862982123 ps
CPU time 104.96 seconds
Started Apr 15 12:28:01 PM PDT 24
Finished Apr 15 12:29:47 PM PDT 24
Peak memory 198096 kb
Host smart-0fe8e2e4-396d-4175-a4e7-6c39b0037c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610266916 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1610266916
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.903655607
Short name T276
Test name
Test status
Simulation time 396713068 ps
CPU time 0.87 seconds
Started Apr 15 12:28:07 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183100 kb
Host smart-8ab51970-4099-44c1-bf85-678039c79da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903655607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.903655607
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1170440610
Short name T115
Test name
Test status
Simulation time 10824662473 ps
CPU time 13.12 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183168 kb
Host smart-47135e7f-7c36-4de6-94bb-3fdf9ceb712b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170440610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1170440610
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3725202119
Short name T242
Test name
Test status
Simulation time 513742180 ps
CPU time 1.2 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183060 kb
Host smart-2d69bd2a-208d-4795-88a4-45e7b6f4f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725202119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3725202119
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2252473692
Short name T27
Test name
Test status
Simulation time 170335377614 ps
CPU time 75.49 seconds
Started Apr 15 12:28:07 PM PDT 24
Finished Apr 15 12:29:24 PM PDT 24
Peak memory 194660 kb
Host smart-910446da-0851-461d-bba6-05dabd7b6f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252473692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2252473692
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3313809712
Short name T167
Test name
Test status
Simulation time 103343464129 ps
CPU time 185.83 seconds
Started Apr 15 12:28:07 PM PDT 24
Finished Apr 15 12:31:14 PM PDT 24
Peak memory 198128 kb
Host smart-cc9cd111-b6e0-406b-9713-3e76b3e0a4b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313809712 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3313809712
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2872400905
Short name T2
Test name
Test status
Simulation time 416399729 ps
CPU time 0.76 seconds
Started Apr 15 12:28:07 PM PDT 24
Finished Apr 15 12:28:09 PM PDT 24
Peak memory 183256 kb
Host smart-2e87a410-4f46-43c7-acc1-d2138a8a5f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872400905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2872400905
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2504322568
Short name T279
Test name
Test status
Simulation time 15109032995 ps
CPU time 6.88 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 183216 kb
Host smart-b73ba2e8-566b-4034-a1a5-0c45e32d974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504322568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2504322568
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.452450377
Short name T238
Test name
Test status
Simulation time 545340659 ps
CPU time 0.59 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183144 kb
Host smart-f1daa4dd-4f76-4094-89dd-353f392838c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452450377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.452450377
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3245808519
Short name T103
Test name
Test status
Simulation time 132260212328 ps
CPU time 99.56 seconds
Started Apr 15 12:28:13 PM PDT 24
Finished Apr 15 12:29:54 PM PDT 24
Peak memory 183188 kb
Host smart-29903345-337b-4533-a677-c500f5ee4a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245808519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3245808519
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1323426516
Short name T97
Test name
Test status
Simulation time 172727351821 ps
CPU time 382.58 seconds
Started Apr 15 12:28:05 PM PDT 24
Finished Apr 15 12:34:29 PM PDT 24
Peak memory 198500 kb
Host smart-80325268-3a5a-4c86-bcf1-d223b60c837f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323426516 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1323426516
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3852387815
Short name T138
Test name
Test status
Simulation time 480253184 ps
CPU time 0.91 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183152 kb
Host smart-fe5001c3-d4fa-4657-be72-5f127d5d1efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852387815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3852387815
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.932228077
Short name T59
Test name
Test status
Simulation time 11114577779 ps
CPU time 16.78 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:32 PM PDT 24
Peak memory 183200 kb
Host smart-5b439983-29d1-4435-8dae-ec3851e60870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932228077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.932228077
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3406776684
Short name T271
Test name
Test status
Simulation time 324841373 ps
CPU time 1.03 seconds
Started Apr 15 12:28:03 PM PDT 24
Finished Apr 15 12:28:05 PM PDT 24
Peak memory 183128 kb
Host smart-75929efb-a15c-4489-8ff5-0071e01e0842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406776684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3406776684
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2308081902
Short name T171
Test name
Test status
Simulation time 599371561303 ps
CPU time 491.5 seconds
Started Apr 15 12:28:09 PM PDT 24
Finished Apr 15 12:36:21 PM PDT 24
Peak memory 183232 kb
Host smart-774c9e20-afdc-4470-932c-6cb96fad19a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308081902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2308081902
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1534167838
Short name T49
Test name
Test status
Simulation time 80432934273 ps
CPU time 653.71 seconds
Started Apr 15 12:28:05 PM PDT 24
Finished Apr 15 12:39:00 PM PDT 24
Peak memory 199584 kb
Host smart-a4262cdc-a35c-4134-b1e9-beff7e5425ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534167838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1534167838
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2399129627
Short name T155
Test name
Test status
Simulation time 600572183 ps
CPU time 0.77 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183112 kb
Host smart-52e0f7e5-275e-47dd-b897-bb809a994733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399129627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2399129627
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3162515618
Short name T266
Test name
Test status
Simulation time 17509885279 ps
CPU time 4.61 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183172 kb
Host smart-0375ffae-0c89-4307-8961-95f36415bf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162515618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3162515618
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2323336469
Short name T250
Test name
Test status
Simulation time 476746377 ps
CPU time 1.2 seconds
Started Apr 15 12:28:03 PM PDT 24
Finished Apr 15 12:28:05 PM PDT 24
Peak memory 183148 kb
Host smart-7b15b62f-a4b7-4f56-9e75-6bd94fd0fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323336469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2323336469
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3684720631
Short name T191
Test name
Test status
Simulation time 159991553881 ps
CPU time 69.22 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:29:17 PM PDT 24
Peak memory 194168 kb
Host smart-4293be57-5243-4f9e-87de-f11679a5647c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684720631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3684720631
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1743172756
Short name T47
Test name
Test status
Simulation time 90720935867 ps
CPU time 337.05 seconds
Started Apr 15 12:28:04 PM PDT 24
Finished Apr 15 12:33:42 PM PDT 24
Peak memory 198148 kb
Host smart-8f3871a8-fbe7-452b-bf50-b0abb4ed754b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743172756 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1743172756
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3855756690
Short name T270
Test name
Test status
Simulation time 535728058 ps
CPU time 0.62 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:07 PM PDT 24
Peak memory 183128 kb
Host smart-a4d2b269-1e9a-4298-9363-2790a99318e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855756690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3855756690
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.53693895
Short name T178
Test name
Test status
Simulation time 2914520840 ps
CPU time 2.89 seconds
Started Apr 15 12:28:04 PM PDT 24
Finished Apr 15 12:28:08 PM PDT 24
Peak memory 183216 kb
Host smart-e16e89c3-1e54-4f6c-aefe-50fce4430f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53693895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.53693895
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.129935446
Short name T126
Test name
Test status
Simulation time 625760734 ps
CPU time 0.57 seconds
Started Apr 15 12:28:07 PM PDT 24
Finished Apr 15 12:28:09 PM PDT 24
Peak memory 183116 kb
Host smart-0a519c83-2b52-4fa0-a59e-0ce52a01be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129935446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.129935446
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3081103307
Short name T128
Test name
Test status
Simulation time 112674731302 ps
CPU time 153.28 seconds
Started Apr 15 12:28:08 PM PDT 24
Finished Apr 15 12:30:42 PM PDT 24
Peak memory 183216 kb
Host smart-a931ce69-304d-4ab4-924f-d804d1980da5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081103307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3081103307
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.4227430853
Short name T141
Test name
Test status
Simulation time 49601729300 ps
CPU time 112.62 seconds
Started Apr 15 12:28:04 PM PDT 24
Finished Apr 15 12:29:58 PM PDT 24
Peak memory 198148 kb
Host smart-31a8cb8e-1ef7-45f3-b42d-93e4a06d21e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227430853 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.4227430853
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3543459595
Short name T86
Test name
Test status
Simulation time 390617063 ps
CPU time 1.22 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:16 PM PDT 24
Peak memory 183096 kb
Host smart-01a0b824-402e-4420-af1c-7a5058b590ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543459595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3543459595
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3796216579
Short name T197
Test name
Test status
Simulation time 18296567800 ps
CPU time 14.39 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:22 PM PDT 24
Peak memory 183212 kb
Host smart-6447bdf8-c871-4333-9320-f7766b868b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796216579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3796216579
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3517574018
Short name T159
Test name
Test status
Simulation time 523919300 ps
CPU time 0.71 seconds
Started Apr 15 12:28:04 PM PDT 24
Finished Apr 15 12:28:06 PM PDT 24
Peak memory 183132 kb
Host smart-495f39a7-593f-4723-938d-c126ca22ffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517574018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3517574018
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1412272471
Short name T241
Test name
Test status
Simulation time 423134731818 ps
CPU time 145.03 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 194752 kb
Host smart-65f9bcb5-92d7-47b1-abe6-c4776cedb119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412272471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1412272471
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.4275592477
Short name T93
Test name
Test status
Simulation time 161489253213 ps
CPU time 855.19 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:42:30 PM PDT 24
Peak memory 202192 kb
Host smart-b57d7ed6-19c8-458e-9885-794bd3304ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275592477 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.4275592477
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.387370635
Short name T184
Test name
Test status
Simulation time 356519832 ps
CPU time 1.03 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:16 PM PDT 24
Peak memory 183132 kb
Host smart-a33b4047-80fa-4689-9234-149b873f3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387370635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.387370635
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.802522890
Short name T127
Test name
Test status
Simulation time 33489376297 ps
CPU time 14.56 seconds
Started Apr 15 12:28:11 PM PDT 24
Finished Apr 15 12:28:26 PM PDT 24
Peak memory 183232 kb
Host smart-d0df0364-7af4-4015-a024-1ff6bcceb8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802522890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.802522890
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2104700125
Short name T125
Test name
Test status
Simulation time 499880149 ps
CPU time 0.61 seconds
Started Apr 15 12:28:08 PM PDT 24
Finished Apr 15 12:28:09 PM PDT 24
Peak memory 183028 kb
Host smart-4f3399bb-15b0-4ec9-8131-eae745e42fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104700125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2104700125
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.391986076
Short name T254
Test name
Test status
Simulation time 202552307227 ps
CPU time 532.07 seconds
Started Apr 15 12:28:11 PM PDT 24
Finished Apr 15 12:37:04 PM PDT 24
Peak memory 198660 kb
Host smart-a511fff8-2f64-4652-9cca-1b85b7c8dcf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391986076 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.391986076
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1507635543
Short name T185
Test name
Test status
Simulation time 414347466 ps
CPU time 0.87 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:17 PM PDT 24
Peak memory 183136 kb
Host smart-afd08cec-5556-4925-bda6-fad6c0603406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507635543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1507635543
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1483313825
Short name T181
Test name
Test status
Simulation time 40233015697 ps
CPU time 15.92 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183136 kb
Host smart-51f1b466-ce19-49c9-89be-fe2244449956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483313825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1483313825
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1923111865
Short name T6
Test name
Test status
Simulation time 532696723 ps
CPU time 1.38 seconds
Started Apr 15 12:28:09 PM PDT 24
Finished Apr 15 12:28:11 PM PDT 24
Peak memory 183092 kb
Host smart-7a7d92b6-9b09-4c37-88dd-03277adcb441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923111865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1923111865
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4152292939
Short name T211
Test name
Test status
Simulation time 86739045095 ps
CPU time 102.63 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:29:54 PM PDT 24
Peak memory 183164 kb
Host smart-7c257623-9bdf-43e2-96fa-afef2b12a9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152292939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4152292939
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1849970801
Short name T98
Test name
Test status
Simulation time 42112782013 ps
CPU time 317.38 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:33:29 PM PDT 24
Peak memory 198188 kb
Host smart-c66d5a97-2e2d-4464-8567-64f6809a75e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849970801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1849970801
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2057541215
Short name T203
Test name
Test status
Simulation time 560975631 ps
CPU time 0.65 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:27:47 PM PDT 24
Peak memory 183168 kb
Host smart-7fb9bd80-d9a9-4dba-86e9-8475fdb4f90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057541215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2057541215
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2033144325
Short name T135
Test name
Test status
Simulation time 47447207750 ps
CPU time 8.63 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:27:55 PM PDT 24
Peak memory 183192 kb
Host smart-a2425578-3a5f-412d-b973-1261da4a134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033144325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2033144325
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1852451544
Short name T22
Test name
Test status
Simulation time 3794627360 ps
CPU time 6.01 seconds
Started Apr 15 12:27:49 PM PDT 24
Finished Apr 15 12:27:56 PM PDT 24
Peak memory 214648 kb
Host smart-afa230b2-e1aa-4dbf-94ea-12d3f3cc90e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852451544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1852451544
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3298493460
Short name T229
Test name
Test status
Simulation time 546928008 ps
CPU time 0.98 seconds
Started Apr 15 12:27:48 PM PDT 24
Finished Apr 15 12:27:49 PM PDT 24
Peak memory 183148 kb
Host smart-892827f3-341e-4db2-8dee-d29ec34676b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298493460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3298493460
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.667501680
Short name T14
Test name
Test status
Simulation time 149307947265 ps
CPU time 239.38 seconds
Started Apr 15 12:27:45 PM PDT 24
Finished Apr 15 12:31:46 PM PDT 24
Peak memory 183216 kb
Host smart-6dc99b9b-8c1a-40ed-ad75-3ad1204aaf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667501680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.667501680
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2704337653
Short name T188
Test name
Test status
Simulation time 224975775686 ps
CPU time 613.45 seconds
Started Apr 15 12:27:49 PM PDT 24
Finished Apr 15 12:38:03 PM PDT 24
Peak memory 199708 kb
Host smart-dba4660b-806e-45a5-b7e2-6d4ded34380d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704337653 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2704337653
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.786118045
Short name T193
Test name
Test status
Simulation time 570663252 ps
CPU time 1.48 seconds
Started Apr 15 12:28:12 PM PDT 24
Finished Apr 15 12:28:14 PM PDT 24
Peak memory 183128 kb
Host smart-b2fab2b8-0358-4be9-8cb3-ca742db8d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786118045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.786118045
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3272390043
Short name T223
Test name
Test status
Simulation time 10573327429 ps
CPU time 18.13 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:30 PM PDT 24
Peak memory 183260 kb
Host smart-e6905d2f-af2e-447f-b7ef-d7f53c54cc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272390043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3272390043
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3106474225
Short name T261
Test name
Test status
Simulation time 535770055 ps
CPU time 1.4 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:28:18 PM PDT 24
Peak memory 183136 kb
Host smart-33ff43d7-1b16-493d-a736-0feafe658b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106474225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3106474225
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.992936868
Short name T70
Test name
Test status
Simulation time 336602314531 ps
CPU time 43.38 seconds
Started Apr 15 12:28:09 PM PDT 24
Finished Apr 15 12:28:54 PM PDT 24
Peak memory 183220 kb
Host smart-ec729e94-ca8b-443a-9f89-e3635657d3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992936868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.992936868
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2719555348
Short name T204
Test name
Test status
Simulation time 84342334337 ps
CPU time 204.66 seconds
Started Apr 15 12:28:12 PM PDT 24
Finished Apr 15 12:31:37 PM PDT 24
Peak memory 198184 kb
Host smart-98129a34-5fea-4509-92e1-3f05d48f9cc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719555348 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2719555348
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3366485396
Short name T87
Test name
Test status
Simulation time 545179340 ps
CPU time 0.75 seconds
Started Apr 15 12:28:11 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 183116 kb
Host smart-8f2d9b0f-8268-417d-8a88-619aba08d5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366485396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3366485396
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4259192866
Short name T142
Test name
Test status
Simulation time 49613799362 ps
CPU time 74.59 seconds
Started Apr 15 12:28:12 PM PDT 24
Finished Apr 15 12:29:27 PM PDT 24
Peak memory 183192 kb
Host smart-c1f3c57e-67b0-46d7-be82-90cf86eaa58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259192866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4259192866
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2184095616
Short name T32
Test name
Test status
Simulation time 384013198 ps
CPU time 0.66 seconds
Started Apr 15 12:28:08 PM PDT 24
Finished Apr 15 12:28:10 PM PDT 24
Peak memory 183236 kb
Host smart-f5fe3f66-251a-40b9-bf41-c55833e7635c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184095616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2184095616
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2543081157
Short name T164
Test name
Test status
Simulation time 3382304865 ps
CPU time 3.28 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:15 PM PDT 24
Peak memory 193564 kb
Host smart-7ead268f-474f-4628-93a6-41ba19e84f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543081157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2543081157
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1343435643
Short name T92
Test name
Test status
Simulation time 109584470690 ps
CPU time 986.23 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:44:42 PM PDT 24
Peak memory 204168 kb
Host smart-199352e5-e049-4650-8ca3-b93fdf54de7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343435643 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1343435643
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.18149499
Short name T26
Test name
Test status
Simulation time 435363613 ps
CPU time 0.62 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:11 PM PDT 24
Peak memory 183156 kb
Host smart-9350b74b-37b8-4c4a-ab17-352548a9f6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18149499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.18149499
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3956358537
Short name T29
Test name
Test status
Simulation time 30842735648 ps
CPU time 25.25 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:41 PM PDT 24
Peak memory 183204 kb
Host smart-172ebfd4-8506-4e54-959a-ff9c0477b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956358537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3956358537
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3136111104
Short name T121
Test name
Test status
Simulation time 590551528 ps
CPU time 1.5 seconds
Started Apr 15 12:28:11 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 183148 kb
Host smart-f32f4e76-cbb8-470d-a615-a75d939a7770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136111104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3136111104
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3309193403
Short name T228
Test name
Test status
Simulation time 58275858135 ps
CPU time 14.17 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:25 PM PDT 24
Peak memory 193416 kb
Host smart-13ca51eb-0420-46f1-ba91-d0c3e94e073a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309193403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3309193403
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2214300441
Short name T55
Test name
Test status
Simulation time 427157678445 ps
CPU time 871.14 seconds
Started Apr 15 12:28:11 PM PDT 24
Finished Apr 15 12:42:43 PM PDT 24
Peak memory 201832 kb
Host smart-205a0531-a2e0-4a1a-9de8-bdd8e5a4595d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214300441 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2214300441
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.87242462
Short name T257
Test name
Test status
Simulation time 401656469 ps
CPU time 1.14 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:12 PM PDT 24
Peak memory 183156 kb
Host smart-e5a18d23-7ae9-44ea-a423-6d84552daf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87242462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.87242462
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3962060157
Short name T7
Test name
Test status
Simulation time 57114762981 ps
CPU time 90.29 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:29:42 PM PDT 24
Peak memory 183280 kb
Host smart-44c94b23-4714-4abb-9a03-dbd01b07ade9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962060157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3962060157
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1920896204
Short name T232
Test name
Test status
Simulation time 448298726 ps
CPU time 1.16 seconds
Started Apr 15 12:28:10 PM PDT 24
Finished Apr 15 12:28:12 PM PDT 24
Peak memory 183136 kb
Host smart-9d65981b-047c-4e10-b57c-53291af33c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920896204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1920896204
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3192532545
Short name T176
Test name
Test status
Simulation time 433608672312 ps
CPU time 163.38 seconds
Started Apr 15 12:28:08 PM PDT 24
Finished Apr 15 12:30:53 PM PDT 24
Peak memory 183316 kb
Host smart-6c792c26-3228-4565-9f78-79a5c494c8e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192532545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3192532545
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2261198194
Short name T259
Test name
Test status
Simulation time 4139550864 ps
CPU time 28.17 seconds
Started Apr 15 12:28:12 PM PDT 24
Finished Apr 15 12:28:41 PM PDT 24
Peak memory 198152 kb
Host smart-75eb9800-f51b-48cf-8b70-2fc4c811e54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261198194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2261198194
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1915750780
Short name T18
Test name
Test status
Simulation time 576247883 ps
CPU time 1.39 seconds
Started Apr 15 12:28:18 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183128 kb
Host smart-4967f233-ff1a-46a5-ae1d-eeb50b6b7893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915750780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1915750780
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3634120103
Short name T131
Test name
Test status
Simulation time 42665752693 ps
CPU time 69.58 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:29:37 PM PDT 24
Peak memory 183048 kb
Host smart-a634a9f8-e227-492b-9777-a1740976486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634120103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3634120103
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2700259581
Short name T222
Test name
Test status
Simulation time 402032972 ps
CPU time 0.67 seconds
Started Apr 15 12:28:12 PM PDT 24
Finished Apr 15 12:28:13 PM PDT 24
Peak memory 183124 kb
Host smart-d9150e88-cfc7-44f5-8658-7b46af3b60aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700259581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2700259581
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3106618331
Short name T265
Test name
Test status
Simulation time 218777507550 ps
CPU time 343.17 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:33:59 PM PDT 24
Peak memory 183212 kb
Host smart-71edae16-89dd-407f-9734-27c11554cec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106618331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3106618331
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1724491645
Short name T57
Test name
Test status
Simulation time 78630411428 ps
CPU time 219.82 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:31:56 PM PDT 24
Peak memory 198236 kb
Host smart-f31b8673-b540-413f-895a-f657a2e0a327
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724491645 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1724491645
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1896784808
Short name T36
Test name
Test status
Simulation time 379264374 ps
CPU time 0.69 seconds
Started Apr 15 12:28:18 PM PDT 24
Finished Apr 15 12:28:19 PM PDT 24
Peak memory 183240 kb
Host smart-e59db2ec-80bf-4bce-83d9-c0de967e6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896784808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1896784808
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1887708583
Short name T221
Test name
Test status
Simulation time 55106447290 ps
CPU time 50.88 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:29:06 PM PDT 24
Peak memory 183200 kb
Host smart-6c9caa6f-0aa3-455f-9fa2-6c2a09172285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887708583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1887708583
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3229143508
Short name T256
Test name
Test status
Simulation time 547269643 ps
CPU time 1.36 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183028 kb
Host smart-6c88d2de-8180-4842-9827-85aec8c59011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229143508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3229143508
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.116210869
Short name T60
Test name
Test status
Simulation time 45661227935 ps
CPU time 31.69 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:47 PM PDT 24
Peak memory 193780 kb
Host smart-14ab2701-2f39-45ea-b9e5-74ba28a57b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116210869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.116210869
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1739858584
Short name T51
Test name
Test status
Simulation time 75242484098 ps
CPU time 280.51 seconds
Started Apr 15 12:28:18 PM PDT 24
Finished Apr 15 12:32:59 PM PDT 24
Peak memory 198160 kb
Host smart-c64c1af7-ce51-4ea4-aaf8-9271e676ff9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739858584 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1739858584
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3793707412
Short name T117
Test name
Test status
Simulation time 504198609 ps
CPU time 1.41 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:17 PM PDT 24
Peak memory 183228 kb
Host smart-4168bca7-0189-4fa9-bb67-aeecbb29d920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793707412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3793707412
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3835115414
Short name T118
Test name
Test status
Simulation time 8305035472 ps
CPU time 6.49 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:28:23 PM PDT 24
Peak memory 183132 kb
Host smart-9a232b45-0a95-4fed-8eeb-22e9271a3505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835115414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3835115414
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2852484394
Short name T16
Test name
Test status
Simulation time 389997995 ps
CPU time 0.68 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183144 kb
Host smart-18e82d2b-0662-492b-8721-9039b322d9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852484394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2852484394
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3083091221
Short name T245
Test name
Test status
Simulation time 132105784341 ps
CPU time 84.17 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:29:41 PM PDT 24
Peak memory 194460 kb
Host smart-4cd99ae5-2745-403c-aa20-b164f72ab590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083091221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3083091221
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3896029764
Short name T208
Test name
Test status
Simulation time 26776162366 ps
CPU time 207.02 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:31:43 PM PDT 24
Peak memory 198188 kb
Host smart-8880edef-a391-4806-9b95-2e365f4bd91e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896029764 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3896029764
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3554846292
Short name T4
Test name
Test status
Simulation time 460913619 ps
CPU time 1.32 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:18 PM PDT 24
Peak memory 183088 kb
Host smart-42f4e521-37a4-4923-9e63-1054338ea5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554846292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3554846292
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1108158648
Short name T129
Test name
Test status
Simulation time 9989735902 ps
CPU time 14.12 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:30 PM PDT 24
Peak memory 183208 kb
Host smart-d9bbeb54-1a78-4bc5-a1ed-d09ce70d1f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108158648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1108158648
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3155130751
Short name T214
Test name
Test status
Simulation time 512556131 ps
CPU time 1.02 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183052 kb
Host smart-e58d243a-cd28-4ccb-a0ed-f4f38d1f29ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155130751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3155130751
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2041638917
Short name T130
Test name
Test status
Simulation time 165173473752 ps
CPU time 237.29 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:32:14 PM PDT 24
Peak memory 183408 kb
Host smart-879e4918-66a1-44a8-b6a8-e5e5fe77246c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041638917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2041638917
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.646557745
Short name T91
Test name
Test status
Simulation time 134389664735 ps
CPU time 445.14 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:35:40 PM PDT 24
Peak memory 198128 kb
Host smart-c111b432-745b-4151-812c-958d9f44cb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646557745 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.646557745
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1555460257
Short name T182
Test name
Test status
Simulation time 562832991 ps
CPU time 1.39 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:28:18 PM PDT 24
Peak memory 183164 kb
Host smart-2a847c13-916b-4ffc-99b0-eb98f3a01091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555460257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1555460257
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.116968231
Short name T120
Test name
Test status
Simulation time 8319983662 ps
CPU time 3.93 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183216 kb
Host smart-69da2a2c-a1cb-4324-ad00-e1b21fedd518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116968231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.116968231
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2550453823
Short name T89
Test name
Test status
Simulation time 369383716 ps
CPU time 0.69 seconds
Started Apr 15 12:28:14 PM PDT 24
Finished Apr 15 12:28:16 PM PDT 24
Peak memory 183124 kb
Host smart-13bafa35-5fe3-4bf7-bef1-8051a3eda666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550453823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2550453823
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.222741395
Short name T174
Test name
Test status
Simulation time 245034807614 ps
CPU time 19.02 seconds
Started Apr 15 12:28:13 PM PDT 24
Finished Apr 15 12:28:33 PM PDT 24
Peak memory 194568 kb
Host smart-2edbf599-3c08-41ec-b4dc-de0f186bc95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222741395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.222741395
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4151641043
Short name T262
Test name
Test status
Simulation time 29309190514 ps
CPU time 115.85 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:30:12 PM PDT 24
Peak memory 198132 kb
Host smart-5427b85a-f232-4159-bae5-c5ed25b890d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151641043 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4151641043
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3438950872
Short name T53
Test name
Test status
Simulation time 553655173 ps
CPU time 0.64 seconds
Started Apr 15 12:28:15 PM PDT 24
Finished Apr 15 12:28:16 PM PDT 24
Peak memory 183116 kb
Host smart-237414ff-98cb-4755-8d51-aca6f5a54a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438950872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3438950872
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2434661087
Short name T154
Test name
Test status
Simulation time 16792251136 ps
CPU time 6.61 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:34 PM PDT 24
Peak memory 183068 kb
Host smart-c134ccf2-a307-4ff7-8d78-66ea5ea1ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434661087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2434661087
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.180140519
Short name T231
Test name
Test status
Simulation time 537105217 ps
CPU time 1.23 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183040 kb
Host smart-e0bf116c-f94e-4b48-ae67-4f6683877ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180140519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.180140519
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2988716183
Short name T212
Test name
Test status
Simulation time 173010401635 ps
CPU time 20.54 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:46 PM PDT 24
Peak memory 194996 kb
Host smart-b0095105-00a6-444c-b513-ddcfef40bf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988716183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2988716183
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1752449416
Short name T200
Test name
Test status
Simulation time 104094874977 ps
CPU time 429.32 seconds
Started Apr 15 12:28:16 PM PDT 24
Finished Apr 15 12:35:26 PM PDT 24
Peak memory 198184 kb
Host smart-ebb649e7-9043-40c3-a818-c64f8454f6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752449416 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1752449416
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3174650957
Short name T46
Test name
Test status
Simulation time 369769928 ps
CPU time 0.91 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:27:48 PM PDT 24
Peak memory 183144 kb
Host smart-f52ca7b1-f66f-469a-b335-63513a0b71e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174650957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3174650957
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2704994366
Short name T172
Test name
Test status
Simulation time 37406737234 ps
CPU time 16.22 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:28:03 PM PDT 24
Peak memory 183208 kb
Host smart-8d3e586c-1357-4339-a8b3-72b391a065cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704994366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2704994366
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2292576418
Short name T21
Test name
Test status
Simulation time 4270066858 ps
CPU time 3.66 seconds
Started Apr 15 12:27:59 PM PDT 24
Finished Apr 15 12:28:04 PM PDT 24
Peak memory 214612 kb
Host smart-e21b2e20-2df7-461f-9eb3-256cebe58a66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292576418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2292576418
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.3034013241
Short name T156
Test name
Test status
Simulation time 361426252 ps
CPU time 0.64 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:27:48 PM PDT 24
Peak memory 183132 kb
Host smart-bd369381-58b7-483c-a989-287c373bf911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034013241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.3034013241
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.928937327
Short name T277
Test name
Test status
Simulation time 200432356823 ps
CPU time 15.09 seconds
Started Apr 15 12:27:46 PM PDT 24
Finished Apr 15 12:28:02 PM PDT 24
Peak memory 193836 kb
Host smart-d1596ca4-bb60-4336-b2bd-3e2963d4de9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928937327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.928937327
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2517527456
Short name T264
Test name
Test status
Simulation time 454052664 ps
CPU time 0.79 seconds
Started Apr 15 12:28:22 PM PDT 24
Finished Apr 15 12:28:23 PM PDT 24
Peak memory 183236 kb
Host smart-0fbb26d7-7aa7-4548-8ea1-0a723819aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517527456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2517527456
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3122577645
Short name T187
Test name
Test status
Simulation time 31754735436 ps
CPU time 45.73 seconds
Started Apr 15 12:28:20 PM PDT 24
Finished Apr 15 12:29:06 PM PDT 24
Peak memory 183300 kb
Host smart-3c80fabe-1124-401d-ae8a-5f09e52bad32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122577645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3122577645
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.597811680
Short name T253
Test name
Test status
Simulation time 551026283 ps
CPU time 0.66 seconds
Started Apr 15 12:28:20 PM PDT 24
Finished Apr 15 12:28:21 PM PDT 24
Peak memory 183128 kb
Host smart-d14ed6d1-dbdb-45d9-b842-ecf9a22b17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597811680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.597811680
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3348733672
Short name T267
Test name
Test status
Simulation time 598894397 ps
CPU time 0.77 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183136 kb
Host smart-94f79217-0dfb-4f4a-86d5-673c850f42b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348733672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3348733672
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3809981055
Short name T10
Test name
Test status
Simulation time 961684039 ps
CPU time 1.99 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 182980 kb
Host smart-33956132-b2c7-4122-9a5d-5350b6aed03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809981055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3809981055
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3366550919
Short name T234
Test name
Test status
Simulation time 555398877 ps
CPU time 0.77 seconds
Started Apr 15 12:28:22 PM PDT 24
Finished Apr 15 12:28:23 PM PDT 24
Peak memory 183216 kb
Host smart-a0f2ba25-0f56-4141-a0ae-9d98ca32e8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366550919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3366550919
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4127679299
Short name T101
Test name
Test status
Simulation time 229328381297 ps
CPU time 184.17 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:31:29 PM PDT 24
Peak memory 183220 kb
Host smart-adf0d2db-5a27-4b74-8289-b3355e728e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127679299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4127679299
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.302393349
Short name T140
Test name
Test status
Simulation time 88785007862 ps
CPU time 166.93 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:31:08 PM PDT 24
Peak memory 198140 kb
Host smart-72f4fcab-2954-43a6-a993-b695dde0a81a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302393349 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.302393349
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2180772137
Short name T123
Test name
Test status
Simulation time 491049966 ps
CPU time 0.71 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:26 PM PDT 24
Peak memory 183128 kb
Host smart-adfb6734-7235-4d7f-97d2-16b0899dd099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180772137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2180772137
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.81308153
Short name T179
Test name
Test status
Simulation time 38929021998 ps
CPU time 28.09 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:48 PM PDT 24
Peak memory 183304 kb
Host smart-db49ee95-b0ca-450a-b24f-b6139d2ac358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81308153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.81308153
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3288354705
Short name T114
Test name
Test status
Simulation time 397155221 ps
CPU time 0.74 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:28:23 PM PDT 24
Peak memory 183152 kb
Host smart-ca68a42a-23cc-43ff-8d58-8392108766a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288354705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3288354705
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1929445561
Short name T52
Test name
Test status
Simulation time 235016464527 ps
CPU time 172.96 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:31:15 PM PDT 24
Peak memory 183240 kb
Host smart-24a846da-4cc5-4812-9c4c-d096ebc9244f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929445561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1929445561
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3947995395
Short name T122
Test name
Test status
Simulation time 605689680 ps
CPU time 0.7 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:21 PM PDT 24
Peak memory 183176 kb
Host smart-e1441c36-8050-49af-93b6-3a8b7afb92b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947995395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3947995395
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1722615816
Short name T61
Test name
Test status
Simulation time 5434112255 ps
CPU time 7.29 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:28:29 PM PDT 24
Peak memory 183304 kb
Host smart-f9ac07f6-9fca-4f3b-8e5b-274693e89914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722615816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1722615816
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.346105121
Short name T252
Test name
Test status
Simulation time 563951189 ps
CPU time 0.72 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:20 PM PDT 24
Peak memory 183148 kb
Host smart-5f6b36c5-963d-4890-8ed4-9e43a18791b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346105121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.346105121
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1209104420
Short name T50
Test name
Test status
Simulation time 38614649067 ps
CPU time 283.84 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:33:10 PM PDT 24
Peak memory 198184 kb
Host smart-b748a28a-0299-4141-9f39-16d7d14bca52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209104420 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1209104420
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.170310736
Short name T273
Test name
Test status
Simulation time 598531544 ps
CPU time 0.95 seconds
Started Apr 15 12:28:18 PM PDT 24
Finished Apr 15 12:28:19 PM PDT 24
Peak memory 183160 kb
Host smart-25828c58-3662-4f38-be80-3de4cd1206c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170310736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.170310736
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2699864173
Short name T239
Test name
Test status
Simulation time 4798769455 ps
CPU time 4.12 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:29 PM PDT 24
Peak memory 183196 kb
Host smart-532da914-5ee6-4e2c-8efd-26287a654c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699864173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2699864173
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4141724078
Short name T152
Test name
Test status
Simulation time 415946429 ps
CPU time 0.85 seconds
Started Apr 15 12:28:52 PM PDT 24
Finished Apr 15 12:28:53 PM PDT 24
Peak memory 183236 kb
Host smart-78166c32-64fc-4c03-aec3-593dcf551777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141724078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4141724078
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1827715432
Short name T3
Test name
Test status
Simulation time 181163405616 ps
CPU time 137.24 seconds
Started Apr 15 12:28:21 PM PDT 24
Finished Apr 15 12:30:39 PM PDT 24
Peak memory 183164 kb
Host smart-341bd887-ace5-4ad2-9d34-42e1553c7e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827715432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1827715432
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2499468321
Short name T157
Test name
Test status
Simulation time 109643054728 ps
CPU time 635.54 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:38:56 PM PDT 24
Peak memory 199780 kb
Host smart-e7b10f9d-3904-4015-9e56-edc88a702ea6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499468321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2499468321
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1965365319
Short name T268
Test name
Test status
Simulation time 598219057 ps
CPU time 0.9 seconds
Started Apr 15 12:28:18 PM PDT 24
Finished Apr 15 12:28:19 PM PDT 24
Peak memory 183160 kb
Host smart-f2136021-1bd2-4972-9773-c3178090f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965365319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1965365319
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3662458456
Short name T15
Test name
Test status
Simulation time 16368284034 ps
CPU time 3.26 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183188 kb
Host smart-d89d6367-351f-48ed-aa78-048541ad184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662458456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3662458456
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.845217178
Short name T240
Test name
Test status
Simulation time 361105024 ps
CPU time 1.1 seconds
Started Apr 15 12:28:20 PM PDT 24
Finished Apr 15 12:28:22 PM PDT 24
Peak memory 183156 kb
Host smart-a30103fd-4204-466d-89fd-587b9a183cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845217178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.845217178
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2646916125
Short name T71
Test name
Test status
Simulation time 262395816486 ps
CPU time 86.37 seconds
Started Apr 15 12:28:20 PM PDT 24
Finished Apr 15 12:29:47 PM PDT 24
Peak memory 183216 kb
Host smart-0dfac8a3-86c5-4fa5-bce6-869a2607178d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646916125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2646916125
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1051839251
Short name T207
Test name
Test status
Simulation time 443519216 ps
CPU time 0.89 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183104 kb
Host smart-af7ec955-60a2-48f6-b428-65cbf3944bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051839251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1051839251
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4143763374
Short name T246
Test name
Test status
Simulation time 19990113240 ps
CPU time 32.83 seconds
Started Apr 15 12:28:19 PM PDT 24
Finished Apr 15 12:28:53 PM PDT 24
Peak memory 183224 kb
Host smart-e722a304-46c5-425a-ae57-8911017279fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143763374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4143763374
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4253052747
Short name T209
Test name
Test status
Simulation time 488906471 ps
CPU time 0.9 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183052 kb
Host smart-dbdf78bf-d115-49a3-9b44-1a379fda87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253052747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4253052747
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3593970701
Short name T133
Test name
Test status
Simulation time 26295842521 ps
CPU time 28.57 seconds
Started Apr 15 12:28:28 PM PDT 24
Finished Apr 15 12:28:57 PM PDT 24
Peak memory 193964 kb
Host smart-cb286d04-55e4-4b80-8c11-f89f23b5fcef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593970701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3593970701
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2600581487
Short name T146
Test name
Test status
Simulation time 543835544 ps
CPU time 0.97 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:26 PM PDT 24
Peak memory 183164 kb
Host smart-53bbf587-c172-4a22-acdc-9484029b3640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600581487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2600581487
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.206730531
Short name T88
Test name
Test status
Simulation time 31318777546 ps
CPU time 14.15 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:41 PM PDT 24
Peak memory 183208 kb
Host smart-b9476d96-fb81-4a7f-98ca-99efc5c567fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206730531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.206730531
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.695346721
Short name T190
Test name
Test status
Simulation time 609545460 ps
CPU time 0.66 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:28:24 PM PDT 24
Peak memory 183152 kb
Host smart-c5b6c562-0c14-43bb-9d1a-398f63777251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695346721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.695346721
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.796853854
Short name T31
Test name
Test status
Simulation time 230046269553 ps
CPU time 185.21 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:31:31 PM PDT 24
Peak memory 183032 kb
Host smart-465720bb-3522-4a2a-b8f5-3ac700894e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796853854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.796853854
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.4214960789
Short name T163
Test name
Test status
Simulation time 456669631 ps
CPU time 0.68 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183144 kb
Host smart-024683a2-dacb-4398-b2a5-03395e77478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214960789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.4214960789
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1496885905
Short name T17
Test name
Test status
Simulation time 40195386257 ps
CPU time 54.58 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:29:21 PM PDT 24
Peak memory 183280 kb
Host smart-ce7ae572-6d71-490c-bd08-b03451b6308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496885905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1496885905
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.304947555
Short name T5
Test name
Test status
Simulation time 479831332 ps
CPU time 1.33 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183148 kb
Host smart-6051d9bb-07cc-4565-9d67-ee42c17ee462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304947555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.304947555
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3229503461
Short name T12
Test name
Test status
Simulation time 319368557550 ps
CPU time 106 seconds
Started Apr 15 12:28:28 PM PDT 24
Finished Apr 15 12:30:14 PM PDT 24
Peak memory 183268 kb
Host smart-fdd15d20-6707-465f-b1c6-8b6f27154d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229503461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3229503461
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.709560439
Short name T173
Test name
Test status
Simulation time 142296593586 ps
CPU time 133.76 seconds
Started Apr 15 12:28:22 PM PDT 24
Finished Apr 15 12:30:37 PM PDT 24
Peak memory 206340 kb
Host smart-1a6cb6f2-f0b8-416a-a264-fa777d529c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709560439 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.709560439
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1994159080
Short name T90
Test name
Test status
Simulation time 488239240 ps
CPU time 0.74 seconds
Started Apr 15 12:28:29 PM PDT 24
Finished Apr 15 12:28:30 PM PDT 24
Peak memory 183148 kb
Host smart-de4e0e3e-97bb-4e32-bee4-644ba28ddede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994159080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1994159080
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2597332669
Short name T62
Test name
Test status
Simulation time 9513783622 ps
CPU time 4.43 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183212 kb
Host smart-bdf3cfa1-60bb-41dc-9570-b762486dd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597332669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2597332669
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2441656065
Short name T269
Test name
Test status
Simulation time 554568019 ps
CPU time 0.77 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183180 kb
Host smart-66836dc3-0a1f-404f-b57f-0c7f3658ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441656065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2441656065
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1193152367
Short name T170
Test name
Test status
Simulation time 101969559789 ps
CPU time 86.88 seconds
Started Apr 15 12:28:28 PM PDT 24
Finished Apr 15 12:29:55 PM PDT 24
Peak memory 194820 kb
Host smart-8e91865f-aef4-4aab-ad4d-71d62d1984d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193152367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1193152367
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.58597648
Short name T64
Test name
Test status
Simulation time 108016643534 ps
CPU time 325.28 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:33:50 PM PDT 24
Peak memory 198180 kb
Host smart-5ac66cd9-31b8-4db0-a2ef-7b3cb8be3bfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58597648 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.58597648
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2608023486
Short name T224
Test name
Test status
Simulation time 469871034 ps
CPU time 0.68 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:28:01 PM PDT 24
Peak memory 183168 kb
Host smart-2004a80a-df71-4980-80b9-988d9799406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608023486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2608023486
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.632014156
Short name T195
Test name
Test status
Simulation time 4477854005 ps
CPU time 4.48 seconds
Started Apr 15 12:27:55 PM PDT 24
Finished Apr 15 12:28:00 PM PDT 24
Peak memory 183168 kb
Host smart-3e6b2f3b-2041-4b96-a8bc-ec2712e690fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632014156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.632014156
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2059695174
Short name T25
Test name
Test status
Simulation time 8992067335 ps
CPU time 4.14 seconds
Started Apr 15 12:27:48 PM PDT 24
Finished Apr 15 12:27:53 PM PDT 24
Peak memory 215116 kb
Host smart-dc40dec5-a82c-44b4-95cb-8cfddf548a1b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059695174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2059695174
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.328673347
Short name T85
Test name
Test status
Simulation time 401372763 ps
CPU time 1.08 seconds
Started Apr 15 12:27:50 PM PDT 24
Finished Apr 15 12:27:51 PM PDT 24
Peak memory 183148 kb
Host smart-ec404db4-e4bf-4750-bef9-fc831989472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328673347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.328673347
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.898600677
Short name T40
Test name
Test status
Simulation time 184960508387 ps
CPU time 70.78 seconds
Started Apr 15 12:27:52 PM PDT 24
Finished Apr 15 12:29:03 PM PDT 24
Peak memory 183272 kb
Host smart-7ba587da-d611-4303-b213-17e0563d94e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898600677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.898600677
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1170821781
Short name T205
Test name
Test status
Simulation time 62205527723 ps
CPU time 319.93 seconds
Started Apr 15 12:27:52 PM PDT 24
Finished Apr 15 12:33:12 PM PDT 24
Peak memory 198140 kb
Host smart-2b8c5e16-6af6-4a6e-81ba-b34c6209ae10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170821781 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1170821781
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2109460924
Short name T202
Test name
Test status
Simulation time 491013957 ps
CPU time 0.72 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:28:26 PM PDT 24
Peak memory 183140 kb
Host smart-792a937b-4488-499f-89f6-87e51c6f1129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109460924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2109460924
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.167416956
Short name T63
Test name
Test status
Simulation time 30976568358 ps
CPU time 45.11 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:29:09 PM PDT 24
Peak memory 183212 kb
Host smart-083e4dee-34eb-4883-99c4-7d1107451a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167416956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.167416956
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1445193981
Short name T147
Test name
Test status
Simulation time 419110768 ps
CPU time 1.13 seconds
Started Apr 15 12:28:23 PM PDT 24
Finished Apr 15 12:28:25 PM PDT 24
Peak memory 183220 kb
Host smart-ec96f885-dfcb-4d32-ba35-3525a6d9caf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445193981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1445193981
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1968202172
Short name T218
Test name
Test status
Simulation time 208389673488 ps
CPU time 336.64 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:34:03 PM PDT 24
Peak memory 183304 kb
Host smart-97817a99-2148-4be3-9ae0-6816e2507e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968202172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1968202172
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3656301186
Short name T278
Test name
Test status
Simulation time 290499990897 ps
CPU time 549.95 seconds
Started Apr 15 12:28:27 PM PDT 24
Finished Apr 15 12:37:37 PM PDT 24
Peak memory 198636 kb
Host smart-f6ab1006-1d93-400d-bba3-9f1600f3674f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656301186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3656301186
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1014650337
Short name T237
Test name
Test status
Simulation time 426951087 ps
CPU time 0.76 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183136 kb
Host smart-120ccd65-a8ed-4c09-83f8-6f4631c59ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014650337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1014650337
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.121972352
Short name T9
Test name
Test status
Simulation time 56807352919 ps
CPU time 48.4 seconds
Started Apr 15 12:28:27 PM PDT 24
Finished Apr 15 12:29:16 PM PDT 24
Peak memory 183160 kb
Host smart-de72868d-4681-4774-8687-766fb2b275bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121972352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.121972352
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1772994701
Short name T33
Test name
Test status
Simulation time 500396353 ps
CPU time 0.61 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183072 kb
Host smart-808117dd-7b32-42a7-b07e-fe19ca802b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772994701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1772994701
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1972868363
Short name T189
Test name
Test status
Simulation time 74553924166 ps
CPU time 115.48 seconds
Started Apr 15 12:28:24 PM PDT 24
Finished Apr 15 12:30:21 PM PDT 24
Peak memory 193304 kb
Host smart-fef31ef3-a439-46db-8433-e604a410baad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972868363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1972868363
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3933408750
Short name T41
Test name
Test status
Simulation time 247659386468 ps
CPU time 602.88 seconds
Started Apr 15 12:28:29 PM PDT 24
Finished Apr 15 12:38:32 PM PDT 24
Peak memory 207560 kb
Host smart-8f4cbb98-27ab-4a95-9d31-deac5327eeef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933408750 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3933408750
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3135152668
Short name T244
Test name
Test status
Simulation time 430104535 ps
CPU time 0.85 seconds
Started Apr 15 12:28:27 PM PDT 24
Finished Apr 15 12:28:29 PM PDT 24
Peak memory 183112 kb
Host smart-9bde2f61-0f14-4395-b915-6d13763384c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135152668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3135152668
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4217930835
Short name T260
Test name
Test status
Simulation time 33410568320 ps
CPU time 27.62 seconds
Started Apr 15 12:28:26 PM PDT 24
Finished Apr 15 12:28:54 PM PDT 24
Peak memory 183212 kb
Host smart-9d6bc79f-b774-4262-8a9c-c1aff95e427c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217930835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4217930835
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3955795019
Short name T124
Test name
Test status
Simulation time 565399352 ps
CPU time 1.32 seconds
Started Apr 15 12:28:25 PM PDT 24
Finished Apr 15 12:28:27 PM PDT 24
Peak memory 183180 kb
Host smart-c19b8fb3-a177-4285-8c9d-9bd782c84b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955795019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3955795019
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2168567747
Short name T34
Test name
Test status
Simulation time 65924847481 ps
CPU time 106.7 seconds
Started Apr 15 12:28:32 PM PDT 24
Finished Apr 15 12:30:19 PM PDT 24
Peak memory 183216 kb
Host smart-9582d2ff-2984-4d29-b9c9-e477cc2bb66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168567747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2168567747
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4116399927
Short name T151
Test name
Test status
Simulation time 608827277 ps
CPU time 0.7 seconds
Started Apr 15 12:28:30 PM PDT 24
Finished Apr 15 12:28:31 PM PDT 24
Peak memory 183084 kb
Host smart-149192ef-dc20-4932-8e01-9ae10e1d38f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116399927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4116399927
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.67019834
Short name T104
Test name
Test status
Simulation time 52039076933 ps
CPU time 73.48 seconds
Started Apr 15 12:28:34 PM PDT 24
Finished Apr 15 12:29:48 PM PDT 24
Peak memory 183320 kb
Host smart-9306b632-589f-40e4-9fd9-b7d742e7350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67019834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.67019834
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2017637096
Short name T227
Test name
Test status
Simulation time 482491985 ps
CPU time 1.28 seconds
Started Apr 15 12:28:32 PM PDT 24
Finished Apr 15 12:28:33 PM PDT 24
Peak memory 183160 kb
Host smart-59c9a7fc-5b3d-4b8a-95f8-906214ccedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017637096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2017637096
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3742724571
Short name T56
Test name
Test status
Simulation time 183455217991 ps
CPU time 348.24 seconds
Started Apr 15 12:28:33 PM PDT 24
Finished Apr 15 12:34:22 PM PDT 24
Peak memory 198244 kb
Host smart-b65a4e41-f519-4dfc-ba11-238dd55e3148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742724571 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3742724571
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.94565508
Short name T249
Test name
Test status
Simulation time 559665557 ps
CPU time 1 seconds
Started Apr 15 12:28:30 PM PDT 24
Finished Apr 15 12:28:31 PM PDT 24
Peak memory 183164 kb
Host smart-74c07116-39a3-4430-954d-eeda8b5bfceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94565508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.94565508
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1352407380
Short name T220
Test name
Test status
Simulation time 16217070122 ps
CPU time 5.93 seconds
Started Apr 15 12:28:31 PM PDT 24
Finished Apr 15 12:28:37 PM PDT 24
Peak memory 183212 kb
Host smart-c33d877a-a8ca-4e46-989c-c0de5cad3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352407380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1352407380
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.224396605
Short name T235
Test name
Test status
Simulation time 574780751 ps
CPU time 1 seconds
Started Apr 15 12:28:50 PM PDT 24
Finished Apr 15 12:28:52 PM PDT 24
Peak memory 183048 kb
Host smart-c6145be9-3d0d-4b1a-9176-ceea3f9f0f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224396605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.224396605
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.297037422
Short name T180
Test name
Test status
Simulation time 183877893419 ps
CPU time 61.16 seconds
Started Apr 15 12:28:29 PM PDT 24
Finished Apr 15 12:29:31 PM PDT 24
Peak memory 183224 kb
Host smart-6eee77d2-5bba-426f-b0fe-85ab9fcafffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297037422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.297037422
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1702027712
Short name T199
Test name
Test status
Simulation time 22755908810 ps
CPU time 84.36 seconds
Started Apr 15 12:28:29 PM PDT 24
Finished Apr 15 12:29:54 PM PDT 24
Peak memory 198208 kb
Host smart-4ebb2a8a-3518-40d5-8c6e-c1e6de413358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702027712 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1702027712
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3027597969
Short name T198
Test name
Test status
Simulation time 443947715 ps
CPU time 0.74 seconds
Started Apr 15 12:28:50 PM PDT 24
Finished Apr 15 12:28:52 PM PDT 24
Peak memory 183052 kb
Host smart-ceb0b042-566c-433a-aead-6a04fa28bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027597969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3027597969
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3372572575
Short name T58
Test name
Test status
Simulation time 22453819093 ps
CPU time 18.27 seconds
Started Apr 15 12:28:45 PM PDT 24
Finished Apr 15 12:29:04 PM PDT 24
Peak memory 183116 kb
Host smart-c22742c2-f132-4f60-8f51-35e7dc9bf0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372572575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3372572575
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3027309474
Short name T210
Test name
Test status
Simulation time 570449548 ps
CPU time 0.82 seconds
Started Apr 15 12:28:28 PM PDT 24
Finished Apr 15 12:28:30 PM PDT 24
Peak memory 183060 kb
Host smart-2d853ec2-3dde-4abf-b443-61414c595bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027309474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3027309474
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.423422421
Short name T150
Test name
Test status
Simulation time 109014453286 ps
CPU time 78.5 seconds
Started Apr 15 12:28:30 PM PDT 24
Finished Apr 15 12:29:49 PM PDT 24
Peak memory 193608 kb
Host smart-dfd911d3-3f1d-43b7-9f1f-10ca599e4c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423422421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.423422421
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4255814805
Short name T165
Test name
Test status
Simulation time 65559642701 ps
CPU time 186.69 seconds
Started Apr 15 12:28:30 PM PDT 24
Finished Apr 15 12:31:37 PM PDT 24
Peak memory 198280 kb
Host smart-4fede293-f49a-4c1f-a13a-d074f6a9acaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255814805 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4255814805
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.4261134515
Short name T162
Test name
Test status
Simulation time 580029604 ps
CPU time 1.41 seconds
Started Apr 15 12:28:29 PM PDT 24
Finished Apr 15 12:28:31 PM PDT 24
Peak memory 183148 kb
Host smart-74bff944-b309-4858-aa04-adcede446437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261134515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.4261134515
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3517429420
Short name T153
Test name
Test status
Simulation time 39478536734 ps
CPU time 10.87 seconds
Started Apr 15 12:28:40 PM PDT 24
Finished Apr 15 12:28:52 PM PDT 24
Peak memory 183116 kb
Host smart-66a573b4-d3db-4d8c-a64c-6cd16a0b4263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517429420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3517429420
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.684871549
Short name T149
Test name
Test status
Simulation time 504997782 ps
CPU time 0.79 seconds
Started Apr 15 12:28:32 PM PDT 24
Finished Apr 15 12:28:34 PM PDT 24
Peak memory 183096 kb
Host smart-3bec39da-dce9-4d96-a5ef-590813176c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684871549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.684871549
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.904705316
Short name T148
Test name
Test status
Simulation time 125915675500 ps
CPU time 82.32 seconds
Started Apr 15 12:28:35 PM PDT 24
Finished Apr 15 12:29:58 PM PDT 24
Peak memory 192860 kb
Host smart-98da0d3a-8220-4d48-9e7c-f3ccd0c57940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904705316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.904705316
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2379611393
Short name T143
Test name
Test status
Simulation time 526899082 ps
CPU time 0.73 seconds
Started Apr 15 12:28:37 PM PDT 24
Finished Apr 15 12:28:38 PM PDT 24
Peak memory 183148 kb
Host smart-ba8aeec7-9075-4ec9-9a23-89826c6db348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379611393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2379611393
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1406268893
Short name T230
Test name
Test status
Simulation time 10016744680 ps
CPU time 4.56 seconds
Started Apr 15 12:30:03 PM PDT 24
Finished Apr 15 12:30:08 PM PDT 24
Peak memory 183160 kb
Host smart-ed60f418-e88b-4d38-b07e-2fa3744aa224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406268893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1406268893
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2217052673
Short name T166
Test name
Test status
Simulation time 356640471 ps
CPU time 1.12 seconds
Started Apr 15 12:28:33 PM PDT 24
Finished Apr 15 12:28:35 PM PDT 24
Peak memory 183100 kb
Host smart-d30df4ce-19ab-463f-be5f-75078f188efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217052673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2217052673
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.385389842
Short name T215
Test name
Test status
Simulation time 9808006002 ps
CPU time 15.49 seconds
Started Apr 15 12:28:35 PM PDT 24
Finished Apr 15 12:28:51 PM PDT 24
Peak memory 194848 kb
Host smart-9f15c0ce-9336-49cf-89d4-fff683381fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385389842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.385389842
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1721284949
Short name T54
Test name
Test status
Simulation time 59901223544 ps
CPU time 179.71 seconds
Started Apr 15 12:28:36 PM PDT 24
Finished Apr 15 12:31:36 PM PDT 24
Peak memory 198156 kb
Host smart-5bdc4474-26d2-4b9d-935a-1ba5142255fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721284949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1721284949
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2860558594
Short name T144
Test name
Test status
Simulation time 561098155 ps
CPU time 0.82 seconds
Started Apr 15 12:28:35 PM PDT 24
Finished Apr 15 12:28:36 PM PDT 24
Peak memory 183256 kb
Host smart-8a64acd3-fe56-42df-bc9c-6af63aa3d69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860558594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2860558594
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1725227322
Short name T272
Test name
Test status
Simulation time 33666483530 ps
CPU time 59.02 seconds
Started Apr 15 12:28:38 PM PDT 24
Finished Apr 15 12:29:37 PM PDT 24
Peak memory 183164 kb
Host smart-5d06f868-9a51-487c-b976-94219dc307c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725227322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1725227322
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1819245195
Short name T30
Test name
Test status
Simulation time 434494250 ps
CPU time 0.74 seconds
Started Apr 15 12:28:34 PM PDT 24
Finished Apr 15 12:28:35 PM PDT 24
Peak memory 183220 kb
Host smart-347d3842-bf33-467d-981b-3401be6745bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819245195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1819245195
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3925148601
Short name T183
Test name
Test status
Simulation time 98009925693 ps
CPU time 154.46 seconds
Started Apr 15 12:28:36 PM PDT 24
Finished Apr 15 12:31:11 PM PDT 24
Peak memory 183152 kb
Host smart-2eb7b7cc-cb1e-40c5-97c1-1b0293d2010c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925148601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3925148601
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1200747840
Short name T137
Test name
Test status
Simulation time 77543149771 ps
CPU time 746.11 seconds
Started Apr 15 12:28:39 PM PDT 24
Finished Apr 15 12:41:06 PM PDT 24
Peak memory 199952 kb
Host smart-d656dbb9-d1fe-4ce8-8fd5-acc2b00a12b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200747840 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1200747840
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1579734238
Short name T119
Test name
Test status
Simulation time 584486597 ps
CPU time 1.36 seconds
Started Apr 15 12:30:04 PM PDT 24
Finished Apr 15 12:30:06 PM PDT 24
Peak memory 183092 kb
Host smart-39c395dc-95b1-469f-ab90-ce709ef3d176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579734238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1579734238
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.63265312
Short name T225
Test name
Test status
Simulation time 38396511486 ps
CPU time 14.07 seconds
Started Apr 15 12:28:34 PM PDT 24
Finished Apr 15 12:28:49 PM PDT 24
Peak memory 183192 kb
Host smart-a75f01ac-f1d7-43c9-b4b7-9cce2ff09eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63265312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.63265312
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1212619276
Short name T251
Test name
Test status
Simulation time 582022022 ps
CPU time 0.95 seconds
Started Apr 15 12:30:02 PM PDT 24
Finished Apr 15 12:30:04 PM PDT 24
Peak memory 183096 kb
Host smart-a22d66bc-034b-46fe-b7ef-3ba40457c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212619276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1212619276
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3062893687
Short name T233
Test name
Test status
Simulation time 41975785903 ps
CPU time 432.88 seconds
Started Apr 15 12:28:37 PM PDT 24
Finished Apr 15 12:35:50 PM PDT 24
Peak memory 198248 kb
Host smart-796746e2-def6-4d9d-954e-a634951f9eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062893687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3062893687
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.874407539
Short name T274
Test name
Test status
Simulation time 482491253 ps
CPU time 0.93 seconds
Started Apr 15 12:27:49 PM PDT 24
Finished Apr 15 12:27:51 PM PDT 24
Peak memory 183088 kb
Host smart-d179d81d-2426-4725-8137-240a2e1f5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874407539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.874407539
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2030864599
Short name T219
Test name
Test status
Simulation time 30590279246 ps
CPU time 45.32 seconds
Started Apr 15 12:27:53 PM PDT 24
Finished Apr 15 12:28:38 PM PDT 24
Peak memory 183216 kb
Host smart-a0e67a9d-a2ad-46c4-8bc1-3eaf7bf26550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030864599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2030864599
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.409868184
Short name T201
Test name
Test status
Simulation time 589912037 ps
CPU time 1.39 seconds
Started Apr 15 12:27:54 PM PDT 24
Finished Apr 15 12:27:55 PM PDT 24
Peak memory 183116 kb
Host smart-98f0d415-3f24-4fae-bce4-3b5157f80e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409868184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.409868184
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2565145307
Short name T169
Test name
Test status
Simulation time 131687346992 ps
CPU time 106.43 seconds
Started Apr 15 12:27:49 PM PDT 24
Finished Apr 15 12:29:36 PM PDT 24
Peak memory 183216 kb
Host smart-b21430f8-a9f4-46b7-b29c-0c5d3f7f01b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565145307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2565145307
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1291514286
Short name T96
Test name
Test status
Simulation time 115419388366 ps
CPU time 661.86 seconds
Started Apr 15 12:27:50 PM PDT 24
Finished Apr 15 12:38:53 PM PDT 24
Peak memory 198532 kb
Host smart-b6bac837-e19a-4d02-9bfd-e9ed0967ca39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291514286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1291514286
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3287525559
Short name T168
Test name
Test status
Simulation time 590314983 ps
CPU time 0.95 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:28:02 PM PDT 24
Peak memory 183184 kb
Host smart-da42f00f-7822-4ae3-a55e-bbe842f1f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287525559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3287525559
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1132684811
Short name T247
Test name
Test status
Simulation time 32942722956 ps
CPU time 12.73 seconds
Started Apr 15 12:27:59 PM PDT 24
Finished Apr 15 12:28:12 PM PDT 24
Peak memory 183188 kb
Host smart-a17261a1-c6ed-42d4-973f-b01a4d05cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132684811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1132684811
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2815085532
Short name T206
Test name
Test status
Simulation time 534739910 ps
CPU time 1.36 seconds
Started Apr 15 12:28:02 PM PDT 24
Finished Apr 15 12:28:04 PM PDT 24
Peak memory 183148 kb
Host smart-77a0e4c1-2b62-46d5-a95c-c6375d28b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815085532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2815085532
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.725143501
Short name T196
Test name
Test status
Simulation time 165460537947 ps
CPU time 257.4 seconds
Started Apr 15 12:27:56 PM PDT 24
Finished Apr 15 12:32:14 PM PDT 24
Peak memory 193912 kb
Host smart-70d5d0cb-055e-4b2b-a95a-6b357be7a6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725143501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.725143501
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2483734989
Short name T48
Test name
Test status
Simulation time 53980657289 ps
CPU time 189.51 seconds
Started Apr 15 12:27:58 PM PDT 24
Finished Apr 15 12:31:09 PM PDT 24
Peak memory 198196 kb
Host smart-47a5c245-fd19-4471-989d-351d8bd757d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483734989 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2483734989
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.400105520
Short name T160
Test name
Test status
Simulation time 353147719 ps
CPU time 0.76 seconds
Started Apr 15 12:27:56 PM PDT 24
Finished Apr 15 12:27:58 PM PDT 24
Peak memory 183256 kb
Host smart-23265876-b174-49fa-a1cd-2414834984c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400105520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.400105520
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4217575502
Short name T116
Test name
Test status
Simulation time 56498448985 ps
CPU time 78.21 seconds
Started Apr 15 12:28:01 PM PDT 24
Finished Apr 15 12:29:21 PM PDT 24
Peak memory 183192 kb
Host smart-4f0855ca-b67b-4aed-8e55-1f42f2fed717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217575502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4217575502
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.658351254
Short name T134
Test name
Test status
Simulation time 461093197 ps
CPU time 0.74 seconds
Started Apr 15 12:28:02 PM PDT 24
Finished Apr 15 12:28:03 PM PDT 24
Peak memory 183152 kb
Host smart-a14f201c-046a-429b-8aea-6ae0bd5a54dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658351254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.658351254
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3396298728
Short name T275
Test name
Test status
Simulation time 112490233228 ps
CPU time 166.72 seconds
Started Apr 15 12:27:56 PM PDT 24
Finished Apr 15 12:30:43 PM PDT 24
Peak memory 191452 kb
Host smart-6874535b-33fa-4e28-954a-fc8b4eeb48b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396298728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3396298728
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1432120988
Short name T177
Test name
Test status
Simulation time 246308568345 ps
CPU time 409.29 seconds
Started Apr 15 12:27:55 PM PDT 24
Finished Apr 15 12:34:45 PM PDT 24
Peak memory 206344 kb
Host smart-14073f1d-3d2a-4a91-a50f-6f675865be84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432120988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1432120988
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1715446627
Short name T13
Test name
Test status
Simulation time 388210925 ps
CPU time 1.23 seconds
Started Apr 15 12:28:00 PM PDT 24
Finished Apr 15 12:28:02 PM PDT 24
Peak memory 183100 kb
Host smart-9a56ff62-d5b9-4c98-9a73-f05bed81986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715446627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1715446627
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1353010659
Short name T161
Test name
Test status
Simulation time 51423508622 ps
CPU time 30.73 seconds
Started Apr 15 12:27:57 PM PDT 24
Finished Apr 15 12:28:28 PM PDT 24
Peak memory 183164 kb
Host smart-f269af1f-d56a-48f7-a866-902446fbb83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353010659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1353010659
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3459968957
Short name T194
Test name
Test status
Simulation time 575579063 ps
CPU time 1.53 seconds
Started Apr 15 12:27:58 PM PDT 24
Finished Apr 15 12:28:00 PM PDT 24
Peak memory 183148 kb
Host smart-1b281f6a-a873-4b77-a06a-a53d9a2ad1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459968957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3459968957
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2809873051
Short name T216
Test name
Test status
Simulation time 190976809279 ps
CPU time 231.82 seconds
Started Apr 15 12:27:57 PM PDT 24
Finished Apr 15 12:31:49 PM PDT 24
Peak memory 194860 kb
Host smart-4ba959a1-a557-4071-a615-1abcfae1a0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809873051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2809873051
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.456592494
Short name T94
Test name
Test status
Simulation time 113470552042 ps
CPU time 276.1 seconds
Started Apr 15 12:27:57 PM PDT 24
Finished Apr 15 12:32:34 PM PDT 24
Peak memory 198152 kb
Host smart-754c7d73-ca63-41c6-8abd-3e3ce1249844
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456592494 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.456592494
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4191627217
Short name T243
Test name
Test status
Simulation time 492020051 ps
CPU time 0.71 seconds
Started Apr 15 12:28:04 PM PDT 24
Finished Apr 15 12:28:06 PM PDT 24
Peak memory 183164 kb
Host smart-aa08e5fb-99ce-4617-97d9-e1533748e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191627217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4191627217
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.875123527
Short name T186
Test name
Test status
Simulation time 19592142767 ps
CPU time 29.45 seconds
Started Apr 15 12:28:06 PM PDT 24
Finished Apr 15 12:28:36 PM PDT 24
Peak memory 183216 kb
Host smart-90731ab4-02b7-4ab0-99a6-d2f11226b4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875123527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.875123527
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2614627079
Short name T35
Test name
Test status
Simulation time 391541651 ps
CPU time 1.03 seconds
Started Apr 15 12:27:55 PM PDT 24
Finished Apr 15 12:27:57 PM PDT 24
Peak memory 183144 kb
Host smart-c0cf6515-34eb-4607-bdc0-f278be1d3838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614627079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2614627079
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1379886701
Short name T139
Test name
Test status
Simulation time 179799499208 ps
CPU time 63.19 seconds
Started Apr 15 12:28:45 PM PDT 24
Finished Apr 15 12:29:49 PM PDT 24
Peak memory 183348 kb
Host smart-690eea2c-6c8f-4cb0-8f77-be8eba9b4f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379886701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1379886701
Directory /workspace/9.aon_timer_stress_all/latest
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