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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 420
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T32 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4196359719 Apr 16 02:10:28 PM PDT 24 Apr 16 02:10:44 PM PDT 24 8265546059 ps
T33 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3247860649 Apr 16 02:10:22 PM PDT 24 Apr 16 02:10:25 PM PDT 24 356827272 ps
T286 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.581126147 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:48 PM PDT 24 457896047 ps
T34 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2807864427 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:27 PM PDT 24 591389725 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1466535000 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:20 PM PDT 24 360440795 ps
T35 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.634992149 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:36 PM PDT 24 4559828548 ps
T287 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1608862581 Apr 16 02:10:54 PM PDT 24 Apr 16 02:10:56 PM PDT 24 489408679 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4199477719 Apr 16 02:10:13 PM PDT 24 Apr 16 02:10:15 PM PDT 24 587094005 ps
T74 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2570551775 Apr 16 02:10:12 PM PDT 24 Apr 16 02:10:14 PM PDT 24 429908165 ps
T60 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.491098048 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:24 PM PDT 24 4448716742 ps
T61 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1828039133 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:34 PM PDT 24 477940815 ps
T75 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1258038456 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 431677765 ps
T288 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1282801101 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 508159352 ps
T289 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1020147386 Apr 16 02:10:48 PM PDT 24 Apr 16 02:10:51 PM PDT 24 442536303 ps
T76 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3958126118 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:34 PM PDT 24 2011670327 ps
T290 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1006149358 Apr 16 02:10:27 PM PDT 24 Apr 16 02:10:29 PM PDT 24 484652618 ps
T291 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.387431090 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:25 PM PDT 24 494192246 ps
T36 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2968763204 Apr 16 02:10:22 PM PDT 24 Apr 16 02:10:26 PM PDT 24 4318728367 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4086951387 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:34 PM PDT 24 532493302 ps
T62 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3813605603 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:32 PM PDT 24 312051365 ps
T292 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1285117739 Apr 16 02:10:17 PM PDT 24 Apr 16 02:10:21 PM PDT 24 4778377287 ps
T293 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.78891501 Apr 16 02:10:29 PM PDT 24 Apr 16 02:10:31 PM PDT 24 283120777 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.756891830 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:23 PM PDT 24 580708187 ps
T294 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3368134098 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:34 PM PDT 24 4483618359 ps
T78 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3331448454 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:55 PM PDT 24 2110774949 ps
T295 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3496888128 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:33 PM PDT 24 405053681 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3722371116 Apr 16 02:10:23 PM PDT 24 Apr 16 02:10:24 PM PDT 24 470465560 ps
T80 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.293613445 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:28 PM PDT 24 2294051724 ps
T64 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4225411990 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:37 PM PDT 24 413747991 ps
T112 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2988665253 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:25 PM PDT 24 4044243677 ps
T296 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3519787436 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:25 PM PDT 24 714989341 ps
T109 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4214159451 Apr 16 02:10:15 PM PDT 24 Apr 16 02:10:20 PM PDT 24 8102223060 ps
T297 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1742188094 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 439708431 ps
T81 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.46181880 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:29 PM PDT 24 975119742 ps
T298 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1678377524 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 441888217 ps
T299 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.660413434 Apr 16 02:10:35 PM PDT 24 Apr 16 02:10:38 PM PDT 24 397120084 ps
T82 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2439697143 Apr 16 02:10:35 PM PDT 24 Apr 16 02:10:39 PM PDT 24 1373748197 ps
T300 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.439637814 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:29 PM PDT 24 4576458266 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4005434375 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:21 PM PDT 24 492989384 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.567112518 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 432133315 ps
T303 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2915288733 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:22 PM PDT 24 750522177 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1932732161 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:39 PM PDT 24 615609938 ps
T305 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2263398829 Apr 16 02:10:28 PM PDT 24 Apr 16 02:10:30 PM PDT 24 448057449 ps
T306 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2255166502 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:21 PM PDT 24 2447199119 ps
T307 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.497952362 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 316613996 ps
T308 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2702979452 Apr 16 02:10:15 PM PDT 24 Apr 16 02:10:19 PM PDT 24 482832312 ps
T309 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3739289447 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:22 PM PDT 24 684979281 ps
T310 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2395465461 Apr 16 02:10:54 PM PDT 24 Apr 16 02:10:56 PM PDT 24 382446465 ps
T311 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.258668514 Apr 16 02:10:29 PM PDT 24 Apr 16 02:10:30 PM PDT 24 479687961 ps
T312 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4267463219 Apr 16 02:10:46 PM PDT 24 Apr 16 02:10:49 PM PDT 24 507448274 ps
T313 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2691315911 Apr 16 02:10:52 PM PDT 24 Apr 16 02:10:54 PM PDT 24 456701607 ps
T314 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2141658436 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 405511800 ps
T65 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2606717076 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:26 PM PDT 24 323271580 ps
T315 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1175596244 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:19 PM PDT 24 403561431 ps
T113 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3647377250 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:29 PM PDT 24 4763317255 ps
T110 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4219354847 Apr 16 02:10:23 PM PDT 24 Apr 16 02:10:29 PM PDT 24 8990185255 ps
T316 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2342971766 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:38 PM PDT 24 646547157 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4136939328 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:36 PM PDT 24 5451965171 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3710970532 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:30 PM PDT 24 543835538 ps
T318 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2215206637 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:40 PM PDT 24 1890871662 ps
T319 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3798668680 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:29 PM PDT 24 7042339588 ps
T320 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1798407287 Apr 16 02:10:28 PM PDT 24 Apr 16 02:10:36 PM PDT 24 3865486483 ps
T321 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3165614547 Apr 16 02:10:17 PM PDT 24 Apr 16 02:10:18 PM PDT 24 370255548 ps
T322 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2897686267 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:28 PM PDT 24 413645540 ps
T111 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2448104777 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:35 PM PDT 24 4605388731 ps
T323 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1558253816 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:20 PM PDT 24 1831981795 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.256484912 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:26 PM PDT 24 8463720110 ps
T325 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2873139534 Apr 16 02:10:23 PM PDT 24 Apr 16 02:10:25 PM PDT 24 401507293 ps
T326 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2755098377 Apr 16 02:10:46 PM PDT 24 Apr 16 02:10:50 PM PDT 24 405787014 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3845815917 Apr 16 02:10:22 PM PDT 24 Apr 16 02:10:26 PM PDT 24 1203466665 ps
T328 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1483148855 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 1715633648 ps
T329 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4183592221 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:33 PM PDT 24 482208654 ps
T330 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4099820234 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 534744712 ps
T331 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2747385855 Apr 16 02:10:28 PM PDT 24 Apr 16 02:10:29 PM PDT 24 530240952 ps
T332 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.109565927 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:35 PM PDT 24 629043609 ps
T333 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1656142914 Apr 16 02:10:28 PM PDT 24 Apr 16 02:10:30 PM PDT 24 1412149366 ps
T334 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2381847145 Apr 16 02:10:54 PM PDT 24 Apr 16 02:10:56 PM PDT 24 398510748 ps
T335 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.275076745 Apr 16 02:10:43 PM PDT 24 Apr 16 02:10:45 PM PDT 24 483336179 ps
T336 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2490013501 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:23 PM PDT 24 884354198 ps
T337 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.434068821 Apr 16 02:10:30 PM PDT 24 Apr 16 02:10:32 PM PDT 24 387424464 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2784866964 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:20 PM PDT 24 1152908462 ps
T338 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1817233420 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:23 PM PDT 24 539788773 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3096252006 Apr 16 02:10:36 PM PDT 24 Apr 16 02:10:40 PM PDT 24 8380258009 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2623737789 Apr 16 02:10:12 PM PDT 24 Apr 16 02:10:14 PM PDT 24 362251877 ps
T341 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2457221278 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 647420896 ps
T342 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3144506921 Apr 16 02:10:37 PM PDT 24 Apr 16 02:10:38 PM PDT 24 427567134 ps
T343 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2529830753 Apr 16 02:10:23 PM PDT 24 Apr 16 02:10:25 PM PDT 24 430748111 ps
T344 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1648970430 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:48 PM PDT 24 13852022744 ps
T345 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3702762362 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:30 PM PDT 24 1186331138 ps
T346 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3106711302 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:38 PM PDT 24 708764573 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3883499009 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 1218218801 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4231894387 Apr 16 02:10:15 PM PDT 24 Apr 16 02:10:19 PM PDT 24 4152019205 ps
T349 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1979022248 Apr 16 02:10:46 PM PDT 24 Apr 16 02:10:49 PM PDT 24 355674658 ps
T350 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.405731945 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 343198442 ps
T351 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2104606808 Apr 16 02:10:31 PM PDT 24 Apr 16 02:10:33 PM PDT 24 1588058647 ps
T352 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.906228459 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 439325162 ps
T353 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3357502390 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:27 PM PDT 24 496583797 ps
T354 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2692500319 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:37 PM PDT 24 290056342 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1866346072 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:21 PM PDT 24 1088411127 ps
T73 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.243441044 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 322192429 ps
T355 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4143013218 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:25 PM PDT 24 2402516771 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1572091827 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:30 PM PDT 24 11914613421 ps
T356 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.274393104 Apr 16 02:10:22 PM PDT 24 Apr 16 02:10:25 PM PDT 24 452342643 ps
T357 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1956366106 Apr 16 02:10:47 PM PDT 24 Apr 16 02:10:49 PM PDT 24 491897397 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.103822007 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 404884135 ps
T359 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1206395916 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:21 PM PDT 24 403529180 ps
T360 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.283077128 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:27 PM PDT 24 500624153 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.980940414 Apr 16 02:10:14 PM PDT 24 Apr 16 02:10:18 PM PDT 24 365037017 ps
T362 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2556894572 Apr 16 02:10:43 PM PDT 24 Apr 16 02:10:45 PM PDT 24 425334165 ps
T363 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.738529282 Apr 16 02:10:30 PM PDT 24 Apr 16 02:10:32 PM PDT 24 321156149 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1035498709 Apr 16 02:10:22 PM PDT 24 Apr 16 02:10:25 PM PDT 24 433798560 ps
T365 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3348346294 Apr 16 02:10:30 PM PDT 24 Apr 16 02:10:32 PM PDT 24 642742215 ps
T366 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1244943120 Apr 16 02:10:38 PM PDT 24 Apr 16 02:10:41 PM PDT 24 396381950 ps
T367 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.578078214 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:36 PM PDT 24 436289453 ps
T368 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.39097253 Apr 16 02:10:45 PM PDT 24 Apr 16 02:10:47 PM PDT 24 425255404 ps
T369 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.291534393 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:38 PM PDT 24 473509840 ps
T370 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2199385688 Apr 16 02:10:44 PM PDT 24 Apr 16 02:10:49 PM PDT 24 4128766056 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4294953265 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 465750408 ps
T372 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.12805077 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:36 PM PDT 24 474273681 ps
T373 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1385070473 Apr 16 02:10:35 PM PDT 24 Apr 16 02:10:38 PM PDT 24 553510803 ps
T374 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1462401979 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:35 PM PDT 24 513818760 ps
T375 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2415362352 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 435610403 ps
T376 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2944006417 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:35 PM PDT 24 2758459629 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1361672444 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:23 PM PDT 24 349004969 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.486084783 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 337941824 ps
T379 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4124059346 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 401703211 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1829615293 Apr 16 02:10:15 PM PDT 24 Apr 16 02:10:17 PM PDT 24 533311018 ps
T381 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1734319750 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:34 PM PDT 24 356893112 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1556189051 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 1134536534 ps
T67 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.271935217 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:37 PM PDT 24 433947897 ps
T382 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2166749582 Apr 16 02:10:47 PM PDT 24 Apr 16 02:10:49 PM PDT 24 345144131 ps
T383 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2205491021 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 522243267 ps
T384 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3171572816 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:27 PM PDT 24 415319170 ps
T385 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1623995046 Apr 16 02:10:25 PM PDT 24 Apr 16 02:10:28 PM PDT 24 784523914 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2788531494 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:21 PM PDT 24 299135014 ps
T387 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2975345041 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:23 PM PDT 24 2677107527 ps
T388 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2045009267 Apr 16 02:10:26 PM PDT 24 Apr 16 02:10:28 PM PDT 24 519699264 ps
T389 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3604055296 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:30 PM PDT 24 4461713636 ps
T390 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2889675002 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 482571969 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2651609959 Apr 16 02:10:43 PM PDT 24 Apr 16 02:10:45 PM PDT 24 578091983 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.263384758 Apr 16 02:10:15 PM PDT 24 Apr 16 02:10:17 PM PDT 24 681401180 ps
T393 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.301444690 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:23 PM PDT 24 277886950 ps
T394 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3381927623 Apr 16 02:10:35 PM PDT 24 Apr 16 02:10:38 PM PDT 24 437583994 ps
T395 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3514325371 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:21 PM PDT 24 393333702 ps
T68 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2581083492 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:23 PM PDT 24 324763593 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2223074758 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:37 PM PDT 24 361677560 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1582515327 Apr 16 02:10:14 PM PDT 24 Apr 16 02:10:16 PM PDT 24 348151841 ps
T398 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2357992067 Apr 16 02:10:18 PM PDT 24 Apr 16 02:10:22 PM PDT 24 1165150072 ps
T399 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3582915267 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:36 PM PDT 24 2799618897 ps
T400 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1311276547 Apr 16 02:10:50 PM PDT 24 Apr 16 02:10:53 PM PDT 24 446814087 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2020767627 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:27 PM PDT 24 550923592 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2888936011 Apr 16 02:10:24 PM PDT 24 Apr 16 02:10:41 PM PDT 24 8297776106 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.455387719 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:23 PM PDT 24 535963011 ps
T404 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2980040175 Apr 16 02:10:19 PM PDT 24 Apr 16 02:10:22 PM PDT 24 491342849 ps
T405 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.824993549 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:27 PM PDT 24 1239588822 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2504201485 Apr 16 02:10:32 PM PDT 24 Apr 16 02:10:35 PM PDT 24 637102945 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2449017863 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 445173229 ps
T408 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.848884965 Apr 16 02:10:36 PM PDT 24 Apr 16 02:10:39 PM PDT 24 4642943308 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1085652418 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 500504825 ps
T410 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1903182808 Apr 16 02:10:27 PM PDT 24 Apr 16 02:10:32 PM PDT 24 8231718676 ps
T411 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4294493205 Apr 16 02:10:34 PM PDT 24 Apr 16 02:10:37 PM PDT 24 440263866 ps
T412 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2192975207 Apr 16 02:10:16 PM PDT 24 Apr 16 02:10:18 PM PDT 24 448920458 ps
T413 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4134711369 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:24 PM PDT 24 345979019 ps
T414 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4276732471 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 537521948 ps
T415 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4041741334 Apr 16 02:10:44 PM PDT 24 Apr 16 02:10:45 PM PDT 24 359780457 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1554351845 Apr 16 02:10:27 PM PDT 24 Apr 16 02:10:29 PM PDT 24 270287264 ps
T417 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1362124208 Apr 16 02:10:33 PM PDT 24 Apr 16 02:10:35 PM PDT 24 424526883 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2353916999 Apr 16 02:10:21 PM PDT 24 Apr 16 02:10:25 PM PDT 24 2190435462 ps
T419 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2028669043 Apr 16 02:10:30 PM PDT 24 Apr 16 02:10:32 PM PDT 24 561658517 ps
T420 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2777945644 Apr 16 02:10:20 PM PDT 24 Apr 16 02:10:22 PM PDT 24 432973300 ps

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.6506888
Short name T9
Test name
Test status
Simulation time 89840090574 ps
CPU time 160.64 seconds
Started Apr 16 02:11:04 PM PDT 24
Finished Apr 16 02:13:47 PM PDT 24
Peak memory 198332 kb
Host smart-a4d1404d-69ad-42e9-9983-689cbae8f749
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6506888 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.6506888
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.517378909
Short name T15
Test name
Test status
Simulation time 102911107099 ps
CPU time 160.68 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:13:36 PM PDT 24
Peak memory 183532 kb
Host smart-d4064aac-59d6-449f-9fa3-88ed4983f4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517378909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.517378909
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.4196359719
Short name T32
Test name
Test status
Simulation time 8265546059 ps
CPU time 15.03 seconds
Started Apr 16 02:10:28 PM PDT 24
Finished Apr 16 02:10:44 PM PDT 24
Peak memory 198276 kb
Host smart-02a50458-a36b-4d60-ba5b-737bd96d5d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196359719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.4196359719
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3470850565
Short name T94
Test name
Test status
Simulation time 742950849255 ps
CPU time 716.95 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:23:08 PM PDT 24
Peak memory 200208 kb
Host smart-4f34da20-c9b7-413b-81ae-86e619a3b4e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470850565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3470850565
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4136939328
Short name T66
Test name
Test status
Simulation time 5451965171 ps
CPU time 15.39 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 192124 kb
Host smart-e110202b-468d-454e-8b5c-831811adbbd0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136939328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4136939328
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3751526101
Short name T19
Test name
Test status
Simulation time 8787137650 ps
CPU time 7.88 seconds
Started Apr 16 02:10:42 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 215196 kb
Host smart-885c2901-b267-48e8-9967-6e8cf4d65bd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751526101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3751526101
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.428835718
Short name T3
Test name
Test status
Simulation time 161984424027 ps
CPU time 121.08 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:12:52 PM PDT 24
Peak memory 194816 kb
Host smart-55586481-5ca3-4ce9-83a9-5c11f523a751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428835718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.428835718
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2275221132
Short name T87
Test name
Test status
Simulation time 138634298857 ps
CPU time 235.89 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:15:04 PM PDT 24
Peak memory 198296 kb
Host smart-d0c0c903-002e-4be2-a356-03cf9e96eb39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275221132 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2275221132
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.499452657
Short name T38
Test name
Test status
Simulation time 17433038400 ps
CPU time 93.23 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:12:22 PM PDT 24
Peak memory 198308 kb
Host smart-1afeddf8-f958-4a87-819b-886ca763cfa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499452657 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.499452657
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2570551775
Short name T74
Test name
Test status
Simulation time 429908165 ps
CPU time 1.27 seconds
Started Apr 16 02:10:12 PM PDT 24
Finished Apr 16 02:10:14 PM PDT 24
Peak memory 184168 kb
Host smart-aec1750e-64cf-4bde-8240-61a4082033c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570551775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2570551775
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2448104777
Short name T111
Test name
Test status
Simulation time 4605388731 ps
CPU time 2.61 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 197900 kb
Host smart-8aa377ca-65d6-4944-af8f-264869c4bd69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448104777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2448104777
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.4199477719
Short name T59
Test name
Test status
Simulation time 587094005 ps
CPU time 0.93 seconds
Started Apr 16 02:10:13 PM PDT 24
Finished Apr 16 02:10:15 PM PDT 24
Peak memory 184000 kb
Host smart-1479311d-bf82-462b-841b-8742957b6e83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199477719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.4199477719
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.263384758
Short name T392
Test name
Test status
Simulation time 681401180 ps
CPU time 1.07 seconds
Started Apr 16 02:10:15 PM PDT 24
Finished Apr 16 02:10:17 PM PDT 24
Peak memory 183992 kb
Host smart-f513226f-09a7-4193-bb19-44e74a331486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263384758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.263384758
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1829615293
Short name T380
Test name
Test status
Simulation time 533311018 ps
CPU time 1.38 seconds
Started Apr 16 02:10:15 PM PDT 24
Finished Apr 16 02:10:17 PM PDT 24
Peak memory 196476 kb
Host smart-08297e09-43b1-4fbe-b788-92508080c3eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829615293 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1829615293
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3165614547
Short name T321
Test name
Test status
Simulation time 370255548 ps
CPU time 0.78 seconds
Started Apr 16 02:10:17 PM PDT 24
Finished Apr 16 02:10:18 PM PDT 24
Peak memory 183896 kb
Host smart-857883cb-c882-484e-8ea1-e4d8726ba7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165614547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3165614547
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4005434375
Short name T301
Test name
Test status
Simulation time 492989384 ps
CPU time 0.81 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 183856 kb
Host smart-a91e4aa7-38c6-478c-858d-e9271290e0a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005434375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4005434375
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2192975207
Short name T412
Test name
Test status
Simulation time 448920458 ps
CPU time 1.2 seconds
Started Apr 16 02:10:16 PM PDT 24
Finished Apr 16 02:10:18 PM PDT 24
Peak memory 183896 kb
Host smart-ac844fe6-9dda-44dd-9cfb-4f08c7edea01
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192975207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2192975207
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2975345041
Short name T387
Test name
Test status
Simulation time 2677107527 ps
CPU time 2.16 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 194380 kb
Host smart-42b167d5-345f-421d-813f-405019e0d00a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975345041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2975345041
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2702979452
Short name T308
Test name
Test status
Simulation time 482832312 ps
CPU time 2.8 seconds
Started Apr 16 02:10:15 PM PDT 24
Finished Apr 16 02:10:19 PM PDT 24
Peak memory 198880 kb
Host smart-657be5c1-05bf-4855-b760-df1e12c3248d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702979452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2702979452
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.4214159451
Short name T109
Test name
Test status
Simulation time 8102223060 ps
CPU time 4.45 seconds
Started Apr 16 02:10:15 PM PDT 24
Finished Apr 16 02:10:20 PM PDT 24
Peak memory 198216 kb
Host smart-f9d3b012-dca2-47d5-b31e-eb0933861e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214159451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.4214159451
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.756891830
Short name T63
Test name
Test status
Simulation time 580708187 ps
CPU time 1.07 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 184024 kb
Host smart-03170d03-013f-4ba0-9fec-75c55eb209f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756891830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.756891830
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.491098048
Short name T60
Test name
Test status
Simulation time 4448716742 ps
CPU time 2.37 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 192420 kb
Host smart-54245dac-4a15-4e67-98ac-0f22ca32adc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491098048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.491098048
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2784866964
Short name T69
Test name
Test status
Simulation time 1152908462 ps
CPU time 1.42 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:20 PM PDT 24
Peak memory 193436 kb
Host smart-e60b60dc-b07b-4126-9b65-e6969cdd2ae7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784866964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2784866964
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.567112518
Short name T302
Test name
Test status
Simulation time 432133315 ps
CPU time 0.9 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 195600 kb
Host smart-f8587303-d369-4111-9b03-8253d7d99fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567112518 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.567112518
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3722371116
Short name T79
Test name
Test status
Simulation time 470465560 ps
CPU time 0.72 seconds
Started Apr 16 02:10:23 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 193264 kb
Host smart-f5c3c117-006a-4826-ad91-fc5a972e81c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722371116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3722371116
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2578581999
Short name T283
Test name
Test status
Simulation time 264643230 ps
CPU time 0.97 seconds
Started Apr 16 02:10:17 PM PDT 24
Finished Apr 16 02:10:19 PM PDT 24
Peak memory 183924 kb
Host smart-386d30f0-3faf-4d7e-a95e-9c1b4365f8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578581999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2578581999
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1582515327
Short name T397
Test name
Test status
Simulation time 348151841 ps
CPU time 1.04 seconds
Started Apr 16 02:10:14 PM PDT 24
Finished Apr 16 02:10:16 PM PDT 24
Peak memory 183824 kb
Host smart-804dc569-5cf3-4d8e-85a1-485041d14a21
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582515327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1582515327
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2623737789
Short name T340
Test name
Test status
Simulation time 362251877 ps
CPU time 0.65 seconds
Started Apr 16 02:10:12 PM PDT 24
Finished Apr 16 02:10:14 PM PDT 24
Peak memory 183872 kb
Host smart-3ceb5be7-4d4c-445a-afc0-fe0cc751cd35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623737789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2623737789
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2255166502
Short name T306
Test name
Test status
Simulation time 2447199119 ps
CPU time 1.72 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 194944 kb
Host smart-6fa31127-37e2-4532-883c-28aee18f02f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255166502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2255166502
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.980940414
Short name T361
Test name
Test status
Simulation time 365037017 ps
CPU time 2.44 seconds
Started Apr 16 02:10:14 PM PDT 24
Finished Apr 16 02:10:18 PM PDT 24
Peak memory 198872 kb
Host smart-942a4d14-dc02-4046-8056-8bdc8b730aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980940414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.980940414
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.4231894387
Short name T348
Test name
Test status
Simulation time 4152019205 ps
CPU time 2.62 seconds
Started Apr 16 02:10:15 PM PDT 24
Finished Apr 16 02:10:19 PM PDT 24
Peak memory 197912 kb
Host smart-482dab22-9455-409c-86cb-91eac51bffd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231894387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.4231894387
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2807864427
Short name T34
Test name
Test status
Simulation time 591389725 ps
CPU time 1.27 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 196752 kb
Host smart-a2ccf300-8107-4feb-8fe2-a724ddbd918d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807864427 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2807864427
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3813605603
Short name T62
Test name
Test status
Simulation time 312051365 ps
CPU time 1.1 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 184244 kb
Host smart-7e1e4c38-8d89-4348-beac-df8799ff34fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813605603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3813605603
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.258668514
Short name T311
Test name
Test status
Simulation time 479687961 ps
CPU time 0.68 seconds
Started Apr 16 02:10:29 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 183936 kb
Host smart-4ebf9564-b326-4a97-8d6e-e05dbeb3dba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258668514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.258668514
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1483148855
Short name T328
Test name
Test status
Simulation time 1715633648 ps
CPU time 1.63 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 194696 kb
Host smart-fd3e45de-52d4-4042-81d1-ebbd1b1766b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483148855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1483148855
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1623995046
Short name T385
Test name
Test status
Simulation time 784523914 ps
CPU time 1.75 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:28 PM PDT 24
Peak memory 198820 kb
Host smart-f12963b3-90f9-4891-a2b2-a0dfadcade38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623995046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1623995046
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.439637814
Short name T300
Test name
Test status
Simulation time 4576458266 ps
CPU time 2.77 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 197856 kb
Host smart-f8e4d418-6723-4d24-8ca8-3753acb306d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439637814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.439637814
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3348346294
Short name T365
Test name
Test status
Simulation time 642742215 ps
CPU time 1.22 seconds
Started Apr 16 02:10:30 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 198744 kb
Host smart-ce181c67-4407-4fc2-bbcf-71ca41789e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348346294 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3348346294
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2020767627
Short name T401
Test name
Test status
Simulation time 550923592 ps
CPU time 1.61 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 193420 kb
Host smart-b22e35d8-d230-45f4-beb1-c6f3b00bac18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020767627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2020767627
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.434068821
Short name T337
Test name
Test status
Simulation time 387424464 ps
CPU time 1.16 seconds
Started Apr 16 02:10:30 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 183948 kb
Host smart-11b66116-7e27-4cb8-93b5-d4f06d406f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434068821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.434068821
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.293613445
Short name T80
Test name
Test status
Simulation time 2294051724 ps
CPU time 1.07 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:28 PM PDT 24
Peak memory 184264 kb
Host smart-952f613b-af52-4806-b84e-a9b0bfcfd53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293613445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.293613445
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2457221278
Short name T341
Test name
Test status
Simulation time 647420896 ps
CPU time 1.9 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 198880 kb
Host smart-e56affd8-1816-4215-a57e-6d714f049f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457221278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2457221278
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3368134098
Short name T294
Test name
Test status
Simulation time 4483618359 ps
CPU time 2.56 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:34 PM PDT 24
Peak memory 197420 kb
Host smart-c4e64f3d-2487-4090-bbbf-4801b8be9913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368134098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3368134098
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1006149358
Short name T290
Test name
Test status
Simulation time 484652618 ps
CPU time 1.1 seconds
Started Apr 16 02:10:27 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 198680 kb
Host smart-1253e794-d909-44af-bb12-c46363cd2b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006149358 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1006149358
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3171572816
Short name T384
Test name
Test status
Simulation time 415319170 ps
CPU time 0.64 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 193280 kb
Host smart-8f19b82c-d7de-47cf-9ccb-61c043c459ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171572816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3171572816
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1554351845
Short name T416
Test name
Test status
Simulation time 270287264 ps
CPU time 0.94 seconds
Started Apr 16 02:10:27 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 183928 kb
Host smart-972255ee-46d9-4a82-a487-f690c0a6c0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554351845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1554351845
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2104606808
Short name T351
Test name
Test status
Simulation time 1588058647 ps
CPU time 1.12 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:33 PM PDT 24
Peak memory 193368 kb
Host smart-0131d40e-21bb-4612-ad44-ecdd94facfa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104606808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2104606808
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3710970532
Short name T317
Test name
Test status
Simulation time 543835538 ps
CPU time 2.81 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 198828 kb
Host smart-447b627d-bcf7-48f0-bffe-82a03984ce00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710970532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3710970532
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1903182808
Short name T410
Test name
Test status
Simulation time 8231718676 ps
CPU time 4.4 seconds
Started Apr 16 02:10:27 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 198484 kb
Host smart-3defd47c-6be6-4f81-bd60-fe366289cf86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903182808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1903182808
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2873139534
Short name T325
Test name
Test status
Simulation time 401507293 ps
CPU time 0.97 seconds
Started Apr 16 02:10:23 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 195628 kb
Host smart-0d3671c1-b1b4-47fb-88e3-fb115ff3394e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873139534 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2873139534
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2606717076
Short name T65
Test name
Test status
Simulation time 323271580 ps
CPU time 1.01 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:26 PM PDT 24
Peak memory 193308 kb
Host smart-78ea17f4-9020-43ac-aae8-f3c4b758ced1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606717076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2606717076
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3357502390
Short name T353
Test name
Test status
Simulation time 496583797 ps
CPU time 0.97 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 183936 kb
Host smart-354c8ee1-d1b3-4ca3-8075-235e159337ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357502390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3357502390
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.46181880
Short name T81
Test name
Test status
Simulation time 975119742 ps
CPU time 2.04 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 184296 kb
Host smart-4afdb85b-0cb9-4360-b3d9-513fc056bbee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46181880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_
timer_same_csr_outstanding.46181880
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.738529282
Short name T363
Test name
Test status
Simulation time 321156149 ps
CPU time 1.52 seconds
Started Apr 16 02:10:30 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 198812 kb
Host smart-a594caf8-f3e9-484f-aa35-e3ab9a8ad289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738529282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.738529282
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1385070473
Short name T373
Test name
Test status
Simulation time 553510803 ps
CPU time 1.07 seconds
Started Apr 16 02:10:35 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 196512 kb
Host smart-c3c1a71b-7e08-41f9-bd3d-c9abec67b19d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385070473 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1385070473
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.283077128
Short name T360
Test name
Test status
Simulation time 500624153 ps
CPU time 1.38 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 183976 kb
Host smart-187ec71c-92ff-4c9c-8395-a0992b194608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283077128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.283077128
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2263398829
Short name T305
Test name
Test status
Simulation time 448057449 ps
CPU time 1.24 seconds
Started Apr 16 02:10:28 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 183856 kb
Host smart-7873cbd6-0a3e-448d-a35c-faa764dbe5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263398829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2263398829
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3331448454
Short name T78
Test name
Test status
Simulation time 2110774949 ps
CPU time 8.15 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:55 PM PDT 24
Peak memory 194784 kb
Host smart-bd443530-a432-4303-9663-ea4dda3112a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331448454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3331448454
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2028669043
Short name T419
Test name
Test status
Simulation time 561658517 ps
CPU time 1.42 seconds
Started Apr 16 02:10:30 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 198836 kb
Host smart-8efdecdf-5b3a-4980-83b3-01d29bbb17e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028669043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2028669043
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.634992149
Short name T35
Test name
Test status
Simulation time 4559828548 ps
CPU time 8.16 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 197892 kb
Host smart-6ded3f56-b00a-4772-b875-8358c136b911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634992149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.634992149
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.906228459
Short name T352
Test name
Test status
Simulation time 439325162 ps
CPU time 0.83 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 196372 kb
Host smart-23e3fc13-38d2-45d1-bfc8-cdc3146bfa9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906228459 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.906228459
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.271935217
Short name T67
Test name
Test status
Simulation time 433947897 ps
CPU time 0.89 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:37 PM PDT 24
Peak memory 193300 kb
Host smart-5c1758be-7fa0-40cc-a480-b62b7f3222d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271935217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.271935217
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.578078214
Short name T367
Test name
Test status
Simulation time 436289453 ps
CPU time 0.91 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 183936 kb
Host smart-4cdd95c0-acf8-4c24-becd-3c01770e8da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578078214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.578078214
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3582915267
Short name T399
Test name
Test status
Simulation time 2799618897 ps
CPU time 2.56 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 195016 kb
Host smart-07e72295-508c-4741-8d06-04dcc96fd86d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582915267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3582915267
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2342971766
Short name T316
Test name
Test status
Simulation time 646547157 ps
CPU time 2.21 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 198836 kb
Host smart-0ad351dc-7988-46cc-a5f7-06496b24abfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342971766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2342971766
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1798407287
Short name T320
Test name
Test status
Simulation time 3865486483 ps
CPU time 7.36 seconds
Started Apr 16 02:10:28 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 198040 kb
Host smart-1c4238fd-65d0-4651-9c2d-d2d552844231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798407287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1798407287
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4099820234
Short name T330
Test name
Test status
Simulation time 534744712 ps
CPU time 0.81 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 195392 kb
Host smart-69aa5a5d-4d33-416d-a577-cb0d269e33a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099820234 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4099820234
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4225411990
Short name T64
Test name
Test status
Simulation time 413747991 ps
CPU time 1.32 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:37 PM PDT 24
Peak memory 184220 kb
Host smart-a310b48b-df48-4d8e-8421-eeca87b71a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225411990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4225411990
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2223074758
Short name T396
Test name
Test status
Simulation time 361677560 ps
CPU time 1.01 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:37 PM PDT 24
Peak memory 183928 kb
Host smart-ead643a8-ac99-41e2-9dbc-4e9cfab6b02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223074758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2223074758
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2439697143
Short name T82
Test name
Test status
Simulation time 1373748197 ps
CPU time 2.44 seconds
Started Apr 16 02:10:35 PM PDT 24
Finished Apr 16 02:10:39 PM PDT 24
Peak memory 184004 kb
Host smart-e7f43b3a-f3de-447c-91d8-45a63616ae8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439697143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2439697143
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1932732161
Short name T304
Test name
Test status
Simulation time 615609938 ps
CPU time 2.8 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:39 PM PDT 24
Peak memory 198736 kb
Host smart-028342e8-3c32-4627-977d-c40242005246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932732161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1932732161
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2199385688
Short name T370
Test name
Test status
Simulation time 4128766056 ps
CPU time 3.96 seconds
Started Apr 16 02:10:44 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 197560 kb
Host smart-d397a9b2-6abe-476e-a543-58a43e25ef25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199385688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2199385688
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1282801101
Short name T288
Test name
Test status
Simulation time 508159352 ps
CPU time 1.22 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 196820 kb
Host smart-97162c11-cffe-4879-a6cf-5d7e85f990b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282801101 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1282801101
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.243441044
Short name T73
Test name
Test status
Simulation time 322192429 ps
CPU time 0.82 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 193268 kb
Host smart-49968912-1b01-43da-94c5-8694c63d2906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243441044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.243441044
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.660413434
Short name T299
Test name
Test status
Simulation time 397120084 ps
CPU time 1.11 seconds
Started Apr 16 02:10:35 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 183912 kb
Host smart-b1c5b7cc-ae63-42e7-b74f-a0da41865b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660413434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.660413434
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3958126118
Short name T76
Test name
Test status
Simulation time 2011670327 ps
CPU time 1.19 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:34 PM PDT 24
Peak memory 194960 kb
Host smart-2be82e00-0a7d-499d-8e5b-ad242bd321dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958126118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3958126118
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3106711302
Short name T346
Test name
Test status
Simulation time 708764573 ps
CPU time 2.04 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 198884 kb
Host smart-6a551fbe-81ee-445b-af5e-3fc09c75f391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106711302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3106711302
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3096252006
Short name T339
Test name
Test status
Simulation time 8380258009 ps
CPU time 3.1 seconds
Started Apr 16 02:10:36 PM PDT 24
Finished Apr 16 02:10:40 PM PDT 24
Peak memory 198236 kb
Host smart-0af18b89-85b4-41a4-ab2e-b482536600b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096252006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3096252006
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.109565927
Short name T332
Test name
Test status
Simulation time 629043609 ps
CPU time 1.5 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 195916 kb
Host smart-04184a25-d586-4219-a856-ec2f3af3defc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109565927 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.109565927
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1362124208
Short name T417
Test name
Test status
Simulation time 424526883 ps
CPU time 1.25 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 184124 kb
Host smart-6c82867a-4b1f-454d-965c-a95f9d94f30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362124208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1362124208
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2889675002
Short name T390
Test name
Test status
Simulation time 482571969 ps
CPU time 0.67 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 183968 kb
Host smart-42f586bb-2ad6-4f72-99de-26a34459d98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889675002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2889675002
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2944006417
Short name T376
Test name
Test status
Simulation time 2758459629 ps
CPU time 1.5 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 184240 kb
Host smart-b265050f-df87-4ff1-8637-5c451db38755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944006417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2944006417
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2504201485
Short name T406
Test name
Test status
Simulation time 637102945 ps
CPU time 2.54 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 198844 kb
Host smart-a01b7656-3466-4288-a89d-7065a2e79cd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504201485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2504201485
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.848884965
Short name T408
Test name
Test status
Simulation time 4642943308 ps
CPU time 2.39 seconds
Started Apr 16 02:10:36 PM PDT 24
Finished Apr 16 02:10:39 PM PDT 24
Peak memory 197848 kb
Host smart-a80e1be1-cf2c-426d-9c17-92c6810a2e40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848884965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.848884965
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2651609959
Short name T391
Test name
Test status
Simulation time 578091983 ps
CPU time 0.79 seconds
Started Apr 16 02:10:43 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 196836 kb
Host smart-2e249001-72dd-490f-aa8c-0014c85f0a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651609959 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2651609959
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4086951387
Short name T77
Test name
Test status
Simulation time 532493302 ps
CPU time 1.37 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:34 PM PDT 24
Peak memory 184184 kb
Host smart-e29a8034-41cc-4baf-8c4e-8288851a95e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086951387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4086951387
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2141658436
Short name T314
Test name
Test status
Simulation time 405511800 ps
CPU time 0.66 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 183968 kb
Host smart-c73cdd83-bc3d-4aed-9eaa-c7413f983cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141658436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2141658436
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2215206637
Short name T318
Test name
Test status
Simulation time 1890871662 ps
CPU time 3.35 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:40 PM PDT 24
Peak memory 192252 kb
Host smart-65d95548-61b4-42ee-b806-335bb7e7728a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215206637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2215206637
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1462401979
Short name T374
Test name
Test status
Simulation time 513818760 ps
CPU time 1.67 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 198900 kb
Host smart-30cf1938-263d-44ab-a31f-925cd9c476cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462401979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1462401979
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1466535000
Short name T58
Test name
Test status
Simulation time 360440795 ps
CPU time 0.78 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:20 PM PDT 24
Peak memory 184036 kb
Host smart-3c090d52-43b3-4ee3-87b8-5ccc5f73d637
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466535000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1466535000
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1572091827
Short name T70
Test name
Test status
Simulation time 11914613421 ps
CPU time 11.5 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 184288 kb
Host smart-1cb27262-3c27-498e-827d-c05e8542389e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572091827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1572091827
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.1866346072
Short name T72
Test name
Test status
Simulation time 1088411127 ps
CPU time 0.99 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 184032 kb
Host smart-49cc0c57-f86f-409f-9608-f855c53254e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866346072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.1866346072
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.486084783
Short name T378
Test name
Test status
Simulation time 337941824 ps
CPU time 0.89 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 195724 kb
Host smart-4f377787-7a61-46d3-aaef-4cb0c909ed9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486084783 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.486084783
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4124059346
Short name T379
Test name
Test status
Simulation time 401703211 ps
CPU time 0.76 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 184192 kb
Host smart-523b2145-1588-4205-988b-eda61392df5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124059346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4124059346
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2415362352
Short name T375
Test name
Test status
Simulation time 435610403 ps
CPU time 0.9 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 183860 kb
Host smart-72f1d9e1-8d89-4c69-b10e-49028bc745e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415362352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2415362352
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.846319209
Short name T285
Test name
Test status
Simulation time 492549188 ps
CPU time 0.64 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 183848 kb
Host smart-0fb518ab-3943-4c96-a0af-4edf6c735114
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846319209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.846319209
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1206395916
Short name T359
Test name
Test status
Simulation time 403529180 ps
CPU time 0.53 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 183864 kb
Host smart-29874402-56bd-45c3-b8ab-df6937526587
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206395916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1206395916
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3883499009
Short name T347
Test name
Test status
Simulation time 1218218801 ps
CPU time 1.22 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 193784 kb
Host smart-7b6eeb43-ab09-446f-bedc-e9123bd6426b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883499009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3883499009
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1085652418
Short name T409
Test name
Test status
Simulation time 500504825 ps
CPU time 1.59 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 198868 kb
Host smart-a88be788-ef5c-4404-8935-52e4d3f0a144
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085652418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1085652418
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1285117739
Short name T292
Test name
Test status
Simulation time 4778377287 ps
CPU time 2.4 seconds
Started Apr 16 02:10:17 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 196676 kb
Host smart-92c92219-e581-4135-b322-5a12bde82236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285117739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1285117739
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1311276547
Short name T400
Test name
Test status
Simulation time 446814087 ps
CPU time 1.24 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:10:53 PM PDT 24
Peak memory 183972 kb
Host smart-0ea1541e-f500-47db-8a4a-72f13265a42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311276547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1311276547
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.405731945
Short name T350
Test name
Test status
Simulation time 343198442 ps
CPU time 0.64 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 183896 kb
Host smart-e19b06ea-4983-468f-a95c-6bc2b1ea111c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405731945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.405731945
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4276732471
Short name T414
Test name
Test status
Simulation time 537521948 ps
CPU time 0.6 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:35 PM PDT 24
Peak memory 183892 kb
Host smart-fbabcc1c-e3e7-4d91-ba9a-bc123ede1473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276732471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4276732471
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.12805077
Short name T372
Test name
Test status
Simulation time 474273681 ps
CPU time 1.36 seconds
Started Apr 16 02:10:33 PM PDT 24
Finished Apr 16 02:10:36 PM PDT 24
Peak memory 183940 kb
Host smart-37dc78b2-9f1e-439e-9572-de57298d22ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.12805077
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3496888128
Short name T295
Test name
Test status
Simulation time 405053681 ps
CPU time 0.73 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:33 PM PDT 24
Peak memory 183920 kb
Host smart-1721c1c2-8121-418d-97e2-13fc49f7cacb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496888128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3496888128
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1734319750
Short name T381
Test name
Test status
Simulation time 356893112 ps
CPU time 0.66 seconds
Started Apr 16 02:10:32 PM PDT 24
Finished Apr 16 02:10:34 PM PDT 24
Peak memory 183956 kb
Host smart-072f271f-90ff-49c4-b651-531b09a7b3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734319750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1734319750
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2166749582
Short name T382
Test name
Test status
Simulation time 345144131 ps
CPU time 0.6 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183876 kb
Host smart-ad9b0c33-0649-48b3-a48f-0f4eb5181479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166749582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2166749582
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.291534393
Short name T369
Test name
Test status
Simulation time 473509840 ps
CPU time 1.36 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 183924 kb
Host smart-9721c56c-5d73-46ef-b7cd-86c6267fca7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291534393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.291534393
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4041741334
Short name T415
Test name
Test status
Simulation time 359780457 ps
CPU time 0.63 seconds
Started Apr 16 02:10:44 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 183880 kb
Host smart-ebbaa312-767d-4959-9f12-167a55d8d1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041741334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4041741334
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1020147386
Short name T289
Test name
Test status
Simulation time 442536303 ps
CPU time 0.97 seconds
Started Apr 16 02:10:48 PM PDT 24
Finished Apr 16 02:10:51 PM PDT 24
Peak memory 183884 kb
Host smart-30916a33-2678-4581-9a8f-3cea4bfe6a23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020147386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1020147386
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4153303909
Short name T31
Test name
Test status
Simulation time 403153923 ps
CPU time 1.13 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 193408 kb
Host smart-181a54dc-e34a-4ba2-8e52-9b3aae9589e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153303909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4153303909
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1648970430
Short name T344
Test name
Test status
Simulation time 13852022744 ps
CPU time 21.94 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:48 PM PDT 24
Peak memory 184248 kb
Host smart-0f7cb14d-c44b-4a25-bb1b-f180d9038b2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648970430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1648970430
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1556189051
Short name T71
Test name
Test status
Simulation time 1134536534 ps
CPU time 1.04 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 184016 kb
Host smart-4d5ee6db-6712-42ec-a856-3227e19325e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556189051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1556189051
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.274393104
Short name T356
Test name
Test status
Simulation time 452342643 ps
CPU time 1.37 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 195076 kb
Host smart-4e7cc5fb-9d59-4a7e-b6f3-b40e0b4a5afa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274393104 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.274393104
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4294953265
Short name T371
Test name
Test status
Simulation time 465750408 ps
CPU time 1.27 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 193236 kb
Host smart-a4603a4d-25bc-4909-a6e7-1131f314655c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294953265 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4294953265
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.455387719
Short name T403
Test name
Test status
Simulation time 535963011 ps
CPU time 0.69 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 183944 kb
Host smart-3204d9b7-b0fa-4d45-9763-9ee2ebd171e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455387719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.455387719
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2777945644
Short name T420
Test name
Test status
Simulation time 432973300 ps
CPU time 0.66 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 183828 kb
Host smart-6329433d-e3a8-4495-bb4b-815642e593cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777945644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2777945644
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1175596244
Short name T315
Test name
Test status
Simulation time 403561431 ps
CPU time 0.86 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:19 PM PDT 24
Peak memory 183896 kb
Host smart-79290d7d-0c75-4f7f-acc7-c276cfcc86b7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175596244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1175596244
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2353916999
Short name T418
Test name
Test status
Simulation time 2190435462 ps
CPU time 1.93 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 184172 kb
Host smart-aff391e3-730f-421d-905e-43cde0c8ed5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353916999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2353916999
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3739289447
Short name T309
Test name
Test status
Simulation time 684979281 ps
CPU time 2.46 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 198820 kb
Host smart-9fe180ac-72f5-4086-aeba-e448ce40c4fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739289447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3739289447
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3647377250
Short name T113
Test name
Test status
Simulation time 4763317255 ps
CPU time 8.79 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 197604 kb
Host smart-9a1bddff-7c77-41a5-a35b-01c8f2435749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647377250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3647377250
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2692500319
Short name T354
Test name
Test status
Simulation time 290056342 ps
CPU time 0.64 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:37 PM PDT 24
Peak memory 183932 kb
Host smart-d55acb17-f0a1-4b2e-b4f7-3337be11ccdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692500319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2692500319
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2556894572
Short name T362
Test name
Test status
Simulation time 425334165 ps
CPU time 1.25 seconds
Started Apr 16 02:10:43 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 183816 kb
Host smart-e081044a-ff33-4ee1-8749-16152d83b0eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556894572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2556894572
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4183592221
Short name T329
Test name
Test status
Simulation time 482208654 ps
CPU time 0.95 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:33 PM PDT 24
Peak memory 183960 kb
Host smart-0ed59459-2174-49dd-8ffd-898ef81558ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183592221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4183592221
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3381927623
Short name T394
Test name
Test status
Simulation time 437583994 ps
CPU time 1.19 seconds
Started Apr 16 02:10:35 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 183924 kb
Host smart-b5c9b911-4a24-4383-8d39-b8dacf080bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381927623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3381927623
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.581126147
Short name T286
Test name
Test status
Simulation time 457896047 ps
CPU time 0.92 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:48 PM PDT 24
Peak memory 183880 kb
Host smart-97a8c8c4-e331-42d0-8c14-f11365495ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581126147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.581126147
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.39097253
Short name T368
Test name
Test status
Simulation time 425255404 ps
CPU time 1.19 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 183792 kb
Host smart-fc3f78d8-f2e9-42d5-8d9e-318df829a2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39097253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.39097253
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.4294493205
Short name T411
Test name
Test status
Simulation time 440263866 ps
CPU time 0.68 seconds
Started Apr 16 02:10:34 PM PDT 24
Finished Apr 16 02:10:37 PM PDT 24
Peak memory 183896 kb
Host smart-57568678-7d18-41ba-9ae1-32dd61632fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294493205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.4294493205
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2691315911
Short name T313
Test name
Test status
Simulation time 456701607 ps
CPU time 0.72 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183936 kb
Host smart-c4e457eb-1a2b-4100-8cf3-7817c68b9987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691315911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2691315911
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2381847145
Short name T334
Test name
Test status
Simulation time 398510748 ps
CPU time 0.65 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183956 kb
Host smart-da2f7492-f8cb-45ff-bb39-8da609c42eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381847145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2381847145
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2755098377
Short name T326
Test name
Test status
Simulation time 405787014 ps
CPU time 1.2 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183896 kb
Host smart-25599c13-c59c-4d45-8a12-0e5bb24e0a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755098377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2755098377
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.103822007
Short name T358
Test name
Test status
Simulation time 404884135 ps
CPU time 1.03 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 183992 kb
Host smart-8228e9e0-3608-4ebd-8a41-b628f0749509
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103822007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_al
iasing.103822007
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3798668680
Short name T319
Test name
Test status
Simulation time 7042339588 ps
CPU time 6.37 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 184296 kb
Host smart-7fb61f80-f2b2-4eee-b3cf-428b0701d943
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798668680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3798668680
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3845815917
Short name T327
Test name
Test status
Simulation time 1203466665 ps
CPU time 2.56 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:26 PM PDT 24
Peak memory 183956 kb
Host smart-492ff490-5412-474d-bed4-d228e18f5b1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845815917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3845815917
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1817233420
Short name T338
Test name
Test status
Simulation time 539788773 ps
CPU time 1.38 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 195900 kb
Host smart-f3ef4bed-bf49-4205-bcb9-b726cf87efcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817233420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1817233420
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2581083492
Short name T68
Test name
Test status
Simulation time 324763593 ps
CPU time 1.06 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 183980 kb
Host smart-61425723-e5e9-477c-8290-2dddb5ca1c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581083492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2581083492
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2788531494
Short name T386
Test name
Test status
Simulation time 299135014 ps
CPU time 0.66 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 183928 kb
Host smart-fbd8b473-8c92-4414-91ef-dfba2c3bd3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788531494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2788531494
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3514325371
Short name T395
Test name
Test status
Simulation time 393333702 ps
CPU time 0.66 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:21 PM PDT 24
Peak memory 183868 kb
Host smart-6a3875cb-53ac-45bc-a1fb-e84aec232f38
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514325371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3514325371
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2449017863
Short name T407
Test name
Test status
Simulation time 445173229 ps
CPU time 0.68 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 183860 kb
Host smart-1a388f5a-1753-475d-8999-2cd1b3c5037d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449017863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2449017863
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4143013218
Short name T355
Test name
Test status
Simulation time 2402516771 ps
CPU time 3.21 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 194868 kb
Host smart-88952785-523e-453b-b411-32389a53d6ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143013218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4143013218
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2915288733
Short name T303
Test name
Test status
Simulation time 750522177 ps
CPU time 2.06 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 198876 kb
Host smart-5723fc90-5734-4596-b21c-4bac192ecf84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915288733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2915288733
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.256484912
Short name T324
Test name
Test status
Simulation time 8463720110 ps
CPU time 4.06 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:26 PM PDT 24
Peak memory 198180 kb
Host smart-3bdb4f6a-d1e8-4723-bfa0-9a98f0ce93c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256484912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.256484912
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2395465461
Short name T310
Test name
Test status
Simulation time 382446465 ps
CPU time 1.13 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183952 kb
Host smart-9c95b1de-9e0d-40b9-87aa-894b6753259c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395465461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2395465461
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.497952362
Short name T307
Test name
Test status
Simulation time 316613996 ps
CPU time 1 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 183932 kb
Host smart-c1379e11-634e-46d7-be11-2d2181e654e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497952362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.497952362
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1979022248
Short name T349
Test name
Test status
Simulation time 355674658 ps
CPU time 0.66 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183892 kb
Host smart-dc34bcff-9b58-46ca-9e10-eee5d1db798d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979022248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1979022248
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1742188094
Short name T297
Test name
Test status
Simulation time 439708431 ps
CPU time 0.88 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:47 PM PDT 24
Peak memory 183956 kb
Host smart-ece84525-27ba-4412-8bf3-9675dd687db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742188094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1742188094
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.275076745
Short name T335
Test name
Test status
Simulation time 483336179 ps
CPU time 1.32 seconds
Started Apr 16 02:10:43 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 183956 kb
Host smart-339ed7e9-b7f1-41e8-8a9d-c621d13bbf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275076745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.275076745
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1956366106
Short name T357
Test name
Test status
Simulation time 491897397 ps
CPU time 0.58 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183948 kb
Host smart-dd278802-87dc-41af-8037-af2da9fe0243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956366106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1956366106
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3144506921
Short name T342
Test name
Test status
Simulation time 427567134 ps
CPU time 0.61 seconds
Started Apr 16 02:10:37 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 183888 kb
Host smart-c76b379a-2cbd-4c82-a84c-ed73d9cc1ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144506921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3144506921
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1608862581
Short name T287
Test name
Test status
Simulation time 489408679 ps
CPU time 0.7 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183952 kb
Host smart-bc82c298-48fd-4644-b6ab-095e8225babe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608862581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1608862581
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1244943120
Short name T366
Test name
Test status
Simulation time 396381950 ps
CPU time 1.12 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:10:41 PM PDT 24
Peak memory 183940 kb
Host smart-1e3225bd-b785-45a3-94a9-4339ef21aa30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244943120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1244943120
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4267463219
Short name T312
Test name
Test status
Simulation time 507448274 ps
CPU time 0.93 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183868 kb
Host smart-7953c325-6ba4-42ca-bd08-9ec374a91bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267463219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4267463219
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1361672444
Short name T377
Test name
Test status
Simulation time 349004969 ps
CPU time 0.94 seconds
Started Apr 16 02:10:20 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 196244 kb
Host smart-d5660824-a114-4904-ae45-5cef819ba9ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361672444 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1361672444
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2980040175
Short name T404
Test name
Test status
Simulation time 491342849 ps
CPU time 1.45 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 193236 kb
Host smart-ce5c5b52-de54-4578-8565-5df74457c1db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980040175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2980040175
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.301444690
Short name T393
Test name
Test status
Simulation time 277886950 ps
CPU time 0.75 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 183900 kb
Host smart-57f34a0c-33f8-40db-af5d-e51faddf847f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301444690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.301444690
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2357992067
Short name T398
Test name
Test status
Simulation time 1165150072 ps
CPU time 2.84 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:22 PM PDT 24
Peak memory 184080 kb
Host smart-c779f2ed-d2bb-4b0c-ac66-e5b29e7114f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357992067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2357992067
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.387431090
Short name T291
Test name
Test status
Simulation time 494192246 ps
CPU time 2.11 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 198916 kb
Host smart-729bbb3a-bc68-4ad3-a2d2-c4124ab861aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387431090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.387431090
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2968763204
Short name T36
Test name
Test status
Simulation time 4318728367 ps
CPU time 2.73 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:26 PM PDT 24
Peak memory 197960 kb
Host smart-8d27c7d4-3b19-4912-b6ee-4b5bc3534fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968763204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2968763204
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2205491021
Short name T383
Test name
Test status
Simulation time 522243267 ps
CPU time 1.37 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 195324 kb
Host smart-f24af66c-712c-4da5-94f7-088fa90bb27b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205491021 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2205491021
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3247860649
Short name T33
Test name
Test status
Simulation time 356827272 ps
CPU time 1.2 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 193348 kb
Host smart-d605ed7a-c6b1-46af-9b83-198a0ec47ee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247860649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3247860649
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4134711369
Short name T413
Test name
Test status
Simulation time 345979019 ps
CPU time 1.06 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 184148 kb
Host smart-dfca4fab-e22e-46d2-9fa3-8b0ebd3d7670
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134711369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4134711369
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1558253816
Short name T323
Test name
Test status
Simulation time 1831981795 ps
CPU time 1.79 seconds
Started Apr 16 02:10:18 PM PDT 24
Finished Apr 16 02:10:20 PM PDT 24
Peak memory 194736 kb
Host smart-e64df139-c445-49b4-9d61-4004228f61b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558253816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1558253816
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2490013501
Short name T336
Test name
Test status
Simulation time 884354198 ps
CPU time 2.54 seconds
Started Apr 16 02:10:19 PM PDT 24
Finished Apr 16 02:10:23 PM PDT 24
Peak memory 198824 kb
Host smart-455bc5aa-ec89-431a-8464-79f5dddc0222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490013501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2490013501
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2988665253
Short name T112
Test name
Test status
Simulation time 4044243677 ps
CPU time 2.34 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 197884 kb
Host smart-69ad80ef-db22-423d-ba54-4bddf3b96afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988665253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2988665253
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1035498709
Short name T364
Test name
Test status
Simulation time 433798560 ps
CPU time 1.31 seconds
Started Apr 16 02:10:22 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 195944 kb
Host smart-430a603c-75b5-414e-a580-44b7a519708d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035498709 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1035498709
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1258038456
Short name T75
Test name
Test status
Simulation time 431677765 ps
CPU time 0.8 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:24 PM PDT 24
Peak memory 183372 kb
Host smart-58fcf5a3-8503-4615-8c54-86b2e0cf93be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258038456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1258038456
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2529830753
Short name T343
Test name
Test status
Simulation time 430748111 ps
CPU time 1.17 seconds
Started Apr 16 02:10:23 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 183936 kb
Host smart-45c3a53a-3d6a-4016-a369-f56fcbbb0e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529830753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2529830753
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.824993549
Short name T405
Test name
Test status
Simulation time 1239588822 ps
CPU time 4.58 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 193524 kb
Host smart-3f8beb24-e306-4797-970f-108b6f420312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824993549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.824993549
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3519787436
Short name T296
Test name
Test status
Simulation time 714989341 ps
CPU time 2.4 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 198248 kb
Host smart-adc43012-750e-40c0-ab71-e253f8457ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519787436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3519787436
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3604055296
Short name T389
Test name
Test status
Simulation time 4461713636 ps
CPU time 7.21 seconds
Started Apr 16 02:10:21 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 198048 kb
Host smart-f9b3575b-47cf-4dc6-bd1e-5a413e6a6bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604055296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3604055296
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2045009267
Short name T388
Test name
Test status
Simulation time 519699264 ps
CPU time 0.81 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:28 PM PDT 24
Peak memory 196764 kb
Host smart-0f5aeb20-61f0-45e3-a1c9-056b0c8c156f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045009267 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2045009267
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2747385855
Short name T331
Test name
Test status
Simulation time 530240952 ps
CPU time 0.77 seconds
Started Apr 16 02:10:28 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 183964 kb
Host smart-31b3d98b-9af4-4270-9a2a-878f57848901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747385855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2747385855
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2752885552
Short name T282
Test name
Test status
Simulation time 482870918 ps
CPU time 1.29 seconds
Started Apr 16 02:10:23 PM PDT 24
Finished Apr 16 02:10:25 PM PDT 24
Peak memory 183940 kb
Host smart-c1710919-6f34-4b0b-9527-3acbfaf5334b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752885552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2752885552
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3702762362
Short name T345
Test name
Test status
Simulation time 1186331138 ps
CPU time 4.13 seconds
Started Apr 16 02:10:25 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 193624 kb
Host smart-dd66502a-6684-4b46-9484-d16beb22a0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702762362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3702762362
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1678377524
Short name T298
Test name
Test status
Simulation time 441888217 ps
CPU time 1.6 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:27 PM PDT 24
Peak memory 197736 kb
Host smart-5ed31f42-8e2e-48cf-8045-474b67172e6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678377524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1678377524
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2888936011
Short name T402
Test name
Test status
Simulation time 8297776106 ps
CPU time 15.96 seconds
Started Apr 16 02:10:24 PM PDT 24
Finished Apr 16 02:10:41 PM PDT 24
Peak memory 197996 kb
Host smart-48b2f02c-0738-4c6f-ab10-35052a80e3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888936011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2888936011
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2897686267
Short name T322
Test name
Test status
Simulation time 413645540 ps
CPU time 1.24 seconds
Started Apr 16 02:10:26 PM PDT 24
Finished Apr 16 02:10:28 PM PDT 24
Peak memory 195972 kb
Host smart-62c6390f-ceed-44c0-8646-a99187fb99a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897686267 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2897686267
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1828039133
Short name T61
Test name
Test status
Simulation time 477940815 ps
CPU time 1.33 seconds
Started Apr 16 02:10:31 PM PDT 24
Finished Apr 16 02:10:34 PM PDT 24
Peak memory 193324 kb
Host smart-55a8b49b-9669-44ce-a40f-e279c0d5b053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828039133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1828039133
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.78891501
Short name T293
Test name
Test status
Simulation time 283120777 ps
CPU time 1 seconds
Started Apr 16 02:10:29 PM PDT 24
Finished Apr 16 02:10:31 PM PDT 24
Peak memory 183960 kb
Host smart-21be2a43-b091-4c77-917e-cacb59747b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78891501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.78891501
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1656142914
Short name T333
Test name
Test status
Simulation time 1412149366 ps
CPU time 1.45 seconds
Started Apr 16 02:10:28 PM PDT 24
Finished Apr 16 02:10:30 PM PDT 24
Peak memory 184224 kb
Host smart-0b5d3f00-f14e-46c2-b28e-fbe3b3a6670e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656142914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1656142914
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1713118037
Short name T284
Test name
Test status
Simulation time 317789701 ps
CPU time 1.54 seconds
Started Apr 16 02:10:30 PM PDT 24
Finished Apr 16 02:10:32 PM PDT 24
Peak memory 198892 kb
Host smart-7af238fb-6a45-4bc7-8e07-1b8194d93f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713118037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1713118037
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4219354847
Short name T110
Test name
Test status
Simulation time 8990185255 ps
CPU time 4.58 seconds
Started Apr 16 02:10:23 PM PDT 24
Finished Apr 16 02:10:29 PM PDT 24
Peak memory 198372 kb
Host smart-6086d381-b0ea-446a-9a20-108b40f2ef94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219354847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4219354847
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3279861194
Short name T153
Test name
Test status
Simulation time 365679905 ps
CPU time 0.83 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183284 kb
Host smart-9a662331-fb4f-4b24-a694-670f533f900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279861194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3279861194
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2135819072
Short name T181
Test name
Test status
Simulation time 23679175541 ps
CPU time 19.12 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:11:17 PM PDT 24
Peak memory 183324 kb
Host smart-03888151-933f-42c4-ab55-912e90348bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135819072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2135819072
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1691916243
Short name T229
Test name
Test status
Simulation time 561467159 ps
CPU time 1 seconds
Started Apr 16 02:10:39 PM PDT 24
Finished Apr 16 02:10:41 PM PDT 24
Peak memory 183268 kb
Host smart-9fca9a28-6068-4a9b-af12-ac75a02ee762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691916243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1691916243
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4203901566
Short name T184
Test name
Test status
Simulation time 262435499935 ps
CPU time 414.44 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:17:44 PM PDT 24
Peak memory 183344 kb
Host smart-4862f5e2-6232-4352-90a7-a1f6fd5dbcd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203901566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4203901566
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1818581313
Short name T12
Test name
Test status
Simulation time 542526404 ps
CPU time 0.77 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:10:53 PM PDT 24
Peak memory 183248 kb
Host smart-5ffab121-55d7-4cfe-be6f-fb98e548c807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818581313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1818581313
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.418957790
Short name T145
Test name
Test status
Simulation time 12532663211 ps
CPU time 2.55 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:10:41 PM PDT 24
Peak memory 183312 kb
Host smart-37b996d2-1dd0-4341-b080-be19de6c9fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418957790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.418957790
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3607966119
Short name T21
Test name
Test status
Simulation time 3912056216 ps
CPU time 3.51 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 214708 kb
Host smart-7ba87546-8122-44e2-ad9c-13d30e83fae5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607966119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3607966119
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3120980898
Short name T1
Test name
Test status
Simulation time 443094909 ps
CPU time 0.89 seconds
Started Apr 16 02:10:44 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 183252 kb
Host smart-094f6360-426a-4a2a-b7cd-0ef9f06bd2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120980898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3120980898
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3922735146
Short name T252
Test name
Test status
Simulation time 50362315150 ps
CPU time 18.92 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 192904 kb
Host smart-40d1edd0-b100-4fa5-90f2-251d3b8b3fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922735146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3922735146
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4097902085
Short name T88
Test name
Test status
Simulation time 22642380876 ps
CPU time 127.62 seconds
Started Apr 16 02:10:37 PM PDT 24
Finished Apr 16 02:12:46 PM PDT 24
Peak memory 198292 kb
Host smart-73b1bf99-e8dc-49b0-b3f6-1bb160e50dd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097902085 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4097902085
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.869120802
Short name T275
Test name
Test status
Simulation time 475011783 ps
CPU time 0.75 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183296 kb
Host smart-d4531794-ad31-4324-9758-555212f273d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869120802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.869120802
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.799927338
Short name T198
Test name
Test status
Simulation time 6058092197 ps
CPU time 3.01 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:10:58 PM PDT 24
Peak memory 183264 kb
Host smart-f5297483-5517-4c4a-a6c4-aa8887b27dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799927338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.799927338
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3094496950
Short name T276
Test name
Test status
Simulation time 361086885 ps
CPU time 1.16 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183272 kb
Host smart-1c81017c-4802-49e7-bd04-b9c9955f571c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094496950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3094496950
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.103210080
Short name T152
Test name
Test status
Simulation time 171891674803 ps
CPU time 269.73 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:15:18 PM PDT 24
Peak memory 194636 kb
Host smart-05084477-5676-4043-93c3-8df93df6cea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103210080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.103210080
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.563156880
Short name T92
Test name
Test status
Simulation time 624456852106 ps
CPU time 949.45 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:26:40 PM PDT 24
Peak memory 202776 kb
Host smart-0707b8e9-eb8d-4803-bd51-d11fe7f58b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563156880 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.563156880
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.408324626
Short name T136
Test name
Test status
Simulation time 528342624 ps
CPU time 0.81 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:10:57 PM PDT 24
Peak memory 183312 kb
Host smart-13c87187-f5a6-49fc-8737-b1eecf3f555b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408324626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.408324626
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1658551881
Short name T125
Test name
Test status
Simulation time 40864795570 ps
CPU time 67.06 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:11:56 PM PDT 24
Peak memory 183376 kb
Host smart-48ab2319-6848-424e-8116-0f735bf0fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658551881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1658551881
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.130602774
Short name T212
Test name
Test status
Simulation time 513504104 ps
CPU time 0.96 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183272 kb
Host smart-95475546-f48b-40a9-b49c-6927a19fc1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130602774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.130602774
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.55626369
Short name T102
Test name
Test status
Simulation time 89023801088 ps
CPU time 118.3 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:12:53 PM PDT 24
Peak memory 193848 kb
Host smart-9a5d31a9-b355-4225-acfb-8df56a0182cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55626369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_al
l.55626369
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1027615660
Short name T130
Test name
Test status
Simulation time 413291018 ps
CPU time 1.21 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183300 kb
Host smart-92d88d36-0d8b-479d-9cd8-b09de6b393d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027615660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1027615660
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3163211479
Short name T25
Test name
Test status
Simulation time 19248200415 ps
CPU time 7.32 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:11:02 PM PDT 24
Peak memory 183216 kb
Host smart-b5456d5a-48c6-415e-925b-9ec06359f12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163211479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3163211479
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2386865132
Short name T209
Test name
Test status
Simulation time 341034721 ps
CPU time 1.15 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:48 PM PDT 24
Peak memory 183288 kb
Host smart-88a5b8d2-d869-4eab-8021-472f535718ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386865132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2386865132
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2423310123
Short name T199
Test name
Test status
Simulation time 100061854211 ps
CPU time 39.73 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:11:36 PM PDT 24
Peak memory 192876 kb
Host smart-a8db9a48-40cf-4402-8ec3-d0ff644cd749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423310123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2423310123
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3061405095
Short name T40
Test name
Test status
Simulation time 148443605036 ps
CPU time 177.22 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:13:53 PM PDT 24
Peak memory 198352 kb
Host smart-53df3ca7-dd87-4046-9209-2dd66058ce3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061405095 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3061405095
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3963096771
Short name T245
Test name
Test status
Simulation time 429725932 ps
CPU time 0.76 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:58 PM PDT 24
Peak memory 183312 kb
Host smart-2a03570a-832e-4f72-99a2-6a23112ec00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963096771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3963096771
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3621822158
Short name T147
Test name
Test status
Simulation time 47125804877 ps
CPU time 29.21 seconds
Started Apr 16 02:10:56 PM PDT 24
Finished Apr 16 02:11:26 PM PDT 24
Peak memory 183296 kb
Host smart-1ecaefbe-c74c-4ba1-b89d-16fea295d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621822158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3621822158
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3003232164
Short name T226
Test name
Test status
Simulation time 369955742 ps
CPU time 0.65 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183260 kb
Host smart-7036092e-6127-4c18-945f-9473d9a21620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003232164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3003232164
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2803222400
Short name T155
Test name
Test status
Simulation time 280569052714 ps
CPU time 100.28 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:12:32 PM PDT 24
Peak memory 194876 kb
Host smart-3ca7af31-0852-4fec-9c26-06827c4313ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803222400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2803222400
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1013502444
Short name T98
Test name
Test status
Simulation time 98607285678 ps
CPU time 761.26 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:23:38 PM PDT 24
Peak memory 213792 kb
Host smart-695bce1e-6276-4b29-94bb-57a7b8ada7ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013502444 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1013502444
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1107879858
Short name T49
Test name
Test status
Simulation time 513069139 ps
CPU time 1.39 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183280 kb
Host smart-01a57503-426a-44cb-9b87-6d07dbad0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107879858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1107879858
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3303136377
Short name T188
Test name
Test status
Simulation time 43117797813 ps
CPU time 4.15 seconds
Started Apr 16 02:10:48 PM PDT 24
Finished Apr 16 02:10:55 PM PDT 24
Peak memory 183308 kb
Host smart-dae5200e-384f-4fd3-aa7c-7e21058767c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303136377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3303136377
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3606142736
Short name T149
Test name
Test status
Simulation time 379538024 ps
CPU time 0.66 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183288 kb
Host smart-edf3700c-3f1e-4481-903c-c1f7e89a69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606142736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3606142736
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4128017686
Short name T114
Test name
Test status
Simulation time 382200325 ps
CPU time 0.71 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:10:55 PM PDT 24
Peak memory 183272 kb
Host smart-cfec528d-74bb-486c-b117-cb1a843fb199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128017686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4128017686
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3532255373
Short name T263
Test name
Test status
Simulation time 34229521759 ps
CPU time 31.11 seconds
Started Apr 16 02:10:56 PM PDT 24
Finished Apr 16 02:11:28 PM PDT 24
Peak memory 183300 kb
Host smart-6a9d0d77-3ea2-4f88-8025-170ee9abcbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532255373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3532255373
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.728080552
Short name T215
Test name
Test status
Simulation time 435543097 ps
CPU time 0.7 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:10:55 PM PDT 24
Peak memory 183240 kb
Host smart-3e5bb085-9e74-4e48-b57b-6b532478976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728080552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.728080552
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1686529667
Short name T118
Test name
Test status
Simulation time 496978317 ps
CPU time 1.3 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:10:57 PM PDT 24
Peak memory 183300 kb
Host smart-b36634cf-cab3-4916-b681-c74a9ec70015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686529667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1686529667
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3476742048
Short name T191
Test name
Test status
Simulation time 2727991489 ps
CPU time 2.5 seconds
Started Apr 16 02:10:48 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183348 kb
Host smart-031d2706-8f1a-43da-ae0e-49aa4be566c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476742048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3476742048
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1744335603
Short name T190
Test name
Test status
Simulation time 405896786 ps
CPU time 0.86 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183232 kb
Host smart-debf1585-8d5a-4d39-9e4f-7cef565216d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744335603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1744335603
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1096805541
Short name T150
Test name
Test status
Simulation time 848895235081 ps
CPU time 622.21 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:21:19 PM PDT 24
Peak memory 192728 kb
Host smart-5d469f89-60da-44c8-a236-cfbfa7452918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096805541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1096805541
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1689047360
Short name T91
Test name
Test status
Simulation time 204010389061 ps
CPU time 725.75 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:23:01 PM PDT 24
Peak memory 200156 kb
Host smart-248d649d-a840-4462-9522-141ffd70021d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689047360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1689047360
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2987990446
Short name T174
Test name
Test status
Simulation time 543299198 ps
CPU time 0.82 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183308 kb
Host smart-c5a89231-e21b-49ff-8b9e-eb2a099d48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987990446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2987990446
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3239125380
Short name T273
Test name
Test status
Simulation time 31555497592 ps
CPU time 11.88 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 183348 kb
Host smart-1fc73f27-7022-4b4d-b052-4391c7d21282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239125380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3239125380
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2795559454
Short name T14
Test name
Test status
Simulation time 511649413 ps
CPU time 1.18 seconds
Started Apr 16 02:10:48 PM PDT 24
Finished Apr 16 02:10:51 PM PDT 24
Peak memory 183300 kb
Host smart-0557b177-178a-4eb9-9e18-6e3f08a32a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795559454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2795559454
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.319900199
Short name T171
Test name
Test status
Simulation time 90884620344 ps
CPU time 149.16 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:13:27 PM PDT 24
Peak memory 183340 kb
Host smart-bf610787-0da8-4656-9dbf-dc2499363ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319900199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.319900199
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3982500977
Short name T278
Test name
Test status
Simulation time 395585212622 ps
CPU time 206.17 seconds
Started Apr 16 02:10:51 PM PDT 24
Finished Apr 16 02:14:19 PM PDT 24
Peak memory 198284 kb
Host smart-9c78a1fd-4f37-421c-b079-47e98132b02c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982500977 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3982500977
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2754820428
Short name T56
Test name
Test status
Simulation time 562415374 ps
CPU time 0.65 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183304 kb
Host smart-11fc684c-8dfa-4e71-8aed-3854a0c386c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754820428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2754820428
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1596520531
Short name T53
Test name
Test status
Simulation time 36184037334 ps
CPU time 16.84 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:11:13 PM PDT 24
Peak memory 183352 kb
Host smart-29cca551-461d-47b1-b5a4-dbe43bd56944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596520531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1596520531
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2732505805
Short name T207
Test name
Test status
Simulation time 462760792 ps
CPU time 0.68 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183292 kb
Host smart-a2056e42-6d1d-4f1a-a5aa-6da3ad9294b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732505805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2732505805
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.201063753
Short name T247
Test name
Test status
Simulation time 97715373317 ps
CPU time 75.29 seconds
Started Apr 16 02:10:56 PM PDT 24
Finished Apr 16 02:12:13 PM PDT 24
Peak memory 183468 kb
Host smart-07a3e09d-bef8-40c3-8e65-a3befc450ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201063753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.201063753
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1234388186
Short name T279
Test name
Test status
Simulation time 169443243314 ps
CPU time 288.82 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:15:42 PM PDT 24
Peak memory 198312 kb
Host smart-5adec49a-bdeb-4909-b3cc-bbef8d7d40e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234388186 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1234388186
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3476258697
Short name T193
Test name
Test status
Simulation time 621667453 ps
CPU time 1.47 seconds
Started Apr 16 02:10:51 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183244 kb
Host smart-1786add9-d8bb-4b22-9070-7c2a4d4525ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476258697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3476258697
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4279576398
Short name T46
Test name
Test status
Simulation time 46521476448 ps
CPU time 32.9 seconds
Started Apr 16 02:10:56 PM PDT 24
Finished Apr 16 02:11:30 PM PDT 24
Peak memory 183344 kb
Host smart-fbfad311-9154-43a9-a797-2103fb1d0d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279576398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4279576398
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1844168813
Short name T169
Test name
Test status
Simulation time 403508734 ps
CPU time 1.23 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183260 kb
Host smart-68666de0-2790-4648-ac25-28e6b2a92daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844168813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1844168813
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.4077352165
Short name T57
Test name
Test status
Simulation time 58796669627 ps
CPU time 6.14 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:11:02 PM PDT 24
Peak memory 183528 kb
Host smart-735644e9-00cf-479c-8742-398860ca6c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077352165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.4077352165
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2574997683
Short name T42
Test name
Test status
Simulation time 50519033967 ps
CPU time 379.66 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:17:16 PM PDT 24
Peak memory 198284 kb
Host smart-4411babc-f32c-4452-a338-e1ede7b93b02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574997683 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2574997683
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.506766171
Short name T50
Test name
Test status
Simulation time 565984961 ps
CPU time 0.78 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183208 kb
Host smart-45e3a0c3-7531-4259-b6a0-83c235abaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506766171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.506766171
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3731996753
Short name T44
Test name
Test status
Simulation time 22133076093 ps
CPU time 6.09 seconds
Started Apr 16 02:10:51 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183368 kb
Host smart-c3884fc2-0188-4c2d-ab1e-8bd8e3ce48f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731996753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3731996753
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.415626841
Short name T22
Test name
Test status
Simulation time 3976860627 ps
CPU time 7.12 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:53 PM PDT 24
Peak memory 214868 kb
Host smart-be6f337d-fc69-418b-b703-83958c14dfd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415626841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.415626841
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.488637111
Short name T139
Test name
Test status
Simulation time 416515244 ps
CPU time 0.72 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183300 kb
Host smart-ddc8243c-28a4-404d-bfa2-4df0b70c69c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488637111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.488637111
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.3922591176
Short name T253
Test name
Test status
Simulation time 340406333838 ps
CPU time 30.48 seconds
Started Apr 16 02:10:39 PM PDT 24
Finished Apr 16 02:11:10 PM PDT 24
Peak memory 195076 kb
Host smart-ec8c0bd2-aaee-4cd5-a45d-60f38f3b27ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922591176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.3922591176
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.558744799
Short name T51
Test name
Test status
Simulation time 45098256618 ps
CPU time 178.54 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:13:48 PM PDT 24
Peak memory 198312 kb
Host smart-43fd1da4-a2fd-49f0-9e53-f31055d8d9f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558744799 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.558744799
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3187222481
Short name T208
Test name
Test status
Simulation time 392250169 ps
CPU time 1.11 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183284 kb
Host smart-6ec51d35-913f-484c-8701-787fa8e8ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187222481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3187222481
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.136825850
Short name T24
Test name
Test status
Simulation time 436905088 ps
CPU time 1.21 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183292 kb
Host smart-e1d4272d-a207-4017-aa36-a70bc43c12c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136825850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.136825850
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2230101709
Short name T28
Test name
Test status
Simulation time 426437557 ps
CPU time 0.88 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:01 PM PDT 24
Peak memory 183312 kb
Host smart-a55efe98-28db-4023-913b-0a5861669f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230101709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2230101709
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2893764125
Short name T281
Test name
Test status
Simulation time 676657963664 ps
CPU time 262.01 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:15:22 PM PDT 24
Peak memory 183376 kb
Host smart-a64c8403-c67e-4ab1-a37d-f3883e698c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893764125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2893764125
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2212829169
Short name T148
Test name
Test status
Simulation time 17073994258 ps
CPU time 187.48 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:14:08 PM PDT 24
Peak memory 198312 kb
Host smart-cd525564-573f-4113-a529-5bef35be3cba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212829169 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2212829169
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3633802135
Short name T16
Test name
Test status
Simulation time 501585123 ps
CPU time 0.78 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183204 kb
Host smart-69c73748-9f0e-4fe0-8ea9-3fc30092b849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633802135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3633802135
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.829772508
Short name T144
Test name
Test status
Simulation time 41017191990 ps
CPU time 18.2 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:18 PM PDT 24
Peak memory 183384 kb
Host smart-e7f43c43-163d-4b47-b570-2b802951e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829772508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.829772508
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.518154384
Short name T237
Test name
Test status
Simulation time 487915741 ps
CPU time 0.99 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183284 kb
Host smart-ea7ad12f-332d-4e27-b7a3-727aedc3f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518154384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.518154384
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1816594151
Short name T269
Test name
Test status
Simulation time 443571103901 ps
CPU time 618.49 seconds
Started Apr 16 02:11:06 PM PDT 24
Finished Apr 16 02:21:26 PM PDT 24
Peak memory 193776 kb
Host smart-7d890b56-f959-4115-be8f-a34b4010a9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816594151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1816594151
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1483783118
Short name T241
Test name
Test status
Simulation time 364937341 ps
CPU time 0.81 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183544 kb
Host smart-4a097483-0e3d-4a7c-bdd4-5389036f4a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483783118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1483783118
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2994951714
Short name T268
Test name
Test status
Simulation time 53269213800 ps
CPU time 82.84 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:12:31 PM PDT 24
Peak memory 183268 kb
Host smart-bea1ca33-aa3d-4fd8-8f4d-5ad8acdc4ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994951714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2994951714
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.412140691
Short name T258
Test name
Test status
Simulation time 531324138 ps
CPU time 0.7 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:05 PM PDT 24
Peak memory 183252 kb
Host smart-fa7b07e8-2dac-4c34-9a32-151a1ee96833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412140691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.412140691
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.633143300
Short name T157
Test name
Test status
Simulation time 219945536488 ps
CPU time 82.77 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:12:19 PM PDT 24
Peak memory 195044 kb
Host smart-d158b74f-a7fb-49d9-90f7-e41332bd7fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633143300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.633143300
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2248592991
Short name T97
Test name
Test status
Simulation time 20762388278 ps
CPU time 153.53 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:13:33 PM PDT 24
Peak memory 198252 kb
Host smart-51fbdc9d-c559-43db-8811-8bc782f53d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248592991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2248592991
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1950426669
Short name T217
Test name
Test status
Simulation time 505853520 ps
CPU time 0.93 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:11:10 PM PDT 24
Peak memory 183200 kb
Host smart-0e3d6161-1621-4ddf-8362-c6c9c7de2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950426669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1950426669
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1697211548
Short name T107
Test name
Test status
Simulation time 27819683652 ps
CPU time 44.68 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:45 PM PDT 24
Peak memory 183308 kb
Host smart-bc2d3b7f-e319-49d8-852f-57e9d4b0fa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697211548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1697211548
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2285127928
Short name T5
Test name
Test status
Simulation time 483703633 ps
CPU time 0.64 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183308 kb
Host smart-edb733bc-b930-4f88-81be-56fdf0550a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285127928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2285127928
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.245247050
Short name T55
Test name
Test status
Simulation time 301433787247 ps
CPU time 421.51 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:18:00 PM PDT 24
Peak memory 191496 kb
Host smart-442135e7-9b6f-4f86-a212-84aabfce41ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245247050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.245247050
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1216656461
Short name T261
Test name
Test status
Simulation time 33197123293 ps
CPU time 342.53 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:16:41 PM PDT 24
Peak memory 198236 kb
Host smart-097cd182-9b6f-402b-97fe-9e32ca1541f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216656461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1216656461
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1924193103
Short name T202
Test name
Test status
Simulation time 366681209 ps
CPU time 0.77 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:01 PM PDT 24
Peak memory 183372 kb
Host smart-928f49d2-6702-433c-80e7-f0c2edd840b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924193103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1924193103
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2573697879
Short name T254
Test name
Test status
Simulation time 5949420965 ps
CPU time 7.44 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 183372 kb
Host smart-1c69c36c-ee86-4225-9573-0212819bf00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573697879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2573697879
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3545189896
Short name T161
Test name
Test status
Simulation time 513206918 ps
CPU time 0.74 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183296 kb
Host smart-5241fb5a-b0bf-46de-8f4a-e4e2e4f6284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545189896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3545189896
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2937155939
Short name T180
Test name
Test status
Simulation time 101668613097 ps
CPU time 164.52 seconds
Started Apr 16 02:11:00 PM PDT 24
Finished Apr 16 02:13:45 PM PDT 24
Peak memory 183356 kb
Host smart-1e086e46-6478-4289-9e2e-e8b5fb76af88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937155939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2937155939
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3661038539
Short name T30
Test name
Test status
Simulation time 31202916552 ps
CPU time 118.29 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:12:58 PM PDT 24
Peak memory 198280 kb
Host smart-edc33308-befd-4283-9887-10c2172a7e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661038539 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3661038539
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3839744980
Short name T151
Test name
Test status
Simulation time 384543468 ps
CPU time 1.15 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:10:58 PM PDT 24
Peak memory 183284 kb
Host smart-c0c787d6-0abe-4aa1-9cfa-806c807c2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839744980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3839744980
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3029848165
Short name T160
Test name
Test status
Simulation time 29930141407 ps
CPU time 50.76 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:11:59 PM PDT 24
Peak memory 183268 kb
Host smart-7fb20226-76a8-49d0-8124-f4140b9c4cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029848165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3029848165
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2271456468
Short name T129
Test name
Test status
Simulation time 490852956 ps
CPU time 1.37 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:01 PM PDT 24
Peak memory 183264 kb
Host smart-b99d1b92-ad28-4238-9ecb-bdf74eb93e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271456468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2271456468
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.301525629
Short name T11
Test name
Test status
Simulation time 399409970114 ps
CPU time 158.25 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:13:34 PM PDT 24
Peak memory 183328 kb
Host smart-80fb7951-7f1e-45f9-8f61-97f790073b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301525629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.301525629
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2610833637
Short name T93
Test name
Test status
Simulation time 233030978912 ps
CPU time 595.55 seconds
Started Apr 16 02:11:00 PM PDT 24
Finished Apr 16 02:20:56 PM PDT 24
Peak memory 199468 kb
Host smart-adf0d77b-a678-4379-9918-e837cc171965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610833637 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2610833637
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.251653615
Short name T131
Test name
Test status
Simulation time 385390467 ps
CPU time 0.73 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183288 kb
Host smart-df89396f-4a94-4ed1-b5c0-00d4b26ce2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251653615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.251653615
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2895398441
Short name T231
Test name
Test status
Simulation time 13953056235 ps
CPU time 4.18 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183408 kb
Host smart-0b60afb0-360f-45a0-9942-b6c33ec89e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895398441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2895398441
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1328832867
Short name T86
Test name
Test status
Simulation time 379734279 ps
CPU time 1.07 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183260 kb
Host smart-d0ef3d85-bfe3-4f67-a5b2-ec8404560bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328832867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1328832867
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1412409068
Short name T256
Test name
Test status
Simulation time 181939676547 ps
CPU time 244.56 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:15:13 PM PDT 24
Peak memory 193280 kb
Host smart-973b3ce9-8f23-44b1-ae88-009c1861e368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412409068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1412409068
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.258869186
Short name T90
Test name
Test status
Simulation time 288926316029 ps
CPU time 597.31 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:20:59 PM PDT 24
Peak memory 198912 kb
Host smart-30b5f342-a626-40da-a40e-b962cf825d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258869186 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.258869186
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2521358637
Short name T27
Test name
Test status
Simulation time 409222001 ps
CPU time 0.81 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:10:56 PM PDT 24
Peak memory 183276 kb
Host smart-be88bf70-5692-40f1-bac9-0092fd7ecac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521358637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2521358637
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2959746600
Short name T103
Test name
Test status
Simulation time 8080717641 ps
CPU time 3.46 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:11:01 PM PDT 24
Peak memory 183348 kb
Host smart-901ff966-e759-4393-b11e-b7f6eca3b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959746600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2959746600
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1765111001
Short name T196
Test name
Test status
Simulation time 440483719 ps
CPU time 0.71 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183276 kb
Host smart-81be07e3-3320-4507-9fc2-c43c2db63fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765111001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1765111001
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3972400378
Short name T234
Test name
Test status
Simulation time 25076104938 ps
CPU time 34.7 seconds
Started Apr 16 02:10:59 PM PDT 24
Finished Apr 16 02:11:35 PM PDT 24
Peak memory 183328 kb
Host smart-c553499a-5d1e-4703-a26b-9566d227d1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972400378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3972400378
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.370482396
Short name T99
Test name
Test status
Simulation time 114120060650 ps
CPU time 896.37 seconds
Started Apr 16 02:10:55 PM PDT 24
Finished Apr 16 02:25:53 PM PDT 24
Peak memory 210876 kb
Host smart-317e2b5c-9a1f-48d5-bbf5-aabec8974107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370482396 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.370482396
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3703368568
Short name T221
Test name
Test status
Simulation time 419151076 ps
CPU time 1.1 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183280 kb
Host smart-1dd10413-d1f5-4370-a579-2d959d5dbec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703368568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3703368568
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3636557631
Short name T211
Test name
Test status
Simulation time 8447086720 ps
CPU time 12.26 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:12 PM PDT 24
Peak memory 183340 kb
Host smart-a6e04bc4-3660-4150-81a0-aac0aa3e3f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636557631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3636557631
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2950973944
Short name T119
Test name
Test status
Simulation time 614604130 ps
CPU time 0.81 seconds
Started Apr 16 02:10:58 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183260 kb
Host smart-55f9034f-3534-40f4-8d08-9d30800decb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950973944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2950973944
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2657887248
Short name T143
Test name
Test status
Simulation time 115844491506 ps
CPU time 82.71 seconds
Started Apr 16 02:11:16 PM PDT 24
Finished Apr 16 02:12:40 PM PDT 24
Peak memory 183556 kb
Host smart-942cc6b1-ca98-43c5-ab5a-7d2117a2206a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657887248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2657887248
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2197991532
Short name T236
Test name
Test status
Simulation time 436042461 ps
CPU time 0.7 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 182800 kb
Host smart-26abfea9-6d74-4a24-957e-6f825e700d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197991532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2197991532
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1930667144
Short name T194
Test name
Test status
Simulation time 4453004354 ps
CPU time 2.19 seconds
Started Apr 16 02:11:06 PM PDT 24
Finished Apr 16 02:11:10 PM PDT 24
Peak memory 183356 kb
Host smart-d85c50a4-e9d4-4412-9262-7ae820e98f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930667144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1930667144
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.102480215
Short name T10
Test name
Test status
Simulation time 359954587 ps
CPU time 1.21 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183272 kb
Host smart-5bd6476e-aa41-4660-b3d5-d736032c5b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102480215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.102480215
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.497992092
Short name T246
Test name
Test status
Simulation time 71318095558 ps
CPU time 99.09 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:12:55 PM PDT 24
Peak memory 183344 kb
Host smart-7b5d28ff-b46b-4a30-9df5-9559b7e2be0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497992092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.497992092
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2974930802
Short name T264
Test name
Test status
Simulation time 259246181046 ps
CPU time 206.59 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:14:28 PM PDT 24
Peak memory 198280 kb
Host smart-0e32d3bb-7046-4c82-beed-60445e64facb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974930802 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2974930802
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3093094911
Short name T224
Test name
Test status
Simulation time 598133077 ps
CPU time 0.99 seconds
Started Apr 16 02:10:41 PM PDT 24
Finished Apr 16 02:10:42 PM PDT 24
Peak memory 183308 kb
Host smart-4b82188b-8ff4-4ee2-b8e0-5acd8694a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093094911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3093094911
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1609511283
Short name T265
Test name
Test status
Simulation time 37018920946 ps
CPU time 8.1 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:59 PM PDT 24
Peak memory 183368 kb
Host smart-a4422b73-a559-4d97-a749-3b9d49158527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609511283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1609511283
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1871823990
Short name T20
Test name
Test status
Simulation time 4298570831 ps
CPU time 2.22 seconds
Started Apr 16 02:10:48 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 215092 kb
Host smart-aa230f01-fe54-498c-8115-9a63b6509621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871823990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1871823990
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2884046123
Short name T84
Test name
Test status
Simulation time 503728144 ps
CPU time 0.76 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:10:40 PM PDT 24
Peak memory 183248 kb
Host smart-93cc4770-f1f0-4224-ba53-9c01ef58b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884046123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2884046123
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2270328856
Short name T187
Test name
Test status
Simulation time 282137067291 ps
CPU time 115.26 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:12:48 PM PDT 24
Peak memory 183368 kb
Host smart-e031d3aa-613d-48fe-92ea-66ed44874357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270328856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2270328856
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3877073375
Short name T39
Test name
Test status
Simulation time 107809458018 ps
CPU time 793.8 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:23:53 PM PDT 24
Peak memory 201172 kb
Host smart-d2c0ed6c-ef78-4834-8fdd-3212425d271f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877073375 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3877073375
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2232817983
Short name T140
Test name
Test status
Simulation time 363858011 ps
CPU time 0.68 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183292 kb
Host smart-45e58c5c-ac95-43e3-bfed-c0202620b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232817983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2232817983
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1788003991
Short name T203
Test name
Test status
Simulation time 10082033962 ps
CPU time 15.53 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:22 PM PDT 24
Peak memory 183316 kb
Host smart-dc942283-c0e3-44b0-9c91-22ba7b3c19de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788003991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1788003991
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3541496183
Short name T280
Test name
Test status
Simulation time 504596165 ps
CPU time 0.72 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183304 kb
Host smart-17ce730d-5ecc-4c81-a082-c5ce443bd43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541496183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3541496183
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2679055688
Short name T85
Test name
Test status
Simulation time 377414814 ps
CPU time 0.87 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:04 PM PDT 24
Peak memory 183276 kb
Host smart-5eb7e157-b47e-42d1-8680-909e46c4a273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679055688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2679055688
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2641951027
Short name T173
Test name
Test status
Simulation time 30622702229 ps
CPU time 46.67 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:49 PM PDT 24
Peak memory 183328 kb
Host smart-c6713f35-f59b-4b5a-ad8b-a6c247b9a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641951027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2641951027
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.940531862
Short name T135
Test name
Test status
Simulation time 476367811 ps
CPU time 1.21 seconds
Started Apr 16 02:11:17 PM PDT 24
Finished Apr 16 02:11:19 PM PDT 24
Peak memory 183244 kb
Host smart-aec199c1-3831-4fcf-9ca4-cca16cd488f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940531862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.940531862
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4041956546
Short name T96
Test name
Test status
Simulation time 79381256355 ps
CPU time 564.72 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:20:36 PM PDT 24
Peak memory 198252 kb
Host smart-28790ac9-3cd1-4735-acba-e3649db64e5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041956546 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4041956546
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3240589634
Short name T239
Test name
Test status
Simulation time 494981767 ps
CPU time 0.73 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:11:13 PM PDT 24
Peak memory 183260 kb
Host smart-ab17617f-907b-4b32-8ef1-ac86cf1d86f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240589634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3240589634
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3760299507
Short name T128
Test name
Test status
Simulation time 16659229437 ps
CPU time 5.56 seconds
Started Apr 16 02:11:09 PM PDT 24
Finished Apr 16 02:11:15 PM PDT 24
Peak memory 183340 kb
Host smart-e68a5f12-5156-4d2d-9ea9-8f68a4c68523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760299507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3760299507
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2682913141
Short name T142
Test name
Test status
Simulation time 445588866 ps
CPU time 1.15 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:11:15 PM PDT 24
Peak memory 183232 kb
Host smart-27ec88b9-3148-45a1-91c3-3a3a8ed41b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682913141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2682913141
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1845362114
Short name T206
Test name
Test status
Simulation time 197821367470 ps
CPU time 324.5 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:16:39 PM PDT 24
Peak memory 193044 kb
Host smart-a51c28b7-4932-415e-8add-77b251421ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845362114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1845362114
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3010146557
Short name T172
Test name
Test status
Simulation time 68088574005 ps
CPU time 704.58 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:22:47 PM PDT 24
Peak memory 199628 kb
Host smart-0c1be690-b35d-4238-8e82-5b1b4af301ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010146557 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3010146557
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4111106563
Short name T170
Test name
Test status
Simulation time 572990961 ps
CPU time 0.78 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:05 PM PDT 24
Peak memory 183312 kb
Host smart-e0df7294-3c82-4edf-b9f4-8c3e859be8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111106563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4111106563
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2938775837
Short name T228
Test name
Test status
Simulation time 31196893956 ps
CPU time 4.76 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183340 kb
Host smart-4a59cda2-696b-4889-b45b-e8b8ab60836e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938775837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2938775837
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2221886740
Short name T267
Test name
Test status
Simulation time 517656303 ps
CPU time 1.34 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:06 PM PDT 24
Peak memory 183544 kb
Host smart-11605b25-0fd1-4e3f-a310-decb80b82ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221886740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2221886740
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.35193535
Short name T251
Test name
Test status
Simulation time 284532013118 ps
CPU time 106.14 seconds
Started Apr 16 02:11:04 PM PDT 24
Finished Apr 16 02:12:52 PM PDT 24
Peak memory 194688 kb
Host smart-40742d8c-552d-4720-a0e4-a657281cad2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35193535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_al
l.35193535
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1496882770
Short name T227
Test name
Test status
Simulation time 310639640742 ps
CPU time 451.94 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:18:37 PM PDT 24
Peak memory 198352 kb
Host smart-28d0c506-87c0-4b7e-a55f-c6412d29eda2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496882770 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1496882770
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1427631714
Short name T205
Test name
Test status
Simulation time 581640257 ps
CPU time 0.72 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:06 PM PDT 24
Peak memory 183312 kb
Host smart-704c2aed-5764-43a2-91d4-3bbc23809817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427631714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1427631714
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2855118662
Short name T271
Test name
Test status
Simulation time 18095860234 ps
CPU time 30.63 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:11:45 PM PDT 24
Peak memory 183316 kb
Host smart-7bd604f0-69c4-4e51-a32d-85a284f80bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855118662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2855118662
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2204290362
Short name T8
Test name
Test status
Simulation time 338323998 ps
CPU time 1.04 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 183280 kb
Host smart-02a5b960-043a-404d-847d-b3b7af06345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204290362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2204290362
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.138942294
Short name T259
Test name
Test status
Simulation time 125036573911 ps
CPU time 190.15 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:14:14 PM PDT 24
Peak memory 194936 kb
Host smart-498f8907-8439-4333-aaed-475588446745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138942294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.138942294
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3245312333
Short name T13
Test name
Test status
Simulation time 80532648829 ps
CPU time 835.3 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:24:59 PM PDT 24
Peak memory 202616 kb
Host smart-c8c35592-cde3-4ee2-a22c-eb61cc5a0278
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245312333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3245312333
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1013798512
Short name T262
Test name
Test status
Simulation time 623736264 ps
CPU time 0.78 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:05 PM PDT 24
Peak memory 183288 kb
Host smart-dd623451-97e7-4c06-a71f-b28a11e77a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013798512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1013798512
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2258029075
Short name T133
Test name
Test status
Simulation time 61203957557 ps
CPU time 102.94 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:12:46 PM PDT 24
Peak memory 183340 kb
Host smart-a055624e-b7f1-4261-a578-1f0fc2c965d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258029075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2258029075
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3769008256
Short name T7
Test name
Test status
Simulation time 448662922 ps
CPU time 0.79 seconds
Started Apr 16 02:11:19 PM PDT 24
Finished Apr 16 02:11:21 PM PDT 24
Peak memory 183288 kb
Host smart-d14f6ad3-2e84-48ae-bcf5-47df720ee951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769008256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3769008256
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.543743759
Short name T266
Test name
Test status
Simulation time 79874800793 ps
CPU time 126.78 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:13:11 PM PDT 24
Peak memory 183364 kb
Host smart-89090757-4054-4cfb-baa4-369f076c7a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543743759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.543743759
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.663689614
Short name T124
Test name
Test status
Simulation time 24707628251 ps
CPU time 98.79 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:12:45 PM PDT 24
Peak memory 198328 kb
Host smart-95e71a3d-ece7-4a68-96f3-e5ac76f01917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663689614 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.663689614
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2368897332
Short name T146
Test name
Test status
Simulation time 426801223 ps
CPU time 0.7 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:11:02 PM PDT 24
Peak memory 183256 kb
Host smart-08b7a7e4-b374-4c91-9ec8-812389418219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368897332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2368897332
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2343633879
Short name T158
Test name
Test status
Simulation time 35600954399 ps
CPU time 49.8 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:56 PM PDT 24
Peak memory 183356 kb
Host smart-baf0193d-8030-4f3a-81ca-763918902279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343633879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2343633879
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.143466840
Short name T200
Test name
Test status
Simulation time 377017709 ps
CPU time 1.15 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:11:12 PM PDT 24
Peak memory 183292 kb
Host smart-1de3bc2d-7263-4529-9c43-b99ddb0485e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143466840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.143466840
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.580828024
Short name T235
Test name
Test status
Simulation time 62488382575 ps
CPU time 23.36 seconds
Started Apr 16 02:11:00 PM PDT 24
Finished Apr 16 02:11:24 PM PDT 24
Peak memory 183376 kb
Host smart-5443f594-4b6e-4f62-a8b1-bba2c24c231b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580828024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.580828024
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.764799658
Short name T219
Test name
Test status
Simulation time 47585812835 ps
CPU time 371.16 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:17:14 PM PDT 24
Peak memory 198304 kb
Host smart-1a824ee1-8fe6-42db-aefe-401c08ef0548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764799658 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.764799658
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3288665978
Short name T257
Test name
Test status
Simulation time 549790868 ps
CPU time 1.43 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 183280 kb
Host smart-92ff96a6-7fe1-4020-a313-bcc9614653db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288665978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3288665978
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2294478263
Short name T132
Test name
Test status
Simulation time 11635698380 ps
CPU time 5.34 seconds
Started Apr 16 02:11:04 PM PDT 24
Finished Apr 16 02:11:11 PM PDT 24
Peak memory 183380 kb
Host smart-a52f5b44-2e7d-4a53-89a2-8a37e0eaa2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294478263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2294478263
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1504259752
Short name T154
Test name
Test status
Simulation time 507845707 ps
CPU time 0.86 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:08 PM PDT 24
Peak memory 183268 kb
Host smart-6eea9998-82f4-4ffb-920f-cc9c05b55b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504259752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1504259752
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3343415563
Short name T197
Test name
Test status
Simulation time 100281991024 ps
CPU time 149.71 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:13:46 PM PDT 24
Peak memory 183280 kb
Host smart-053e3e86-dfdd-4e0c-adb5-52639d86f343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343415563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3343415563
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2688278786
Short name T270
Test name
Test status
Simulation time 720945721762 ps
CPU time 384.72 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:17:30 PM PDT 24
Peak memory 198304 kb
Host smart-97fd2284-fced-4ef7-ab58-2b430a282fb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688278786 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2688278786
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.564017941
Short name T116
Test name
Test status
Simulation time 538978387 ps
CPU time 0.99 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:06 PM PDT 24
Peak memory 183244 kb
Host smart-8c08a320-91b3-4216-ba6a-5be5db440a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564017941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.564017941
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3600428779
Short name T122
Test name
Test status
Simulation time 3830022176 ps
CPU time 2.11 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:11:05 PM PDT 24
Peak memory 183288 kb
Host smart-dc087dc6-bfcb-4986-8e96-a2a01c2d7200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600428779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3600428779
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.4046104936
Short name T162
Test name
Test status
Simulation time 427349985 ps
CPU time 1.27 seconds
Started Apr 16 02:11:04 PM PDT 24
Finished Apr 16 02:11:07 PM PDT 24
Peak memory 183264 kb
Host smart-5225322c-c6fd-435e-b06b-e31927c5c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046104936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.4046104936
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.636552054
Short name T213
Test name
Test status
Simulation time 101497352190 ps
CPU time 159.51 seconds
Started Apr 16 02:11:02 PM PDT 24
Finished Apr 16 02:13:42 PM PDT 24
Peak memory 183332 kb
Host smart-3139cb6d-b805-4a55-98bb-524197f98b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636552054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.636552054
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.622167276
Short name T95
Test name
Test status
Simulation time 117485141285 ps
CPU time 148.09 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:13:30 PM PDT 24
Peak memory 198316 kb
Host smart-c9631240-7673-431d-9e84-ccf4b1efd69d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622167276 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.622167276
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.419389637
Short name T255
Test name
Test status
Simulation time 478426894 ps
CPU time 0.57 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:11:15 PM PDT 24
Peak memory 183288 kb
Host smart-79a51d62-b18e-4758-b262-261b1b502a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419389637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.419389637
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1628129883
Short name T120
Test name
Test status
Simulation time 46192672659 ps
CPU time 18.04 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:25 PM PDT 24
Peak memory 183272 kb
Host smart-60ace50c-3385-450e-bd8b-094d50b01ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628129883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1628129883
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2800933303
Short name T260
Test name
Test status
Simulation time 334975298 ps
CPU time 0.98 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:06 PM PDT 24
Peak memory 183308 kb
Host smart-afb0a03d-9994-41dd-9f91-d2eb6e703e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800933303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2800933303
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.404268742
Short name T277
Test name
Test status
Simulation time 4907969255 ps
CPU time 2.89 seconds
Started Apr 16 02:11:03 PM PDT 24
Finished Apr 16 02:11:07 PM PDT 24
Peak memory 194824 kb
Host smart-74d22743-ce8a-4f72-94fd-261a2b9b304e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404268742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.404268742
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.442444392
Short name T89
Test name
Test status
Simulation time 58952015712 ps
CPU time 629.34 seconds
Started Apr 16 02:11:01 PM PDT 24
Finished Apr 16 02:21:31 PM PDT 24
Peak memory 198340 kb
Host smart-6dc5a9ab-7443-4c4b-95b7-f3b22b38d6f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442444392 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.442444392
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.767110936
Short name T244
Test name
Test status
Simulation time 547788769 ps
CPU time 1.42 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:10:54 PM PDT 24
Peak memory 183280 kb
Host smart-6a1ae963-e5c2-4da1-8ed9-d2aa3d0e7f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767110936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.767110936
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3721421473
Short name T232
Test name
Test status
Simulation time 57413649073 ps
CPU time 40.84 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:11:30 PM PDT 24
Peak memory 183412 kb
Host smart-f6098e35-af09-41e2-b5c4-10f1a90a3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721421473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3721421473
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3411972358
Short name T18
Test name
Test status
Simulation time 4217347043 ps
CPU time 6.83 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 214832 kb
Host smart-fb4c9f37-ed5e-4e22-ba64-b33333cfc3e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411972358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3411972358
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.571304715
Short name T220
Test name
Test status
Simulation time 398214628 ps
CPU time 0.61 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:51 PM PDT 24
Peak memory 183172 kb
Host smart-23ded517-b494-4676-836e-89dafe48233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571304715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.571304715
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1217058018
Short name T243
Test name
Test status
Simulation time 67529008758 ps
CPU time 13.92 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:11:12 PM PDT 24
Peak memory 194756 kb
Host smart-1daec1da-a9ea-4fa5-be78-4bf82452ecb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217058018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1217058018
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2831286271
Short name T274
Test name
Test status
Simulation time 118236451636 ps
CPU time 223.71 seconds
Started Apr 16 02:10:50 PM PDT 24
Finished Apr 16 02:14:36 PM PDT 24
Peak memory 198300 kb
Host smart-c0dccbef-01af-4d78-b3e9-9f4178dbf6b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831286271 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2831286271
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2015866468
Short name T204
Test name
Test status
Simulation time 515384128 ps
CPU time 0.72 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183220 kb
Host smart-8778205b-51d9-4dbc-a939-3c338d6f5f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015866468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2015866468
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3649620455
Short name T240
Test name
Test status
Simulation time 16414839792 ps
CPU time 2.59 seconds
Started Apr 16 02:11:05 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 182904 kb
Host smart-9c48e5de-9364-4d30-9cda-995b1c31b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649620455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3649620455
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.831786996
Short name T115
Test name
Test status
Simulation time 445256128 ps
CPU time 1.21 seconds
Started Apr 16 02:11:06 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183284 kb
Host smart-ddf2e4f6-9017-498c-ba6d-4f5cab77df90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831786996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.831786996
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.4191346968
Short name T165
Test name
Test status
Simulation time 222514509221 ps
CPU time 337.32 seconds
Started Apr 16 02:11:06 PM PDT 24
Finished Apr 16 02:16:45 PM PDT 24
Peak memory 193368 kb
Host smart-7cbcee7e-510d-485e-849f-ff970e081361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191346968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.4191346968
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2491368720
Short name T201
Test name
Test status
Simulation time 358646043 ps
CPU time 1.22 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:11:17 PM PDT 24
Peak memory 183288 kb
Host smart-ad344bf5-0c26-4dd7-a045-59ec90d77925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491368720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2491368720
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.808447915
Short name T156
Test name
Test status
Simulation time 49392171985 ps
CPU time 17.12 seconds
Started Apr 16 02:11:06 PM PDT 24
Finished Apr 16 02:11:24 PM PDT 24
Peak memory 183252 kb
Host smart-94e8a15a-2dbd-43b7-a4b3-5fa9691a3a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808447915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.808447915
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3611662137
Short name T192
Test name
Test status
Simulation time 405601036 ps
CPU time 1.2 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:11:13 PM PDT 24
Peak memory 183312 kb
Host smart-61b50b40-f1ce-4783-b360-4b14abaa16ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611662137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3611662137
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3235249139
Short name T6
Test name
Test status
Simulation time 83025056589 ps
CPU time 33.82 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:11:49 PM PDT 24
Peak memory 192696 kb
Host smart-ca2fd295-1b84-4a1f-8604-9e3e5757c984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235249139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3235249139
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1895080646
Short name T101
Test name
Test status
Simulation time 21612672712 ps
CPU time 178.78 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:14:15 PM PDT 24
Peak memory 198292 kb
Host smart-5d97eedc-ac93-4ba3-a932-7a9a2db6ae86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895080646 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1895080646
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3282257706
Short name T248
Test name
Test status
Simulation time 377548128 ps
CPU time 0.6 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183308 kb
Host smart-396e4f44-afa5-4a63-a5eb-68d672d0dc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282257706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3282257706
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.71710448
Short name T45
Test name
Test status
Simulation time 33115363128 ps
CPU time 6.9 seconds
Started Apr 16 02:11:08 PM PDT 24
Finished Apr 16 02:11:16 PM PDT 24
Peak memory 183272 kb
Host smart-4d300a94-6b0e-40cc-b8b7-55cd92d85c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71710448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.71710448
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3317212259
Short name T177
Test name
Test status
Simulation time 486058241 ps
CPU time 0.92 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:11:11 PM PDT 24
Peak memory 183316 kb
Host smart-80eec134-3569-428e-af6c-e12046386886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317212259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3317212259
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.156486057
Short name T250
Test name
Test status
Simulation time 142000903427 ps
CPU time 207.42 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:14:36 PM PDT 24
Peak memory 183344 kb
Host smart-be32efcc-5ffc-4568-a45a-22e487a83b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156486057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.156486057
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2385327491
Short name T210
Test name
Test status
Simulation time 577118729 ps
CPU time 1.45 seconds
Started Apr 16 02:11:09 PM PDT 24
Finished Apr 16 02:11:11 PM PDT 24
Peak memory 183264 kb
Host smart-e1a54d40-b79f-45ab-912e-ec7d77127ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385327491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2385327491
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2293015505
Short name T48
Test name
Test status
Simulation time 48634375115 ps
CPU time 25.58 seconds
Started Apr 16 02:11:17 PM PDT 24
Finished Apr 16 02:11:43 PM PDT 24
Peak memory 183340 kb
Host smart-c6634902-93e5-4888-9cc3-fad921d779ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293015505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2293015505
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1401431918
Short name T159
Test name
Test status
Simulation time 461573759 ps
CPU time 0.72 seconds
Started Apr 16 02:11:08 PM PDT 24
Finished Apr 16 02:11:10 PM PDT 24
Peak memory 183276 kb
Host smart-e23301ba-f6f0-4d1c-bb10-1f81eaa99d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401431918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1401431918
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4197627505
Short name T242
Test name
Test status
Simulation time 413242392404 ps
CPU time 619.21 seconds
Started Apr 16 02:11:16 PM PDT 24
Finished Apr 16 02:21:37 PM PDT 24
Peak memory 183380 kb
Host smart-a7c86e70-45cf-4ab7-875a-2e66f7bfabdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197627505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4197627505
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1845268564
Short name T43
Test name
Test status
Simulation time 43187474069 ps
CPU time 456.89 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:18:51 PM PDT 24
Peak memory 198364 kb
Host smart-a478fd30-dd6c-408f-966f-c7aee7de12b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845268564 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1845268564
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2695951037
Short name T166
Test name
Test status
Simulation time 561310873 ps
CPU time 0.98 seconds
Started Apr 16 02:11:17 PM PDT 24
Finished Apr 16 02:11:19 PM PDT 24
Peak memory 183312 kb
Host smart-595f6104-2a85-46b1-94f0-957ad4a096c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695951037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2695951037
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.973997081
Short name T108
Test name
Test status
Simulation time 60652938538 ps
CPU time 12.71 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:11:25 PM PDT 24
Peak memory 183336 kb
Host smart-bf3b5f2d-9d8f-4130-b3d0-73e6c96ae17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973997081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.973997081
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.711191286
Short name T23
Test name
Test status
Simulation time 467785678 ps
CPU time 0.76 seconds
Started Apr 16 02:11:19 PM PDT 24
Finished Apr 16 02:11:21 PM PDT 24
Peak memory 183252 kb
Host smart-151853f1-b1b8-4b56-a526-44465f82a831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711191286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.711191286
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1251642847
Short name T249
Test name
Test status
Simulation time 124137938264 ps
CPU time 23.31 seconds
Started Apr 16 02:11:09 PM PDT 24
Finished Apr 16 02:11:33 PM PDT 24
Peak memory 192976 kb
Host smart-8434330d-72a6-428e-883d-e10cb1dedab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251642847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1251642847
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3157037397
Short name T225
Test name
Test status
Simulation time 36551782561 ps
CPU time 383.09 seconds
Started Apr 16 02:11:17 PM PDT 24
Finished Apr 16 02:17:41 PM PDT 24
Peak memory 198300 kb
Host smart-5cb951f7-5552-473f-b040-84a0bd360d16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157037397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3157037397
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2650952756
Short name T178
Test name
Test status
Simulation time 505926208 ps
CPU time 0.96 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:11:17 PM PDT 24
Peak memory 183260 kb
Host smart-1213451c-6a5c-4126-bfcc-21e0b4efebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650952756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2650952756
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2244107258
Short name T52
Test name
Test status
Simulation time 39951470407 ps
CPU time 16.16 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:11:32 PM PDT 24
Peak memory 183316 kb
Host smart-baa805ec-0e3a-4056-9801-2350df0b90d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244107258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2244107258
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1286913492
Short name T176
Test name
Test status
Simulation time 609160451 ps
CPU time 0.87 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:11:16 PM PDT 24
Peak memory 183296 kb
Host smart-6dab4a33-631d-4c7f-b644-633a9dd399c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286913492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1286913492
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1449434285
Short name T175
Test name
Test status
Simulation time 250337653176 ps
CPU time 175.89 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:14:08 PM PDT 24
Peak memory 183360 kb
Host smart-6d12c06b-00d5-4243-a45b-cd7b585281ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449434285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1449434285
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1865672494
Short name T272
Test name
Test status
Simulation time 60813556455 ps
CPU time 181.66 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:14:16 PM PDT 24
Peak memory 198336 kb
Host smart-056d3e6a-233e-4f80-a1e1-4c449b1c0381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865672494 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1865672494
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.801376037
Short name T179
Test name
Test status
Simulation time 379830165 ps
CPU time 1.22 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:11:12 PM PDT 24
Peak memory 183272 kb
Host smart-7996e781-1e58-47bf-be74-432341db2bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801376037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.801376037
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2573156234
Short name T168
Test name
Test status
Simulation time 7381810298 ps
CPU time 12.16 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:11:24 PM PDT 24
Peak memory 183372 kb
Host smart-5e317fbc-aecd-48d8-ba30-3cf08fdb0a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573156234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2573156234
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2680363650
Short name T2
Test name
Test status
Simulation time 491438592 ps
CPU time 0.84 seconds
Started Apr 16 02:11:17 PM PDT 24
Finished Apr 16 02:11:19 PM PDT 24
Peak memory 183296 kb
Host smart-8f8d4afa-70c3-4596-8e17-87207ea5ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680363650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2680363650
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1063535089
Short name T223
Test name
Test status
Simulation time 268452261550 ps
CPU time 97.67 seconds
Started Apr 16 02:11:10 PM PDT 24
Finished Apr 16 02:12:49 PM PDT 24
Peak memory 193908 kb
Host smart-600993aa-c652-4c7e-900a-3f4dfa784e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063535089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1063535089
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.732946102
Short name T222
Test name
Test status
Simulation time 443292234 ps
CPU time 0.68 seconds
Started Apr 16 02:11:11 PM PDT 24
Finished Apr 16 02:11:12 PM PDT 24
Peak memory 183288 kb
Host smart-352f332a-fa3e-4dc0-a0e0-b6547d4b054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732946102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.732946102
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2907068690
Short name T100
Test name
Test status
Simulation time 1340579208 ps
CPU time 0.67 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:11:17 PM PDT 24
Peak memory 183188 kb
Host smart-fd5b06cb-0a58-4e4b-946f-51bddbfdf886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907068690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2907068690
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3487796724
Short name T214
Test name
Test status
Simulation time 515705928 ps
CPU time 1 seconds
Started Apr 16 02:11:16 PM PDT 24
Finished Apr 16 02:11:18 PM PDT 24
Peak memory 183296 kb
Host smart-e80cfdd0-23da-4c26-bd7a-30c7bcf299cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487796724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3487796724
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1557307850
Short name T104
Test name
Test status
Simulation time 298553820077 ps
CPU time 460.98 seconds
Started Apr 16 02:11:07 PM PDT 24
Finished Apr 16 02:18:49 PM PDT 24
Peak memory 194944 kb
Host smart-3bccc692-bbd8-43e7-976e-be627a55a562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557307850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1557307850
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3561200109
Short name T189
Test name
Test status
Simulation time 97107243917 ps
CPU time 385.54 seconds
Started Apr 16 02:11:18 PM PDT 24
Finished Apr 16 02:17:44 PM PDT 24
Peak memory 198332 kb
Host smart-deb6d856-5d3f-48a4-8482-fb23a4f4c325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561200109 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3561200109
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2393785301
Short name T183
Test name
Test status
Simulation time 609362378 ps
CPU time 1.51 seconds
Started Apr 16 02:11:16 PM PDT 24
Finished Apr 16 02:11:19 PM PDT 24
Peak memory 183264 kb
Host smart-095048f7-7754-4a85-a0b6-161b33e5bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393785301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2393785301
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.323130192
Short name T167
Test name
Test status
Simulation time 8725924872 ps
CPU time 12.31 seconds
Started Apr 16 02:11:19 PM PDT 24
Finished Apr 16 02:11:32 PM PDT 24
Peak memory 183324 kb
Host smart-93420df9-735b-4071-8ad6-5da26545845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323130192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.323130192
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1133204860
Short name T29
Test name
Test status
Simulation time 571078830 ps
CPU time 0.64 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:11:15 PM PDT 24
Peak memory 183260 kb
Host smart-38cf49ee-d164-4e5c-9823-8a2091606c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133204860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1133204860
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2603501837
Short name T164
Test name
Test status
Simulation time 221189269647 ps
CPU time 86.32 seconds
Started Apr 16 02:11:22 PM PDT 24
Finished Apr 16 02:12:49 PM PDT 24
Peak memory 183356 kb
Host smart-5accc7ff-bf7f-44d0-bd12-6b2af51c9bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603501837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2603501837
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.438713011
Short name T37
Test name
Test status
Simulation time 198865338270 ps
CPU time 394.46 seconds
Started Apr 16 02:11:14 PM PDT 24
Finished Apr 16 02:17:50 PM PDT 24
Peak memory 198276 kb
Host smart-410a969c-5d96-4231-9e04-463d8148e175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438713011 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.438713011
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2010510341
Short name T47
Test name
Test status
Simulation time 504907956 ps
CPU time 1.32 seconds
Started Apr 16 02:11:13 PM PDT 24
Finished Apr 16 02:11:15 PM PDT 24
Peak memory 183300 kb
Host smart-7eba1a53-643e-48ae-9851-dab6811da0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010510341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2010510341
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3570086322
Short name T238
Test name
Test status
Simulation time 34946310112 ps
CPU time 23.9 seconds
Started Apr 16 02:11:22 PM PDT 24
Finished Apr 16 02:11:47 PM PDT 24
Peak memory 183340 kb
Host smart-d6f81865-eb4a-4024-9997-7d8b5374b33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570086322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3570086322
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.966370493
Short name T233
Test name
Test status
Simulation time 535566575 ps
CPU time 0.97 seconds
Started Apr 16 02:11:16 PM PDT 24
Finished Apr 16 02:11:18 PM PDT 24
Peak memory 183208 kb
Host smart-27198053-44b5-4a6f-8e6e-3fc0e09a4225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966370493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.966370493
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3084157671
Short name T121
Test name
Test status
Simulation time 36783443706 ps
CPU time 57.82 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:12:14 PM PDT 24
Peak memory 183376 kb
Host smart-bfa2dff1-d05b-4027-809c-083d7d63e421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084157671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3084157671
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1694254180
Short name T186
Test name
Test status
Simulation time 2327348612 ps
CPU time 13.31 seconds
Started Apr 16 02:11:15 PM PDT 24
Finished Apr 16 02:11:29 PM PDT 24
Peak memory 198300 kb
Host smart-0d7bc41d-3d1c-4fc7-8ff3-0b5513be67c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694254180 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1694254180
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3652597936
Short name T127
Test name
Test status
Simulation time 528386633 ps
CPU time 0.63 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:10:39 PM PDT 24
Peak memory 183248 kb
Host smart-82dec307-51d0-4e4b-9a6c-d4879e576f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652597936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3652597936
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3229717226
Short name T105
Test name
Test status
Simulation time 31925840907 ps
CPU time 10.47 seconds
Started Apr 16 02:10:37 PM PDT 24
Finished Apr 16 02:10:48 PM PDT 24
Peak memory 183332 kb
Host smart-4dad35f2-3ed7-49b4-9ea8-f02f9b71f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229717226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3229717226
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3265745869
Short name T26
Test name
Test status
Simulation time 471467492 ps
CPU time 0.7 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:10:49 PM PDT 24
Peak memory 183304 kb
Host smart-49f787fb-6bdf-4e5f-9cd9-9fe07b1e4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265745869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3265745869
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2107470209
Short name T117
Test name
Test status
Simulation time 91959150743 ps
CPU time 49.42 seconds
Started Apr 16 02:10:52 PM PDT 24
Finished Apr 16 02:11:43 PM PDT 24
Peak memory 183352 kb
Host smart-d2e2bf2e-5fb1-4ab0-bd87-f491a8f6b618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107470209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2107470209
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.822998235
Short name T17
Test name
Test status
Simulation time 22907254882 ps
CPU time 228.19 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:14:43 PM PDT 24
Peak memory 198332 kb
Host smart-7102e076-2f5a-4a8e-8d56-db90317318e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822998235 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.822998235
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.808636720
Short name T123
Test name
Test status
Simulation time 490341384 ps
CPU time 1.23 seconds
Started Apr 16 02:10:38 PM PDT 24
Finished Apr 16 02:10:40 PM PDT 24
Peak memory 183316 kb
Host smart-cad0fe1e-3da2-492f-88cb-92b0700e4094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808636720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.808636720
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.148912700
Short name T106
Test name
Test status
Simulation time 37965412165 ps
CPU time 30.02 seconds
Started Apr 16 02:10:39 PM PDT 24
Finished Apr 16 02:11:10 PM PDT 24
Peak memory 183340 kb
Host smart-61bd4a2e-7a42-4c0e-861b-e9ffb1c8f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148912700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.148912700
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3469278618
Short name T218
Test name
Test status
Simulation time 624574558 ps
CPU time 0.63 seconds
Started Apr 16 02:10:36 PM PDT 24
Finished Apr 16 02:10:38 PM PDT 24
Peak memory 183292 kb
Host smart-ed172339-6ad0-4703-b3ed-502fd31c5021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469278618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3469278618
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.661557746
Short name T141
Test name
Test status
Simulation time 54121664127 ps
CPU time 117.36 seconds
Started Apr 16 02:10:53 PM PDT 24
Finished Apr 16 02:12:52 PM PDT 24
Peak memory 198264 kb
Host smart-1e17d88e-7a52-4821-bc2b-6d4a383aa98e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661557746 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.661557746
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2748344918
Short name T138
Test name
Test status
Simulation time 611626108 ps
CPU time 0.95 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183284 kb
Host smart-9b2d2b17-4386-4356-b929-c090d71745f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748344918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2748344918
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.999604633
Short name T134
Test name
Test status
Simulation time 20148104479 ps
CPU time 17.45 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:11:09 PM PDT 24
Peak memory 183372 kb
Host smart-2ac228f3-4389-4f53-a412-b72d75e05d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999604633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.999604633
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3537902234
Short name T126
Test name
Test status
Simulation time 418093877 ps
CPU time 0.87 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183264 kb
Host smart-72425039-55c7-428c-8996-a244ea22631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537902234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3537902234
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1069993361
Short name T182
Test name
Test status
Simulation time 12855665698 ps
CPU time 101.44 seconds
Started Apr 16 02:10:54 PM PDT 24
Finished Apr 16 02:12:36 PM PDT 24
Peak memory 198276 kb
Host smart-6e127af6-9c15-40a9-a459-6260f1e560cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069993361 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1069993361
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2644004668
Short name T4
Test name
Test status
Simulation time 573636420 ps
CPU time 1 seconds
Started Apr 16 02:10:49 PM PDT 24
Finished Apr 16 02:10:52 PM PDT 24
Peak memory 183212 kb
Host smart-6c915168-203b-46ef-a8d5-507eac8719b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644004668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2644004668
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.148091790
Short name T216
Test name
Test status
Simulation time 1483359785 ps
CPU time 2.82 seconds
Started Apr 16 02:10:57 PM PDT 24
Finished Apr 16 02:11:00 PM PDT 24
Peak memory 183308 kb
Host smart-e53ffd77-e94c-44e6-ba52-e95a332cf373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148091790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.148091790
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3346275559
Short name T195
Test name
Test status
Simulation time 510937228 ps
CPU time 0.61 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183224 kb
Host smart-3f589d36-5b66-4f6b-90b1-3d0947f6c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346275559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3346275559
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2433548054
Short name T54
Test name
Test status
Simulation time 95874994289 ps
CPU time 30.8 seconds
Started Apr 16 02:10:45 PM PDT 24
Finished Apr 16 02:11:17 PM PDT 24
Peak memory 191556 kb
Host smart-b3392347-6308-43d1-ad58-e3fddd923846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433548054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2433548054
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3738816513
Short name T137
Test name
Test status
Simulation time 334825404662 ps
CPU time 712.53 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:22:41 PM PDT 24
Peak memory 213672 kb
Host smart-bad9bd1f-520e-444f-829d-1337b32cd3b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738816513 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3738816513
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.980100233
Short name T185
Test name
Test status
Simulation time 589041692 ps
CPU time 1 seconds
Started Apr 16 02:10:51 PM PDT 24
Finished Apr 16 02:10:53 PM PDT 24
Peak memory 183244 kb
Host smart-1cd887a2-8232-46c8-8c91-47d2abdf43fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980100233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.980100233
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.790384652
Short name T163
Test name
Test status
Simulation time 15850626439 ps
CPU time 6.37 seconds
Started Apr 16 02:10:43 PM PDT 24
Finished Apr 16 02:10:50 PM PDT 24
Peak memory 183352 kb
Host smart-7746ac75-2791-4763-bec0-22419c28f191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790384652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.790384652
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2068109288
Short name T230
Test name
Test status
Simulation time 590052102 ps
CPU time 0.8 seconds
Started Apr 16 02:10:43 PM PDT 24
Finished Apr 16 02:10:45 PM PDT 24
Peak memory 183256 kb
Host smart-e9a4a2a3-a118-4a80-ab2a-a88caa68abef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068109288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2068109288
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.555626747
Short name T83
Test name
Test status
Simulation time 87990281539 ps
CPU time 61.17 seconds
Started Apr 16 02:10:47 PM PDT 24
Finished Apr 16 02:11:51 PM PDT 24
Peak memory 194288 kb
Host smart-b0a0e36f-7c57-454e-93e7-7fb97ce6948b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555626747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.555626747
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2492118646
Short name T41
Test name
Test status
Simulation time 13663918695 ps
CPU time 129.92 seconds
Started Apr 16 02:10:46 PM PDT 24
Finished Apr 16 02:12:58 PM PDT 24
Peak memory 198324 kb
Host smart-948a6f12-4a62-4e48-b969-a3b9c25aec8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492118646 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2492118646
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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