Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	333053	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4133887	1		T1	16		T2	15		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1099771	1		T1	1		T2	1		T3	1
values[0x0]	1579593	1		T1	9		T2	9		T3	9
values[0x1]	1787576	1		T1	10		T2	10		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149155	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4317785	1		T1	16		T2	16		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15609	1		T7	2		T8	360		T13	164
valid_sources[0x01]	17762	1		T8	325		T13	186		T29	5
valid_sources[0x02]	17961	1		T7	1		T8	341		T13	161
valid_sources[0x03]	17408	1		T7	2		T8	363		T13	201
valid_sources[0x04]	18304	1		T7	2		T8	389		T12	1
valid_sources[0x05]	17312	1		T5	1		T8	356		T13	178
valid_sources[0x06]	18317	1		T7	1		T8	375		T13	173
valid_sources[0x07]	18100	1		T8	417		T13	193		T29	1
valid_sources[0x08]	16062	1		T7	1		T8	363		T13	198
valid_sources[0x09]	18417	1		T8	387		T13	201		T14	170
valid_sources[0x0a]	17976	1		T7	3		T8	363		T13	173
valid_sources[0x0b]	18205	1		T7	3		T8	352		T13	135
valid_sources[0x0c]	17026	1		T7	2		T8	343		T13	155
valid_sources[0x0d]	17938	1		T7	1		T8	386		T12	14
valid_sources[0x0e]	16275	1		T7	4		T8	340		T13	207
valid_sources[0x0f]	16993	1		T8	368		T12	5		T13	198
valid_sources[0x10]	17279	1		T2	1		T3	7		T7	1
valid_sources[0x11]	15797	1		T7	3		T8	361		T32	3
valid_sources[0x12]	17627	1		T5	1		T8	346		T12	5
valid_sources[0x13]	17907	1		T7	2		T8	358		T13	161
valid_sources[0x14]	18608	1		T7	1		T8	333		T12	1
valid_sources[0x15]	15422	1		T7	2		T8	398		T12	3
valid_sources[0x16]	19157	1		T8	357		T13	184		T14	158
valid_sources[0x17]	18009	1		T8	339		T13	182		T30	1
valid_sources[0x18]	18904	1		T4	2		T5	1		T7	2
valid_sources[0x19]	17024	1		T7	3		T8	337		T13	184
valid_sources[0x1a]	16457	1		T8	351		T13	169		T29	1
valid_sources[0x1b]	16137	1		T5	1		T7	2		T8	354
valid_sources[0x1c]	17295	1		T7	1		T8	375		T12	4
valid_sources[0x1d]	16856	1		T7	5		T8	353		T13	173
valid_sources[0x1e]	16361	1		T7	2		T8	337		T13	167
valid_sources[0x1f]	18909	1		T7	2		T8	374		T13	189
valid_sources[0x20]	18705	1		T7	2		T8	344		T13	190
valid_sources[0x21]	18663	1		T2	1		T7	3		T8	344
valid_sources[0x22]	18319	1		T7	2		T8	362		T13	179
valid_sources[0x23]	16310	1		T8	359		T34	1		T13	165
valid_sources[0x24]	17940	1		T7	3		T8	381		T13	176
valid_sources[0x25]	18734	1		T7	2		T8	343		T13	184
valid_sources[0x26]	18046	1		T7	3		T8	353		T12	5
valid_sources[0x27]	18200	1		T8	387		T12	4		T13	173
valid_sources[0x28]	16149	1		T7	2		T8	382		T13	168
valid_sources[0x29]	17708	1		T8	342		T13	177		T14	143
valid_sources[0x2a]	17503	1		T7	1		T8	364		T13	178
valid_sources[0x2b]	18054	1		T7	1		T8	366		T12	4
valid_sources[0x2c]	17256	1		T8	387		T11	2		T32	1
valid_sources[0x2d]	18991	1		T7	2		T8	370		T13	200
valid_sources[0x2e]	17911	1		T2	2		T7	2		T8	342
valid_sources[0x2f]	16419	1		T7	1		T8	358		T13	176
valid_sources[0x30]	18819	1		T7	2		T8	336		T13	197
valid_sources[0x31]	18927	1		T7	2		T8	375		T13	199
valid_sources[0x32]	16532	1		T1	1		T7	3		T8	378
valid_sources[0x33]	16153	1		T7	2		T8	344		T12	6
valid_sources[0x34]	17570	1		T7	4		T8	348		T13	191
valid_sources[0x35]	18185	1		T7	2		T8	361		T34	1
valid_sources[0x36]	14888	1		T5	2		T7	2		T8	343
valid_sources[0x37]	19121	1		T1	2		T7	2		T8	346
valid_sources[0x38]	18346	1		T2	2		T8	336		T13	198
valid_sources[0x39]	17247	1		T2	1		T7	1		T8	349
valid_sources[0x3a]	18101	1		T8	341		T13	156		T14	164
valid_sources[0x3b]	18196	1		T7	1		T8	354		T13	197
valid_sources[0x3c]	15641	1		T7	2		T8	375		T13	162
valid_sources[0x3d]	15645	1		T8	360		T12	3		T34	1
valid_sources[0x3e]	16107	1		T8	346		T10	4		T13	166
valid_sources[0x3f]	19007	1		T7	1		T8	344		T13	168
valid_sources[0x40]	17976	1		T7	2		T8	375		T12	1
valid_sources[0x41]	16858	1		T7	2		T8	373		T13	167
valid_sources[0x42]	16608	1		T7	2		T8	356		T13	162
valid_sources[0x43]	16003	1		T7	1		T8	382		T12	7
valid_sources[0x44]	17635	1		T7	4		T8	379		T12	4
valid_sources[0x45]	15911	1		T5	2		T7	1		T8	355
valid_sources[0x46]	16329	1		T8	384		T13	167		T31	2
valid_sources[0x47]	16605	1		T7	2		T8	332		T13	179
valid_sources[0x48]	17453	1		T7	1		T8	358		T13	197
valid_sources[0x49]	17919	1		T7	1		T8	320		T32	1
valid_sources[0x4a]	17609	1		T8	355		T12	4		T13	180
valid_sources[0x4b]	17866	1		T7	3		T8	355		T12	1
valid_sources[0x4c]	17359	1		T5	1		T7	1		T8	373
valid_sources[0x4d]	16864	1		T8	348		T13	174		T14	189
valid_sources[0x4e]	18086	1		T7	2		T8	380		T13	184
valid_sources[0x4f]	17454	1		T7	4		T8	370		T12	1
valid_sources[0x50]	18031	1		T7	3		T8	376		T13	162
valid_sources[0x51]	19001	1		T7	1		T8	370		T12	1
valid_sources[0x52]	17806	1		T5	1		T8	382		T10	5
valid_sources[0x53]	17145	1		T2	1		T7	1		T8	358
valid_sources[0x54]	18133	1		T7	3		T8	362		T32	1
valid_sources[0x55]	17564	1		T7	7		T8	365		T12	4
valid_sources[0x56]	18200	1		T7	1		T8	365		T13	160
valid_sources[0x57]	17974	1		T7	2		T8	379		T13	183
valid_sources[0x58]	17107	1		T7	1		T8	365		T11	18
valid_sources[0x59]	18963	1		T7	1		T8	384		T12	3
valid_sources[0x5a]	17420	1		T7	1		T8	345		T12	3
valid_sources[0x5b]	16435	1		T8	352		T12	7		T13	181
valid_sources[0x5c]	18201	1		T7	1		T8	378		T12	12
valid_sources[0x5d]	15891	1		T7	3		T8	374		T13	175
valid_sources[0x5e]	15970	1		T8	381		T13	147		T14	185
valid_sources[0x5f]	17041	1		T1	2		T8	385		T13	147
valid_sources[0x60]	16684	1		T8	344		T13	161		T14	169
valid_sources[0x61]	19804	1		T1	1		T4	3		T7	1
valid_sources[0x62]	18029	1		T8	338		T13	186		T29	1
valid_sources[0x63]	18537	1		T8	371		T13	181		T14	142
valid_sources[0x64]	18145	1		T7	2		T8	367		T13	190
valid_sources[0x65]	15631	1		T1	2		T7	1		T8	385
valid_sources[0x66]	16411	1		T7	3		T8	382		T13	180
valid_sources[0x67]	18051	1		T8	355		T13	169		T14	127
valid_sources[0x68]	18495	1		T8	316		T13	206		T30	1
valid_sources[0x69]	19027	1		T2	2		T8	369		T12	2
valid_sources[0x6a]	17354	1		T7	3		T8	366		T9	287
valid_sources[0x6b]	17134	1		T4	1		T7	4		T8	361
valid_sources[0x6c]	17386	1		T7	5		T8	362		T13	200
valid_sources[0x6d]	17931	1		T7	1		T8	385		T13	178
valid_sources[0x6e]	17331	1		T7	2		T8	369		T13	154
valid_sources[0x6f]	17703	1		T7	1		T8	383		T13	162
valid_sources[0x70]	17166	1		T8	350		T13	192		T14	117
valid_sources[0x71]	17196	1		T7	2		T8	379		T13	157
valid_sources[0x72]	17737	1		T8	362		T32	2		T12	11
valid_sources[0x73]	18293	1		T7	3		T8	344		T13	197
valid_sources[0x74]	18064	1		T8	311		T12	2		T13	173
valid_sources[0x75]	16823	1		T7	1		T8	348		T13	163
valid_sources[0x76]	17325	1		T7	1		T8	353		T13	192
valid_sources[0x77]	18082	1		T3	2		T8	345		T12	1
valid_sources[0x78]	17784	1		T8	310		T13	184		T50	1
valid_sources[0x79]	16881	1		T7	1		T8	365		T13	174
valid_sources[0x7a]	17574	1		T7	1		T8	354		T10	2
valid_sources[0x7b]	16969	1		T7	2		T8	343		T12	2
valid_sources[0x7c]	20112	1		T8	397		T34	1		T13	192
valid_sources[0x7d]	18369	1		T7	3		T8	347		T13	181
valid_sources[0x7e]	17488	1		T4	1		T7	1		T8	339
valid_sources[0x7f]	17303	1		T1	6		T8	327		T13	191
valid_sources[0x80]	17349	1		T7	1		T8	344		T13	178

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1031753

1

T5

1

T6

1

T7

20

values[0x0]

all_enables

biggest_size

1551382

1

T1

7

T2

8

T3

6

values[0x1]

all_enables

biggest_size

1550752

1

T1

9

T2

7

T3

8