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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 425
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T31 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3751411182 Apr 21 01:50:29 PM PDT 24 Apr 21 01:50:31 PM PDT 24 4405369804 ps
T32 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4210877256 Apr 21 01:51:34 PM PDT 24 Apr 21 01:51:36 PM PDT 24 1255509268 ps
T33 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.459169634 Apr 21 01:51:28 PM PDT 24 Apr 21 01:51:42 PM PDT 24 8655311607 ps
T39 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2228549430 Apr 21 01:51:25 PM PDT 24 Apr 21 01:51:26 PM PDT 24 324071325 ps
T37 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.971174649 Apr 21 01:50:51 PM PDT 24 Apr 21 01:50:52 PM PDT 24 335166185 ps
T72 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1110965402 Apr 21 01:51:02 PM PDT 24 Apr 21 01:51:07 PM PDT 24 1789332323 ps
T95 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4266324786 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:33 PM PDT 24 539027651 ps
T38 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1957763272 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:41 PM PDT 24 4506962658 ps
T285 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.76465933 Apr 21 01:51:42 PM PDT 24 Apr 21 01:51:43 PM PDT 24 277432092 ps
T49 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1644410899 Apr 21 01:49:49 PM PDT 24 Apr 21 01:49:51 PM PDT 24 443684490 ps
T73 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3059116593 Apr 21 01:51:07 PM PDT 24 Apr 21 01:51:09 PM PDT 24 1219790875 ps
T286 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2735646483 Apr 21 01:51:52 PM PDT 24 Apr 21 01:51:53 PM PDT 24 367677858 ps
T287 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1119512691 Apr 21 01:50:56 PM PDT 24 Apr 21 01:50:57 PM PDT 24 294561537 ps
T288 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2842882623 Apr 21 01:51:58 PM PDT 24 Apr 21 01:51:59 PM PDT 24 306414831 ps
T289 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2088170025 Apr 21 01:49:45 PM PDT 24 Apr 21 01:49:46 PM PDT 24 495473282 ps
T290 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2115764104 Apr 21 01:49:36 PM PDT 24 Apr 21 01:49:39 PM PDT 24 578458860 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2525986390 Apr 21 01:50:15 PM PDT 24 Apr 21 01:50:16 PM PDT 24 378892138 ps
T292 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2668043875 Apr 21 01:51:22 PM PDT 24 Apr 21 01:51:24 PM PDT 24 473478175 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.880738040 Apr 21 01:50:35 PM PDT 24 Apr 21 01:50:38 PM PDT 24 362432548 ps
T294 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1837672025 Apr 21 01:49:43 PM PDT 24 Apr 21 01:49:45 PM PDT 24 516124230 ps
T74 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3211534081 Apr 21 01:51:13 PM PDT 24 Apr 21 01:51:14 PM PDT 24 455614422 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.867731442 Apr 21 01:50:27 PM PDT 24 Apr 21 01:50:28 PM PDT 24 691708365 ps
T296 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.886744725 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:41 PM PDT 24 491432510 ps
T297 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2603664070 Apr 21 01:51:55 PM PDT 24 Apr 21 01:51:56 PM PDT 24 485015699 ps
T93 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1163873409 Apr 21 01:50:51 PM PDT 24 Apr 21 01:50:55 PM PDT 24 4151073431 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1047150699 Apr 21 01:49:35 PM PDT 24 Apr 21 01:49:36 PM PDT 24 512248238 ps
T75 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3290084057 Apr 21 01:51:26 PM PDT 24 Apr 21 01:51:28 PM PDT 24 1994864022 ps
T299 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.678806637 Apr 21 01:51:12 PM PDT 24 Apr 21 01:51:13 PM PDT 24 447428295 ps
T50 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2760758185 Apr 21 01:51:29 PM PDT 24 Apr 21 01:51:30 PM PDT 24 440606440 ps
T76 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3827785804 Apr 21 01:51:26 PM PDT 24 Apr 21 01:51:28 PM PDT 24 979389341 ps
T51 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.185738730 Apr 21 01:50:43 PM PDT 24 Apr 21 01:50:44 PM PDT 24 1152663167 ps
T300 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3893153391 Apr 21 01:50:28 PM PDT 24 Apr 21 01:50:39 PM PDT 24 7173517304 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.253655431 Apr 21 01:49:56 PM PDT 24 Apr 21 01:49:57 PM PDT 24 292295913 ps
T302 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1652424471 Apr 21 01:51:49 PM PDT 24 Apr 21 01:51:51 PM PDT 24 312702968 ps
T303 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3804979117 Apr 21 01:51:02 PM PDT 24 Apr 21 01:51:05 PM PDT 24 454592339 ps
T304 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4218484865 Apr 21 01:51:53 PM PDT 24 Apr 21 01:51:54 PM PDT 24 452411511 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.783435407 Apr 21 01:50:19 PM PDT 24 Apr 21 01:50:30 PM PDT 24 7148949645 ps
T306 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3147041929 Apr 21 01:51:22 PM PDT 24 Apr 21 01:51:25 PM PDT 24 419235567 ps
T52 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.201948963 Apr 21 01:51:02 PM PDT 24 Apr 21 01:51:03 PM PDT 24 493773989 ps
T307 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1056817986 Apr 21 01:49:39 PM PDT 24 Apr 21 01:49:40 PM PDT 24 365154000 ps
T308 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3194375279 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:33 PM PDT 24 673075995 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3554877692 Apr 21 01:50:53 PM PDT 24 Apr 21 01:50:54 PM PDT 24 397516685 ps
T310 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1669523244 Apr 21 01:50:50 PM PDT 24 Apr 21 01:50:52 PM PDT 24 564061422 ps
T77 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1996397254 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:39 PM PDT 24 521468392 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4291695116 Apr 21 01:50:25 PM PDT 24 Apr 21 01:50:26 PM PDT 24 322290357 ps
T53 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2019430948 Apr 21 01:51:20 PM PDT 24 Apr 21 01:51:21 PM PDT 24 530990359 ps
T312 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3225390115 Apr 21 01:51:34 PM PDT 24 Apr 21 01:51:35 PM PDT 24 450522434 ps
T54 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2684743589 Apr 21 01:50:10 PM PDT 24 Apr 21 01:50:11 PM PDT 24 466141766 ps
T313 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1966556932 Apr 21 01:51:27 PM PDT 24 Apr 21 01:51:28 PM PDT 24 519998101 ps
T89 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.298287155 Apr 21 01:49:34 PM PDT 24 Apr 21 01:49:41 PM PDT 24 8290875082 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.113316406 Apr 21 01:50:37 PM PDT 24 Apr 21 01:50:38 PM PDT 24 448609382 ps
T315 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1176899424 Apr 21 01:52:06 PM PDT 24 Apr 21 01:52:07 PM PDT 24 505895478 ps
T78 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2926397770 Apr 21 01:51:32 PM PDT 24 Apr 21 01:51:33 PM PDT 24 462735824 ps
T316 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.32919891 Apr 21 01:49:45 PM PDT 24 Apr 21 01:49:48 PM PDT 24 1203836638 ps
T90 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1372965069 Apr 21 01:51:23 PM PDT 24 Apr 21 01:51:35 PM PDT 24 8551365970 ps
T317 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1324685148 Apr 21 01:51:16 PM PDT 24 Apr 21 01:51:18 PM PDT 24 9069886870 ps
T91 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1135192895 Apr 21 01:50:50 PM PDT 24 Apr 21 01:50:58 PM PDT 24 8427189801 ps
T318 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2492249776 Apr 21 01:51:01 PM PDT 24 Apr 21 01:51:02 PM PDT 24 860115462 ps
T319 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.792793560 Apr 21 01:51:54 PM PDT 24 Apr 21 01:51:55 PM PDT 24 349635925 ps
T320 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.223356491 Apr 21 01:51:22 PM PDT 24 Apr 21 01:51:23 PM PDT 24 378301617 ps
T321 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.821372922 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:40 PM PDT 24 626374328 ps
T322 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2759533402 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:32 PM PDT 24 473490746 ps
T323 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.985043493 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:32 PM PDT 24 406971799 ps
T324 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3265184918 Apr 21 01:50:54 PM PDT 24 Apr 21 01:50:55 PM PDT 24 392211661 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3558117198 Apr 21 01:50:48 PM PDT 24 Apr 21 01:50:50 PM PDT 24 962476572 ps
T326 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1473869818 Apr 21 01:49:49 PM PDT 24 Apr 21 01:49:52 PM PDT 24 7132508983 ps
T327 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3241747888 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:35 PM PDT 24 8524927061 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1624617076 Apr 21 01:50:10 PM PDT 24 Apr 21 01:50:20 PM PDT 24 6940337124 ps
T94 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1841750604 Apr 21 01:51:39 PM PDT 24 Apr 21 01:51:47 PM PDT 24 8356680098 ps
T329 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.478673552 Apr 21 01:50:58 PM PDT 24 Apr 21 01:50:59 PM PDT 24 462497194 ps
T330 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1605060072 Apr 21 01:49:53 PM PDT 24 Apr 21 01:49:58 PM PDT 24 8280648170 ps
T331 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2007841025 Apr 21 01:50:57 PM PDT 24 Apr 21 01:50:59 PM PDT 24 507996651 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.784478857 Apr 21 01:50:11 PM PDT 24 Apr 21 01:50:12 PM PDT 24 618295878 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1809683473 Apr 21 01:51:23 PM PDT 24 Apr 21 01:51:25 PM PDT 24 443911088 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.826499291 Apr 21 01:51:13 PM PDT 24 Apr 21 01:51:15 PM PDT 24 4434332238 ps
T55 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.565970561 Apr 21 01:50:26 PM PDT 24 Apr 21 01:50:27 PM PDT 24 383724836 ps
T335 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1183049306 Apr 21 01:50:53 PM PDT 24 Apr 21 01:50:56 PM PDT 24 1295107316 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.705556995 Apr 21 01:50:26 PM PDT 24 Apr 21 01:50:27 PM PDT 24 526541430 ps
T337 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2277421500 Apr 21 01:50:39 PM PDT 24 Apr 21 01:50:40 PM PDT 24 487434440 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2557032413 Apr 21 01:49:53 PM PDT 24 Apr 21 01:49:55 PM PDT 24 354226182 ps
T339 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.321558019 Apr 21 01:51:29 PM PDT 24 Apr 21 01:51:32 PM PDT 24 569020151 ps
T70 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1712299605 Apr 21 01:50:18 PM PDT 24 Apr 21 01:50:19 PM PDT 24 523615624 ps
T92 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2514405405 Apr 21 01:50:38 PM PDT 24 Apr 21 01:50:43 PM PDT 24 8124401886 ps
T340 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1053931108 Apr 21 01:50:56 PM PDT 24 Apr 21 01:50:57 PM PDT 24 628195490 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1815678550 Apr 21 01:51:01 PM PDT 24 Apr 21 01:51:05 PM PDT 24 8638738921 ps
T342 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.393189774 Apr 21 01:51:23 PM PDT 24 Apr 21 01:51:24 PM PDT 24 465959986 ps
T71 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4069456386 Apr 21 01:51:40 PM PDT 24 Apr 21 01:51:41 PM PDT 24 558829373 ps
T343 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1658074782 Apr 21 01:51:47 PM PDT 24 Apr 21 01:51:48 PM PDT 24 488210591 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.330668806 Apr 21 01:49:59 PM PDT 24 Apr 21 01:49:59 PM PDT 24 434897855 ps
T345 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4069551426 Apr 21 01:51:05 PM PDT 24 Apr 21 01:51:09 PM PDT 24 8086472394 ps
T346 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1764744726 Apr 21 01:51:40 PM PDT 24 Apr 21 01:51:41 PM PDT 24 492925116 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2290803282 Apr 21 01:50:44 PM PDT 24 Apr 21 01:50:45 PM PDT 24 617117366 ps
T348 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3855059238 Apr 21 01:51:52 PM PDT 24 Apr 21 01:51:53 PM PDT 24 367783251 ps
T349 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2585255095 Apr 21 01:51:40 PM PDT 24 Apr 21 01:51:41 PM PDT 24 579393320 ps
T350 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.39216108 Apr 21 01:51:32 PM PDT 24 Apr 21 01:51:37 PM PDT 24 2793982141 ps
T56 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1207458585 Apr 21 01:50:33 PM PDT 24 Apr 21 01:50:34 PM PDT 24 744521711 ps
T351 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1753696196 Apr 21 01:50:50 PM PDT 24 Apr 21 01:50:51 PM PDT 24 368310479 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4039439363 Apr 21 01:51:25 PM PDT 24 Apr 21 01:51:26 PM PDT 24 449457760 ps
T353 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3490940680 Apr 21 01:50:14 PM PDT 24 Apr 21 01:50:19 PM PDT 24 8564978042 ps
T354 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2736143671 Apr 21 01:51:43 PM PDT 24 Apr 21 01:51:44 PM PDT 24 535634106 ps
T355 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1280726980 Apr 21 01:50:40 PM PDT 24 Apr 21 01:50:41 PM PDT 24 353852192 ps
T356 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3573103000 Apr 21 01:51:49 PM PDT 24 Apr 21 01:51:50 PM PDT 24 442470555 ps
T357 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.191645660 Apr 21 01:50:52 PM PDT 24 Apr 21 01:50:57 PM PDT 24 1840605732 ps
T358 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.854307677 Apr 21 01:51:44 PM PDT 24 Apr 21 01:51:45 PM PDT 24 508851352 ps
T359 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3482270051 Apr 21 01:51:28 PM PDT 24 Apr 21 01:51:29 PM PDT 24 424870948 ps
T360 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2130337505 Apr 21 01:51:07 PM PDT 24 Apr 21 01:51:08 PM PDT 24 393419337 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1726681166 Apr 21 01:51:39 PM PDT 24 Apr 21 01:51:41 PM PDT 24 576351155 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4229565532 Apr 21 01:50:34 PM PDT 24 Apr 21 01:50:35 PM PDT 24 1276517677 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1636016141 Apr 21 01:51:30 PM PDT 24 Apr 21 01:51:33 PM PDT 24 515501198 ps
T364 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4061908036 Apr 21 01:51:02 PM PDT 24 Apr 21 01:51:05 PM PDT 24 809624659 ps
T365 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3167040173 Apr 21 01:50:56 PM PDT 24 Apr 21 01:51:04 PM PDT 24 8482241144 ps
T366 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1613196461 Apr 21 01:51:39 PM PDT 24 Apr 21 01:51:41 PM PDT 24 546352787 ps
T367 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3698061577 Apr 21 01:51:55 PM PDT 24 Apr 21 01:51:56 PM PDT 24 451578898 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1468991992 Apr 21 01:50:47 PM PDT 24 Apr 21 01:50:49 PM PDT 24 417959899 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1853839925 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:40 PM PDT 24 2233622044 ps
T370 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2396455918 Apr 21 01:51:51 PM PDT 24 Apr 21 01:51:52 PM PDT 24 437885467 ps
T371 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.372840058 Apr 21 01:51:35 PM PDT 24 Apr 21 01:51:37 PM PDT 24 947902360 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3246662631 Apr 21 01:50:09 PM PDT 24 Apr 21 01:50:10 PM PDT 24 1130348938 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.49062459 Apr 21 01:50:26 PM PDT 24 Apr 21 01:50:27 PM PDT 24 304953518 ps
T374 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.205642363 Apr 21 01:51:28 PM PDT 24 Apr 21 01:51:29 PM PDT 24 332383247 ps
T375 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2711804666 Apr 21 01:51:47 PM PDT 24 Apr 21 01:51:48 PM PDT 24 470486094 ps
T376 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1885619895 Apr 21 01:51:22 PM PDT 24 Apr 21 01:51:23 PM PDT 24 515173898 ps
T377 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1933556955 Apr 21 01:50:43 PM PDT 24 Apr 21 01:51:02 PM PDT 24 13864969310 ps
T378 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3773536883 Apr 21 01:51:57 PM PDT 24 Apr 21 01:51:59 PM PDT 24 454384297 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1665629616 Apr 21 01:50:44 PM PDT 24 Apr 21 01:50:45 PM PDT 24 372408508 ps
T379 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1018236396 Apr 21 01:50:12 PM PDT 24 Apr 21 01:50:19 PM PDT 24 2883364982 ps
T380 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2590529091 Apr 21 01:51:54 PM PDT 24 Apr 21 01:51:55 PM PDT 24 371296893 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3918042917 Apr 21 01:50:50 PM PDT 24 Apr 21 01:50:51 PM PDT 24 541885873 ps
T382 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1104566398 Apr 21 01:51:52 PM PDT 24 Apr 21 01:51:53 PM PDT 24 366335266 ps
T383 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1511724661 Apr 21 01:51:38 PM PDT 24 Apr 21 01:51:39 PM PDT 24 338014599 ps
T384 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1105702122 Apr 21 01:51:14 PM PDT 24 Apr 21 01:51:16 PM PDT 24 397630084 ps
T385 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3309157183 Apr 21 01:51:33 PM PDT 24 Apr 21 01:51:36 PM PDT 24 2368582178 ps
T386 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1184085147 Apr 21 01:51:56 PM PDT 24 Apr 21 01:51:57 PM PDT 24 349389286 ps
T387 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1491238256 Apr 21 01:51:37 PM PDT 24 Apr 21 01:51:38 PM PDT 24 461841187 ps
T388 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1594155490 Apr 21 01:51:18 PM PDT 24 Apr 21 01:51:20 PM PDT 24 1448852972 ps
T389 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1790038748 Apr 21 01:51:46 PM PDT 24 Apr 21 01:51:47 PM PDT 24 392328760 ps
T390 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3688096263 Apr 21 01:51:21 PM PDT 24 Apr 21 01:51:24 PM PDT 24 4554829702 ps
T391 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2495434175 Apr 21 01:51:46 PM PDT 24 Apr 21 01:51:47 PM PDT 24 511880448 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2029211991 Apr 21 01:49:52 PM PDT 24 Apr 21 01:49:53 PM PDT 24 529008081 ps
T393 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1826426829 Apr 21 01:51:02 PM PDT 24 Apr 21 01:51:03 PM PDT 24 407998674 ps
T394 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1447332084 Apr 21 01:51:54 PM PDT 24 Apr 21 01:51:55 PM PDT 24 501705078 ps
T395 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1555653679 Apr 21 01:51:34 PM PDT 24 Apr 21 01:51:38 PM PDT 24 4513669847 ps
T396 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4172869313 Apr 21 01:51:57 PM PDT 24 Apr 21 01:51:58 PM PDT 24 353105409 ps
T397 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3882006751 Apr 21 01:51:06 PM PDT 24 Apr 21 01:51:06 PM PDT 24 408839654 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.284143251 Apr 21 01:51:20 PM PDT 24 Apr 21 01:51:21 PM PDT 24 404366396 ps
T398 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2234235895 Apr 21 01:51:07 PM PDT 24 Apr 21 01:51:08 PM PDT 24 362563951 ps
T399 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2499883035 Apr 21 01:51:21 PM PDT 24 Apr 21 01:51:23 PM PDT 24 802053701 ps
T400 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3493097401 Apr 21 01:51:59 PM PDT 24 Apr 21 01:52:00 PM PDT 24 454199168 ps
T401 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4054798350 Apr 21 01:51:29 PM PDT 24 Apr 21 01:51:30 PM PDT 24 314035347 ps
T402 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.964953234 Apr 21 01:51:29 PM PDT 24 Apr 21 01:51:34 PM PDT 24 8065864825 ps
T403 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1377750515 Apr 21 01:50:18 PM PDT 24 Apr 21 01:50:19 PM PDT 24 359581646 ps
T404 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3797725152 Apr 21 01:50:24 PM PDT 24 Apr 21 01:50:26 PM PDT 24 401431037 ps
T405 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3287549015 Apr 21 01:51:51 PM PDT 24 Apr 21 01:51:52 PM PDT 24 322123486 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2942236331 Apr 21 01:51:12 PM PDT 24 Apr 21 01:51:14 PM PDT 24 2401482377 ps
T59 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1670872974 Apr 21 01:50:09 PM PDT 24 Apr 21 01:50:11 PM PDT 24 516200665 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2162050718 Apr 21 01:51:10 PM PDT 24 Apr 21 01:51:13 PM PDT 24 517933996 ps
T408 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2295716786 Apr 21 01:51:31 PM PDT 24 Apr 21 01:51:34 PM PDT 24 1853421556 ps
T409 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3020884421 Apr 21 01:51:43 PM PDT 24 Apr 21 01:51:44 PM PDT 24 563932057 ps
T410 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3740789157 Apr 21 01:51:42 PM PDT 24 Apr 21 01:51:44 PM PDT 24 1196233396 ps
T60 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.30203642 Apr 21 01:50:57 PM PDT 24 Apr 21 01:50:59 PM PDT 24 463653104 ps
T411 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.126945915 Apr 21 01:50:18 PM PDT 24 Apr 21 01:50:19 PM PDT 24 305296171 ps
T412 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1893997133 Apr 21 01:50:44 PM PDT 24 Apr 21 01:50:45 PM PDT 24 438759428 ps
T413 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4033315758 Apr 21 01:50:56 PM PDT 24 Apr 21 01:50:59 PM PDT 24 1205144654 ps
T414 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1731967652 Apr 21 01:51:15 PM PDT 24 Apr 21 01:51:17 PM PDT 24 435592544 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4256098747 Apr 21 01:50:49 PM PDT 24 Apr 21 01:50:53 PM PDT 24 2748415607 ps
T416 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4187909340 Apr 21 01:51:56 PM PDT 24 Apr 21 01:51:57 PM PDT 24 500464752 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.730475480 Apr 21 01:50:17 PM PDT 24 Apr 21 01:50:18 PM PDT 24 1043842550 ps
T418 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1356070627 Apr 21 01:50:21 PM PDT 24 Apr 21 01:50:22 PM PDT 24 637705928 ps
T419 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2226678815 Apr 21 01:50:24 PM PDT 24 Apr 21 01:50:25 PM PDT 24 418685579 ps
T420 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3061611346 Apr 21 01:49:51 PM PDT 24 Apr 21 01:49:54 PM PDT 24 2079498400 ps
T421 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3591129477 Apr 21 01:50:15 PM PDT 24 Apr 21 01:50:17 PM PDT 24 631383971 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3656355053 Apr 21 01:50:25 PM PDT 24 Apr 21 01:50:27 PM PDT 24 2165234836 ps
T423 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1309992086 Apr 21 01:51:44 PM PDT 24 Apr 21 01:51:44 PM PDT 24 463104622 ps
T424 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1829147552 Apr 21 01:49:55 PM PDT 24 Apr 21 01:49:56 PM PDT 24 484841527 ps
T425 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1366567556 Apr 21 01:51:54 PM PDT 24 Apr 21 01:51:55 PM PDT 24 427463464 ps

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3442915392
Short name T10
Test name
Test status
Simulation time 287349816129 ps
CPU time 570.03 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:59:21 PM PDT 24
Peak memory 198916 kb
Host smart-3a22cd4a-0842-4799-93c2-cc82ae1996a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442915392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3442915392
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.368480721
Short name T34
Test name
Test status
Simulation time 96270040499 ps
CPU time 67.64 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:50:38 PM PDT 24
Peak memory 183380 kb
Host smart-62aa484f-f67f-4eab-8faa-825aefb6b481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368480721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.368480721
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.459169634
Short name T33
Test name
Test status
Simulation time 8655311607 ps
CPU time 13.54 seconds
Started Apr 21 01:51:28 PM PDT 24
Finished Apr 21 01:51:42 PM PDT 24
Peak memory 198116 kb
Host smart-277c990a-a618-44b1-9dd9-9a6fbe5548e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459169634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.459169634
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3118226047
Short name T11
Test name
Test status
Simulation time 76271010018 ps
CPU time 335.88 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:55:31 PM PDT 24
Peak memory 198324 kb
Host smart-5f0cc0df-7721-4af7-a8cd-be2573209171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118226047 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3118226047
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.29365837
Short name T41
Test name
Test status
Simulation time 229896119087 ps
CPU time 438.51 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 198268 kb
Host smart-10517f04-56fa-4082-9149-19a9764e7acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365837 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.29365837
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1556489111
Short name T17
Test name
Test status
Simulation time 8545476781 ps
CPU time 1.5 seconds
Started Apr 21 12:49:15 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 215216 kb
Host smart-23b831d8-ff9e-4515-bbf6-a8e6f348758c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556489111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1556489111
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2228549430
Short name T39
Test name
Test status
Simulation time 324071325 ps
CPU time 0.7 seconds
Started Apr 21 01:51:25 PM PDT 24
Finished Apr 21 01:51:26 PM PDT 24
Peak memory 193268 kb
Host smart-35ccb165-44f9-47a0-a4b5-b1b765589ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228549430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2228549430
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1372965069
Short name T90
Test name
Test status
Simulation time 8551365970 ps
CPU time 12.08 seconds
Started Apr 21 01:51:23 PM PDT 24
Finished Apr 21 01:51:35 PM PDT 24
Peak memory 198148 kb
Host smart-6bad2cd3-a637-4ab2-8f01-012b901980a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372965069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1372965069
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3572176691
Short name T23
Test name
Test status
Simulation time 247498377544 ps
CPU time 102.06 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:51:40 PM PDT 24
Peak memory 194840 kb
Host smart-6d2e0951-699a-44de-94fe-38e72dc48e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572176691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3572176691
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1644410899
Short name T49
Test name
Test status
Simulation time 443684490 ps
CPU time 1.41 seconds
Started Apr 21 01:49:49 PM PDT 24
Finished Apr 21 01:49:51 PM PDT 24
Peak memory 183968 kb
Host smart-d710c017-8ac3-4261-860b-3b2d156a6a3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644410899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1644410899
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1473869818
Short name T326
Test name
Test status
Simulation time 7132508983 ps
CPU time 2.83 seconds
Started Apr 21 01:49:49 PM PDT 24
Finished Apr 21 01:49:52 PM PDT 24
Peak memory 192468 kb
Host smart-06444047-24b3-4dd3-a1df-17cb3a3ae7ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473869818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1473869818
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.32919891
Short name T316
Test name
Test status
Simulation time 1203836638 ps
CPU time 2.41 seconds
Started Apr 21 01:49:45 PM PDT 24
Finished Apr 21 01:49:48 PM PDT 24
Peak memory 183960 kb
Host smart-aa20cda3-02f2-4056-9d7d-56c7b45ddf37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32919891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_
reset.32919891
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2029211991
Short name T392
Test name
Test status
Simulation time 529008081 ps
CPU time 1.07 seconds
Started Apr 21 01:49:52 PM PDT 24
Finished Apr 21 01:49:53 PM PDT 24
Peak memory 198504 kb
Host smart-6c65f800-7ab3-47fc-b9f3-5af4f33d2822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029211991 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2029211991
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2088170025
Short name T289
Test name
Test status
Simulation time 495473282 ps
CPU time 0.92 seconds
Started Apr 21 01:49:45 PM PDT 24
Finished Apr 21 01:49:46 PM PDT 24
Peak memory 193248 kb
Host smart-361f1661-5616-45ce-a555-a5746f294c81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088170025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2088170025
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1047150699
Short name T298
Test name
Test status
Simulation time 512248238 ps
CPU time 1.28 seconds
Started Apr 21 01:49:35 PM PDT 24
Finished Apr 21 01:49:36 PM PDT 24
Peak memory 183928 kb
Host smart-a0e16333-473a-4481-8f51-41338d9a9e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047150699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1047150699
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1837672025
Short name T294
Test name
Test status
Simulation time 516124230 ps
CPU time 1.29 seconds
Started Apr 21 01:49:43 PM PDT 24
Finished Apr 21 01:49:45 PM PDT 24
Peak memory 183804 kb
Host smart-6242625b-3b41-44e7-a2c4-2aad1301b119
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837672025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1837672025
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1056817986
Short name T307
Test name
Test status
Simulation time 365154000 ps
CPU time 0.75 seconds
Started Apr 21 01:49:39 PM PDT 24
Finished Apr 21 01:49:40 PM PDT 24
Peak memory 183852 kb
Host smart-678178d2-9646-43c5-99c2-7e846de7b9bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056817986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1056817986
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3061611346
Short name T420
Test name
Test status
Simulation time 2079498400 ps
CPU time 3.33 seconds
Started Apr 21 01:49:51 PM PDT 24
Finished Apr 21 01:49:54 PM PDT 24
Peak memory 184136 kb
Host smart-46680bd9-f5ef-48ed-98c2-e2d88895dfa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061611346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3061611346
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2115764104
Short name T290
Test name
Test status
Simulation time 578458860 ps
CPU time 2.31 seconds
Started Apr 21 01:49:36 PM PDT 24
Finished Apr 21 01:49:39 PM PDT 24
Peak memory 198840 kb
Host smart-89c2f85a-8330-40e5-a068-f60d82bcb528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115764104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2115764104
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.298287155
Short name T89
Test name
Test status
Simulation time 8290875082 ps
CPU time 7.15 seconds
Started Apr 21 01:49:34 PM PDT 24
Finished Apr 21 01:49:41 PM PDT 24
Peak memory 198264 kb
Host smart-d9cc1687-5cd2-4539-9160-488db877fcd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298287155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.298287155
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1670872974
Short name T59
Test name
Test status
Simulation time 516200665 ps
CPU time 1.52 seconds
Started Apr 21 01:50:09 PM PDT 24
Finished Apr 21 01:50:11 PM PDT 24
Peak memory 193280 kb
Host smart-cc0c1715-785d-4fc7-8ddb-1b48ec71d0fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670872974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1670872974
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1624617076
Short name T328
Test name
Test status
Simulation time 6940337124 ps
CPU time 10.37 seconds
Started Apr 21 01:50:10 PM PDT 24
Finished Apr 21 01:50:20 PM PDT 24
Peak memory 192488 kb
Host smart-eccb772e-3180-4b0e-9aa1-69bd2c5cdb0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624617076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1624617076
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3246662631
Short name T372
Test name
Test status
Simulation time 1130348938 ps
CPU time 1 seconds
Started Apr 21 01:50:09 PM PDT 24
Finished Apr 21 01:50:10 PM PDT 24
Peak memory 183984 kb
Host smart-be20f018-365e-4d2c-ad19-f05b80dea2b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246662631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3246662631
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.784478857
Short name T332
Test name
Test status
Simulation time 618295878 ps
CPU time 0.92 seconds
Started Apr 21 01:50:11 PM PDT 24
Finished Apr 21 01:50:12 PM PDT 24
Peak memory 195896 kb
Host smart-0f78877e-c087-4f07-ad8d-64efb9eb610c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784478857 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.784478857
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2684743589
Short name T54
Test name
Test status
Simulation time 466141766 ps
CPU time 0.87 seconds
Started Apr 21 01:50:10 PM PDT 24
Finished Apr 21 01:50:11 PM PDT 24
Peak memory 193332 kb
Host smart-b85ad82e-b0d8-4506-80b0-abf9cbe70e15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684743589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2684743589
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.1829147552
Short name T424
Test name
Test status
Simulation time 484841527 ps
CPU time 0.81 seconds
Started Apr 21 01:49:55 PM PDT 24
Finished Apr 21 01:49:56 PM PDT 24
Peak memory 183948 kb
Host smart-357fe9cc-3c87-4ab5-a5d6-0a562e2d3919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829147552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.1829147552
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.330668806
Short name T344
Test name
Test status
Simulation time 434897855 ps
CPU time 0.66 seconds
Started Apr 21 01:49:59 PM PDT 24
Finished Apr 21 01:49:59 PM PDT 24
Peak memory 183840 kb
Host smart-77bbaaf9-6915-4f37-93c5-cdb38756630f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330668806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.330668806
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.253655431
Short name T301
Test name
Test status
Simulation time 292295913 ps
CPU time 0.72 seconds
Started Apr 21 01:49:56 PM PDT 24
Finished Apr 21 01:49:57 PM PDT 24
Peak memory 183888 kb
Host smart-58551ce7-342d-47b9-81a9-f2979519a5be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253655431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.253655431
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1018236396
Short name T379
Test name
Test status
Simulation time 2883364982 ps
CPU time 7.42 seconds
Started Apr 21 01:50:12 PM PDT 24
Finished Apr 21 01:50:19 PM PDT 24
Peak memory 194804 kb
Host smart-b522d541-722a-44aa-bb24-9307d6377efc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018236396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1018236396
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2557032413
Short name T338
Test name
Test status
Simulation time 354226182 ps
CPU time 1.83 seconds
Started Apr 21 01:49:53 PM PDT 24
Finished Apr 21 01:49:55 PM PDT 24
Peak memory 198840 kb
Host smart-cde06263-3d86-43af-8c90-8dbbec8b90b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557032413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2557032413
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1605060072
Short name T330
Test name
Test status
Simulation time 8280648170 ps
CPU time 4.14 seconds
Started Apr 21 01:49:53 PM PDT 24
Finished Apr 21 01:49:58 PM PDT 24
Peak memory 198280 kb
Host smart-f21ce607-fc8f-464f-8eaa-3a2559b51b90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605060072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1605060072
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1105702122
Short name T384
Test name
Test status
Simulation time 397630084 ps
CPU time 1.06 seconds
Started Apr 21 01:51:14 PM PDT 24
Finished Apr 21 01:51:16 PM PDT 24
Peak memory 196708 kb
Host smart-6e6b2928-4216-4007-9a86-67e29785cd1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105702122 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1105702122
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3211534081
Short name T74
Test name
Test status
Simulation time 455614422 ps
CPU time 1.21 seconds
Started Apr 21 01:51:13 PM PDT 24
Finished Apr 21 01:51:14 PM PDT 24
Peak memory 193400 kb
Host smart-ef41c37e-e6bd-477d-945c-559306dde049
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211534081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3211534081
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.678806637
Short name T299
Test name
Test status
Simulation time 447428295 ps
CPU time 0.89 seconds
Started Apr 21 01:51:12 PM PDT 24
Finished Apr 21 01:51:13 PM PDT 24
Peak memory 183968 kb
Host smart-4fe26664-abf0-4511-a88d-b24040a6f3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678806637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.678806637
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2942236331
Short name T406
Test name
Test status
Simulation time 2401482377 ps
CPU time 0.89 seconds
Started Apr 21 01:51:12 PM PDT 24
Finished Apr 21 01:51:14 PM PDT 24
Peak memory 194796 kb
Host smart-d6f35487-9eae-41c4-a4c0-bd3cb9a48210
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942236331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2942236331
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2162050718
Short name T407
Test name
Test status
Simulation time 517933996 ps
CPU time 2.51 seconds
Started Apr 21 01:51:10 PM PDT 24
Finished Apr 21 01:51:13 PM PDT 24
Peak memory 198812 kb
Host smart-d3331cf0-cf0a-43fc-8a4d-172854c0e6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162050718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2162050718
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.826499291
Short name T334
Test name
Test status
Simulation time 4434332238 ps
CPU time 2.41 seconds
Started Apr 21 01:51:13 PM PDT 24
Finished Apr 21 01:51:15 PM PDT 24
Peak memory 197568 kb
Host smart-8bba1410-3107-442a-8295-fd4a9066f57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826499291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.826499291
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2668043875
Short name T292
Test name
Test status
Simulation time 473478175 ps
CPU time 1.47 seconds
Started Apr 21 01:51:22 PM PDT 24
Finished Apr 21 01:51:24 PM PDT 24
Peak memory 195996 kb
Host smart-cc192ea6-77f9-4bae-b464-2cab7ea748c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668043875 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2668043875
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2019430948
Short name T53
Test name
Test status
Simulation time 530990359 ps
CPU time 0.76 seconds
Started Apr 21 01:51:20 PM PDT 24
Finished Apr 21 01:51:21 PM PDT 24
Peak memory 184200 kb
Host smart-15daa607-6ca6-4456-ac9a-cb05a235ec98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019430948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2019430948
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1731967652
Short name T414
Test name
Test status
Simulation time 435592544 ps
CPU time 0.69 seconds
Started Apr 21 01:51:15 PM PDT 24
Finished Apr 21 01:51:17 PM PDT 24
Peak memory 183912 kb
Host smart-353f5b55-4d0e-4e44-8844-272d94153334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731967652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1731967652
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1594155490
Short name T388
Test name
Test status
Simulation time 1448852972 ps
CPU time 1.63 seconds
Started Apr 21 01:51:18 PM PDT 24
Finished Apr 21 01:51:20 PM PDT 24
Peak memory 193604 kb
Host smart-bebd7027-1f7f-4474-b678-c6d930e274d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594155490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1594155490
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1636016141
Short name T363
Test name
Test status
Simulation time 515501198 ps
CPU time 2.55 seconds
Started Apr 21 01:51:30 PM PDT 24
Finished Apr 21 01:51:33 PM PDT 24
Peak memory 198856 kb
Host smart-12c5c38c-b931-49b7-99c4-a546ad1762cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636016141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1636016141
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1324685148
Short name T317
Test name
Test status
Simulation time 9069886870 ps
CPU time 2.01 seconds
Started Apr 21 01:51:16 PM PDT 24
Finished Apr 21 01:51:18 PM PDT 24
Peak memory 198296 kb
Host smart-cda4e20d-097f-49b7-9930-80167d1be275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324685148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1324685148
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1809683473
Short name T333
Test name
Test status
Simulation time 443911088 ps
CPU time 1.37 seconds
Started Apr 21 01:51:23 PM PDT 24
Finished Apr 21 01:51:25 PM PDT 24
Peak memory 197100 kb
Host smart-537489f2-4bd0-44bf-87ab-93909015a36c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809683473 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1809683473
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.284143251
Short name T58
Test name
Test status
Simulation time 404366396 ps
CPU time 0.72 seconds
Started Apr 21 01:51:20 PM PDT 24
Finished Apr 21 01:51:21 PM PDT 24
Peak memory 183924 kb
Host smart-4e421f2f-931b-461f-97dd-a18740090058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284143251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.284143251
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.223356491
Short name T320
Test name
Test status
Simulation time 378301617 ps
CPU time 0.65 seconds
Started Apr 21 01:51:22 PM PDT 24
Finished Apr 21 01:51:23 PM PDT 24
Peak memory 183960 kb
Host smart-24f1721d-6f16-4bfc-99fe-6a116cdf2d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223356491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.223356491
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3827785804
Short name T76
Test name
Test status
Simulation time 979389341 ps
CPU time 1.23 seconds
Started Apr 21 01:51:26 PM PDT 24
Finished Apr 21 01:51:28 PM PDT 24
Peak memory 184020 kb
Host smart-e83c9c3c-2d13-4906-9af0-0ff773ce3d7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827785804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3827785804
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3147041929
Short name T306
Test name
Test status
Simulation time 419235567 ps
CPU time 2.21 seconds
Started Apr 21 01:51:22 PM PDT 24
Finished Apr 21 01:51:25 PM PDT 24
Peak memory 198872 kb
Host smart-5aa475cb-d4ee-451b-9bf8-b3a5360fd39f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147041929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3147041929
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1966556932
Short name T313
Test name
Test status
Simulation time 519998101 ps
CPU time 1.04 seconds
Started Apr 21 01:51:27 PM PDT 24
Finished Apr 21 01:51:28 PM PDT 24
Peak memory 197136 kb
Host smart-bd4be7be-8370-4469-b7e9-5340ff4ae306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966556932 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1966556932
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1885619895
Short name T376
Test name
Test status
Simulation time 515173898 ps
CPU time 0.97 seconds
Started Apr 21 01:51:22 PM PDT 24
Finished Apr 21 01:51:23 PM PDT 24
Peak memory 183948 kb
Host smart-a3b77473-a460-4bcd-a84e-2b7eccf83dec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885619895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1885619895
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.393189774
Short name T342
Test name
Test status
Simulation time 465959986 ps
CPU time 0.68 seconds
Started Apr 21 01:51:23 PM PDT 24
Finished Apr 21 01:51:24 PM PDT 24
Peak memory 184124 kb
Host smart-d42c4d29-b075-46db-8cc6-fe4881ebd0f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393189774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.393189774
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3290084057
Short name T75
Test name
Test status
Simulation time 1994864022 ps
CPU time 1.8 seconds
Started Apr 21 01:51:26 PM PDT 24
Finished Apr 21 01:51:28 PM PDT 24
Peak memory 184100 kb
Host smart-215307f6-f970-4738-82e7-de82bfe75289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290084057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3290084057
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2499883035
Short name T399
Test name
Test status
Simulation time 802053701 ps
CPU time 1.97 seconds
Started Apr 21 01:51:21 PM PDT 24
Finished Apr 21 01:51:23 PM PDT 24
Peak memory 198868 kb
Host smart-05273926-13f4-4352-b239-9bbb1fa8eb42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499883035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2499883035
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3688096263
Short name T390
Test name
Test status
Simulation time 4554829702 ps
CPU time 3.02 seconds
Started Apr 21 01:51:21 PM PDT 24
Finished Apr 21 01:51:24 PM PDT 24
Peak memory 197644 kb
Host smart-a022c902-8219-47ca-8311-df671ba5975d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688096263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3688096263
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.4039439363
Short name T352
Test name
Test status
Simulation time 449457760 ps
CPU time 1 seconds
Started Apr 21 01:51:25 PM PDT 24
Finished Apr 21 01:51:26 PM PDT 24
Peak memory 195488 kb
Host smart-514728f1-e077-4665-8f7e-4d3aa2dd0de0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039439363 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.4039439363
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.4054798350
Short name T401
Test name
Test status
Simulation time 314035347 ps
CPU time 0.79 seconds
Started Apr 21 01:51:29 PM PDT 24
Finished Apr 21 01:51:30 PM PDT 24
Peak memory 183944 kb
Host smart-a278bf2e-79a2-4e52-af4a-2725acb5c800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054798350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.4054798350
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2295716786
Short name T408
Test name
Test status
Simulation time 1853421556 ps
CPU time 2.54 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:34 PM PDT 24
Peak memory 184164 kb
Host smart-ae373dad-1021-49e2-a8a7-acc6aa611871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295716786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2295716786
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.321558019
Short name T339
Test name
Test status
Simulation time 569020151 ps
CPU time 2.9 seconds
Started Apr 21 01:51:29 PM PDT 24
Finished Apr 21 01:51:32 PM PDT 24
Peak memory 198892 kb
Host smart-4b47527c-004e-4f22-973a-b477df1df5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321558019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.321558019
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.964953234
Short name T402
Test name
Test status
Simulation time 8065864825 ps
CPU time 4.95 seconds
Started Apr 21 01:51:29 PM PDT 24
Finished Apr 21 01:51:34 PM PDT 24
Peak memory 198396 kb
Host smart-974fc8c8-7d3d-4cc0-b92e-eaf21124ee69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964953234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.964953234
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4266324786
Short name T95
Test name
Test status
Simulation time 539027651 ps
CPU time 1.52 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:33 PM PDT 24
Peak memory 197260 kb
Host smart-e5f6b9b8-4fa2-4cc2-b7b2-b5a98616603d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266324786 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4266324786
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2760758185
Short name T50
Test name
Test status
Simulation time 440606440 ps
CPU time 0.77 seconds
Started Apr 21 01:51:29 PM PDT 24
Finished Apr 21 01:51:30 PM PDT 24
Peak memory 183988 kb
Host smart-1e983667-8151-4b82-8c8e-d57f7e166e67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760758185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2760758185
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.205642363
Short name T374
Test name
Test status
Simulation time 332383247 ps
CPU time 0.76 seconds
Started Apr 21 01:51:28 PM PDT 24
Finished Apr 21 01:51:29 PM PDT 24
Peak memory 183964 kb
Host smart-7c5f121a-d281-485d-adc4-fd9a1ff0c8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205642363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.205642363
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4210877256
Short name T32
Test name
Test status
Simulation time 1255509268 ps
CPU time 1.38 seconds
Started Apr 21 01:51:34 PM PDT 24
Finished Apr 21 01:51:36 PM PDT 24
Peak memory 183988 kb
Host smart-49b101bc-e408-4e67-9819-acbcf68b49f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210877256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4210877256
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3194375279
Short name T308
Test name
Test status
Simulation time 673075995 ps
CPU time 1.48 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:33 PM PDT 24
Peak memory 198808 kb
Host smart-a88525d7-fda5-4337-92d1-7c9835f530f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194375279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3194375279
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2759533402
Short name T322
Test name
Test status
Simulation time 473490746 ps
CPU time 0.81 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:32 PM PDT 24
Peak memory 196564 kb
Host smart-12350694-8b6f-45bc-9304-c637ce7f1cdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759533402 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2759533402
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2926397770
Short name T78
Test name
Test status
Simulation time 462735824 ps
CPU time 0.67 seconds
Started Apr 21 01:51:32 PM PDT 24
Finished Apr 21 01:51:33 PM PDT 24
Peak memory 193344 kb
Host smart-18d72b5f-2e93-4c5d-bd19-ca9227a89c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926397770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2926397770
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.985043493
Short name T323
Test name
Test status
Simulation time 406971799 ps
CPU time 0.63 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:32 PM PDT 24
Peak memory 183984 kb
Host smart-aadb9267-4ba5-47b5-9735-d5f456a63777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985043493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.985043493
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.39216108
Short name T350
Test name
Test status
Simulation time 2793982141 ps
CPU time 4.92 seconds
Started Apr 21 01:51:32 PM PDT 24
Finished Apr 21 01:51:37 PM PDT 24
Peak memory 195056 kb
Host smart-41ca2c2b-22ab-48c8-b91c-5cf4e6687cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_
timer_same_csr_outstanding.39216108
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3482270051
Short name T359
Test name
Test status
Simulation time 424870948 ps
CPU time 1.13 seconds
Started Apr 21 01:51:28 PM PDT 24
Finished Apr 21 01:51:29 PM PDT 24
Peak memory 198660 kb
Host smart-d6d89738-fa8e-42bc-a1ae-9ac829c048d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482270051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3482270051
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3241747888
Short name T327
Test name
Test status
Simulation time 8524927061 ps
CPU time 3.4 seconds
Started Apr 21 01:51:31 PM PDT 24
Finished Apr 21 01:51:35 PM PDT 24
Peak memory 198224 kb
Host smart-ef718285-aeca-476d-b69a-b7eae63228f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241747888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3241747888
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.821372922
Short name T321
Test name
Test status
Simulation time 626374328 ps
CPU time 1.19 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:40 PM PDT 24
Peak memory 196376 kb
Host smart-6e3816a5-5f2f-415f-b206-c39b09e63a9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821372922 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.821372922
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1613196461
Short name T366
Test name
Test status
Simulation time 546352787 ps
CPU time 1.37 seconds
Started Apr 21 01:51:39 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 193384 kb
Host smart-c098eff7-0b69-48e9-a624-3dfc498e2291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613196461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1613196461
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1764744726
Short name T346
Test name
Test status
Simulation time 492925116 ps
CPU time 1.2 seconds
Started Apr 21 01:51:40 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 183928 kb
Host smart-4f5c2949-455f-4b8d-8860-f43f6d1a955c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764744726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1764744726
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3309157183
Short name T385
Test name
Test status
Simulation time 2368582178 ps
CPU time 2.37 seconds
Started Apr 21 01:51:33 PM PDT 24
Finished Apr 21 01:51:36 PM PDT 24
Peak memory 194352 kb
Host smart-7235a5ff-74d2-4b4f-8d6f-141129df5101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309157183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3309157183
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.372840058
Short name T371
Test name
Test status
Simulation time 947902360 ps
CPU time 2.49 seconds
Started Apr 21 01:51:35 PM PDT 24
Finished Apr 21 01:51:37 PM PDT 24
Peak memory 198816 kb
Host smart-94da31ba-7e1f-4679-9ec4-ff6b619aceda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372840058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.372840058
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1555653679
Short name T395
Test name
Test status
Simulation time 4513669847 ps
CPU time 3.69 seconds
Started Apr 21 01:51:34 PM PDT 24
Finished Apr 21 01:51:38 PM PDT 24
Peak memory 196856 kb
Host smart-51e35486-6706-41fb-9126-9d56443c2ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555653679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1555653679
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1491238256
Short name T387
Test name
Test status
Simulation time 461841187 ps
CPU time 0.76 seconds
Started Apr 21 01:51:37 PM PDT 24
Finished Apr 21 01:51:38 PM PDT 24
Peak memory 195852 kb
Host smart-41e6234c-9ea7-4e27-95b7-b50d011b129f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491238256 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1491238256
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1996397254
Short name T77
Test name
Test status
Simulation time 521468392 ps
CPU time 0.75 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:39 PM PDT 24
Peak memory 183964 kb
Host smart-c66c2fed-c01f-48fc-b714-6e4e140aeceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996397254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1996397254
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3225390115
Short name T312
Test name
Test status
Simulation time 450522434 ps
CPU time 0.66 seconds
Started Apr 21 01:51:34 PM PDT 24
Finished Apr 21 01:51:35 PM PDT 24
Peak memory 183944 kb
Host smart-ff79527d-5c53-4661-98cd-3b61cfa143c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225390115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3225390115
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1853839925
Short name T369
Test name
Test status
Simulation time 2233622044 ps
CPU time 1.59 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:40 PM PDT 24
Peak memory 184260 kb
Host smart-200370b8-1748-4317-ab71-f8424fdf555b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853839925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1853839925
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1726681166
Short name T361
Test name
Test status
Simulation time 576351155 ps
CPU time 1.66 seconds
Started Apr 21 01:51:39 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 198868 kb
Host smart-2418e3ba-0db7-4246-836c-b68809e1615c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726681166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1726681166
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1957763272
Short name T38
Test name
Test status
Simulation time 4506962658 ps
CPU time 2.35 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 197728 kb
Host smart-f7ad9766-fca3-4db5-adbb-4568d2b963fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957763272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1957763272
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2585255095
Short name T349
Test name
Test status
Simulation time 579393320 ps
CPU time 0.96 seconds
Started Apr 21 01:51:40 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 198668 kb
Host smart-75088025-2efa-4f8b-94c6-af2a0f590fdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585255095 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2585255095
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4069456386
Short name T71
Test name
Test status
Simulation time 558829373 ps
CPU time 0.74 seconds
Started Apr 21 01:51:40 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 183972 kb
Host smart-01ab481a-188f-413e-b64c-2bb535e7f96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069456386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4069456386
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1511724661
Short name T383
Test name
Test status
Simulation time 338014599 ps
CPU time 1 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:39 PM PDT 24
Peak memory 183972 kb
Host smart-4eb4e1d6-6ad0-4c63-9c55-5822c31f5df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511724661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1511724661
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3740789157
Short name T410
Test name
Test status
Simulation time 1196233396 ps
CPU time 1.88 seconds
Started Apr 21 01:51:42 PM PDT 24
Finished Apr 21 01:51:44 PM PDT 24
Peak memory 184084 kb
Host smart-173ede3f-35a7-49cf-afb4-f5e2a5f68dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740789157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3740789157
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.886744725
Short name T296
Test name
Test status
Simulation time 491432510 ps
CPU time 2.92 seconds
Started Apr 21 01:51:38 PM PDT 24
Finished Apr 21 01:51:41 PM PDT 24
Peak memory 198864 kb
Host smart-0cf3045e-c8c8-4084-bcb2-6b9c3bfa67e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886744725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.886744725
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1841750604
Short name T94
Test name
Test status
Simulation time 8356680098 ps
CPU time 7.98 seconds
Started Apr 21 01:51:39 PM PDT 24
Finished Apr 21 01:51:47 PM PDT 24
Peak memory 198236 kb
Host smart-ce1f3860-cb98-47f6-9f8f-092679e4e4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841750604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1841750604
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1356070627
Short name T418
Test name
Test status
Simulation time 637705928 ps
CPU time 1 seconds
Started Apr 21 01:50:21 PM PDT 24
Finished Apr 21 01:50:22 PM PDT 24
Peak memory 194556 kb
Host smart-e5152ebb-f4d7-4e6a-8e80-529f3b530cad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356070627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1356070627
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.783435407
Short name T305
Test name
Test status
Simulation time 7148949645 ps
CPU time 10.95 seconds
Started Apr 21 01:50:19 PM PDT 24
Finished Apr 21 01:50:30 PM PDT 24
Peak memory 195956 kb
Host smart-4fcc1e8e-7c2a-48aa-ac3c-b31f6b66cc0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783435407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.783435407
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.730475480
Short name T417
Test name
Test status
Simulation time 1043842550 ps
CPU time 0.95 seconds
Started Apr 21 01:50:17 PM PDT 24
Finished Apr 21 01:50:18 PM PDT 24
Peak memory 183972 kb
Host smart-caf40041-eef2-4fa2-ac87-d9e6cdacc819
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730475480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.730475480
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2226678815
Short name T419
Test name
Test status
Simulation time 418685579 ps
CPU time 1.29 seconds
Started Apr 21 01:50:24 PM PDT 24
Finished Apr 21 01:50:25 PM PDT 24
Peak memory 196356 kb
Host smart-03766514-bec8-4813-886e-8666c2499bc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226678815 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2226678815
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1712299605
Short name T70
Test name
Test status
Simulation time 523615624 ps
CPU time 0.78 seconds
Started Apr 21 01:50:18 PM PDT 24
Finished Apr 21 01:50:19 PM PDT 24
Peak memory 193328 kb
Host smart-f4c76008-a4d9-4f4e-90b9-1f0c441ad7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712299605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1712299605
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2525986390
Short name T291
Test name
Test status
Simulation time 378892138 ps
CPU time 0.64 seconds
Started Apr 21 01:50:15 PM PDT 24
Finished Apr 21 01:50:16 PM PDT 24
Peak memory 183928 kb
Host smart-1fcd9b8b-0f40-450e-ac78-b654b8f38257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525986390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2525986390
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.126945915
Short name T411
Test name
Test status
Simulation time 305296171 ps
CPU time 0.94 seconds
Started Apr 21 01:50:18 PM PDT 24
Finished Apr 21 01:50:19 PM PDT 24
Peak memory 183876 kb
Host smart-1e4cc5de-29db-42f2-937a-079f5fca4163
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126945915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.126945915
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1377750515
Short name T403
Test name
Test status
Simulation time 359581646 ps
CPU time 0.69 seconds
Started Apr 21 01:50:18 PM PDT 24
Finished Apr 21 01:50:19 PM PDT 24
Peak memory 183848 kb
Host smart-9a592fed-8b34-4dc0-b2c8-d6c67276e1d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377750515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1377750515
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3656355053
Short name T422
Test name
Test status
Simulation time 2165234836 ps
CPU time 1.42 seconds
Started Apr 21 01:50:25 PM PDT 24
Finished Apr 21 01:50:27 PM PDT 24
Peak memory 184092 kb
Host smart-6f6f0f75-e4f0-4994-a448-ad4882cf5fdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656355053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3656355053
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3591129477
Short name T421
Test name
Test status
Simulation time 631383971 ps
CPU time 2.5 seconds
Started Apr 21 01:50:15 PM PDT 24
Finished Apr 21 01:50:17 PM PDT 24
Peak memory 198804 kb
Host smart-ddd51103-cfb4-47c1-aa6d-a647127dbabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591129477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3591129477
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3490940680
Short name T353
Test name
Test status
Simulation time 8564978042 ps
CPU time 4.52 seconds
Started Apr 21 01:50:14 PM PDT 24
Finished Apr 21 01:50:19 PM PDT 24
Peak memory 198348 kb
Host smart-54579fcb-756e-400e-b66d-da49f4e81732
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490940680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3490940680
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.854307677
Short name T358
Test name
Test status
Simulation time 508851352 ps
CPU time 1.27 seconds
Started Apr 21 01:51:44 PM PDT 24
Finished Apr 21 01:51:45 PM PDT 24
Peak memory 183924 kb
Host smart-21490319-4223-4777-b5e1-52213abd7bbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854307677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.854307677
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3020884421
Short name T409
Test name
Test status
Simulation time 563932057 ps
CPU time 0.6 seconds
Started Apr 21 01:51:43 PM PDT 24
Finished Apr 21 01:51:44 PM PDT 24
Peak memory 183940 kb
Host smart-dd92bc94-10b2-4ff7-a89f-0416b6b81e75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020884421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3020884421
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1309992086
Short name T423
Test name
Test status
Simulation time 463104622 ps
CPU time 0.59 seconds
Started Apr 21 01:51:44 PM PDT 24
Finished Apr 21 01:51:44 PM PDT 24
Peak memory 183948 kb
Host smart-a8fcba81-680d-437b-8320-a09b5d97fc50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309992086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1309992086
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.76465933
Short name T285
Test name
Test status
Simulation time 277432092 ps
CPU time 0.7 seconds
Started Apr 21 01:51:42 PM PDT 24
Finished Apr 21 01:51:43 PM PDT 24
Peak memory 183952 kb
Host smart-773ba1b1-fdc7-4bba-8db2-6a5760f85d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76465933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.76465933
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2736143671
Short name T354
Test name
Test status
Simulation time 535634106 ps
CPU time 0.69 seconds
Started Apr 21 01:51:43 PM PDT 24
Finished Apr 21 01:51:44 PM PDT 24
Peak memory 183952 kb
Host smart-3a8e4065-8926-4e21-9a84-63905f652096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736143671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2736143671
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1790038748
Short name T389
Test name
Test status
Simulation time 392328760 ps
CPU time 0.68 seconds
Started Apr 21 01:51:46 PM PDT 24
Finished Apr 21 01:51:47 PM PDT 24
Peak memory 183884 kb
Host smart-6cd087fc-4bb9-4845-b448-0642d0c0a57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790038748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1790038748
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2495434175
Short name T391
Test name
Test status
Simulation time 511880448 ps
CPU time 0.71 seconds
Started Apr 21 01:51:46 PM PDT 24
Finished Apr 21 01:51:47 PM PDT 24
Peak memory 183912 kb
Host smart-682c75cb-4ebf-4c48-84f7-c280a5ffba3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495434175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2495434175
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3287549015
Short name T405
Test name
Test status
Simulation time 322123486 ps
CPU time 0.95 seconds
Started Apr 21 01:51:51 PM PDT 24
Finished Apr 21 01:51:52 PM PDT 24
Peak memory 183904 kb
Host smart-d48468c2-681d-497b-9e95-d425a14c4d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287549015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3287549015
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1658074782
Short name T343
Test name
Test status
Simulation time 488210591 ps
CPU time 0.72 seconds
Started Apr 21 01:51:47 PM PDT 24
Finished Apr 21 01:51:48 PM PDT 24
Peak memory 183912 kb
Host smart-0b04eec4-4d9d-4b44-b1f8-064dad41d33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658074782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1658074782
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2711804666
Short name T375
Test name
Test status
Simulation time 470486094 ps
CPU time 0.84 seconds
Started Apr 21 01:51:47 PM PDT 24
Finished Apr 21 01:51:48 PM PDT 24
Peak memory 183948 kb
Host smart-4d248966-d028-459c-be1a-12fa81abfb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711804666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2711804666
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1207458585
Short name T56
Test name
Test status
Simulation time 744521711 ps
CPU time 1.06 seconds
Started Apr 21 01:50:33 PM PDT 24
Finished Apr 21 01:50:34 PM PDT 24
Peak memory 194540 kb
Host smart-41082816-3ade-4b25-a036-e069b1d2f576
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207458585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1207458585
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3893153391
Short name T300
Test name
Test status
Simulation time 7173517304 ps
CPU time 10.76 seconds
Started Apr 21 01:50:28 PM PDT 24
Finished Apr 21 01:50:39 PM PDT 24
Peak memory 195908 kb
Host smart-ec459579-34bc-469f-bd61-f1d24c834094
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893153391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3893153391
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.867731442
Short name T295
Test name
Test status
Simulation time 691708365 ps
CPU time 1.04 seconds
Started Apr 21 01:50:27 PM PDT 24
Finished Apr 21 01:50:28 PM PDT 24
Peak memory 184024 kb
Host smart-5ac0ea33-6936-403e-8005-176286c20dbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867731442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.867731442
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.113316406
Short name T314
Test name
Test status
Simulation time 448609382 ps
CPU time 1.05 seconds
Started Apr 21 01:50:37 PM PDT 24
Finished Apr 21 01:50:38 PM PDT 24
Peak memory 198724 kb
Host smart-d638a767-0978-4fcd-a326-ac4b7caa2ebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113316406 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.113316406
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.565970561
Short name T55
Test name
Test status
Simulation time 383724836 ps
CPU time 0.62 seconds
Started Apr 21 01:50:26 PM PDT 24
Finished Apr 21 01:50:27 PM PDT 24
Peak memory 183964 kb
Host smart-f717d523-187c-4044-a9f4-e261c03d556f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565970561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.565970561
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4291695116
Short name T311
Test name
Test status
Simulation time 322290357 ps
CPU time 1.01 seconds
Started Apr 21 01:50:25 PM PDT 24
Finished Apr 21 01:50:26 PM PDT 24
Peak memory 183956 kb
Host smart-04f2337f-f810-4e9a-af95-6eca68d16528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291695116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4291695116
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.49062459
Short name T373
Test name
Test status
Simulation time 304953518 ps
CPU time 0.7 seconds
Started Apr 21 01:50:26 PM PDT 24
Finished Apr 21 01:50:27 PM PDT 24
Peak memory 183868 kb
Host smart-4dc2de04-ae87-48ba-8723-b07e3bd80e4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49062459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_tim
er_mem_partial_access.49062459
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.705556995
Short name T336
Test name
Test status
Simulation time 526541430 ps
CPU time 0.68 seconds
Started Apr 21 01:50:26 PM PDT 24
Finished Apr 21 01:50:27 PM PDT 24
Peak memory 183848 kb
Host smart-017eaa8c-d337-449d-91ad-8276c4ae851a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705556995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.705556995
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.4229565532
Short name T362
Test name
Test status
Simulation time 1276517677 ps
CPU time 1.45 seconds
Started Apr 21 01:50:34 PM PDT 24
Finished Apr 21 01:50:35 PM PDT 24
Peak memory 193740 kb
Host smart-a3f30826-7f17-4bfd-bd3d-3d91b6eec464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229565532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.4229565532
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3797725152
Short name T404
Test name
Test status
Simulation time 401431037 ps
CPU time 2.32 seconds
Started Apr 21 01:50:24 PM PDT 24
Finished Apr 21 01:50:26 PM PDT 24
Peak memory 198868 kb
Host smart-01a28eb7-528d-4edb-97dd-aa262393703a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797725152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3797725152
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3751411182
Short name T31
Test name
Test status
Simulation time 4405369804 ps
CPU time 2.34 seconds
Started Apr 21 01:50:29 PM PDT 24
Finished Apr 21 01:50:31 PM PDT 24
Peak memory 197828 kb
Host smart-b369837d-76c8-4734-830c-b5f6cc2dd154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751411182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3751411182
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1652424471
Short name T302
Test name
Test status
Simulation time 312702968 ps
CPU time 1.01 seconds
Started Apr 21 01:51:49 PM PDT 24
Finished Apr 21 01:51:51 PM PDT 24
Peak memory 183944 kb
Host smart-52ef6540-2032-4922-bc7c-bd3d51de6550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652424471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1652424471
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2396455918
Short name T370
Test name
Test status
Simulation time 437885467 ps
CPU time 0.83 seconds
Started Apr 21 01:51:51 PM PDT 24
Finished Apr 21 01:51:52 PM PDT 24
Peak memory 183908 kb
Host smart-7e941fd5-45d9-4849-b356-e0fd557e5443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396455918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2396455918
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3573103000
Short name T356
Test name
Test status
Simulation time 442470555 ps
CPU time 0.77 seconds
Started Apr 21 01:51:49 PM PDT 24
Finished Apr 21 01:51:50 PM PDT 24
Peak memory 183952 kb
Host smart-96863eab-7974-4e81-81e0-4d28b106a9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573103000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3573103000
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1176899424
Short name T315
Test name
Test status
Simulation time 505895478 ps
CPU time 0.68 seconds
Started Apr 21 01:52:06 PM PDT 24
Finished Apr 21 01:52:07 PM PDT 24
Peak memory 183948 kb
Host smart-d7749970-2e6f-47aa-9545-373531f39919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176899424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1176899424
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1104566398
Short name T382
Test name
Test status
Simulation time 366335266 ps
CPU time 0.62 seconds
Started Apr 21 01:51:52 PM PDT 24
Finished Apr 21 01:51:53 PM PDT 24
Peak memory 183912 kb
Host smart-ed30abc0-87a7-4ef6-b99c-60d0706aadab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104566398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1104566398
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2735646483
Short name T286
Test name
Test status
Simulation time 367677858 ps
CPU time 0.81 seconds
Started Apr 21 01:51:52 PM PDT 24
Finished Apr 21 01:51:53 PM PDT 24
Peak memory 183904 kb
Host smart-d17b5f68-69f2-4c67-8999-5de06d6ae235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735646483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2735646483
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3855059238
Short name T348
Test name
Test status
Simulation time 367783251 ps
CPU time 1.13 seconds
Started Apr 21 01:51:52 PM PDT 24
Finished Apr 21 01:51:53 PM PDT 24
Peak memory 183908 kb
Host smart-fec76b04-28b3-4b52-b5a0-ecf8c7b89385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855059238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3855059238
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4218484865
Short name T304
Test name
Test status
Simulation time 452411511 ps
CPU time 0.67 seconds
Started Apr 21 01:51:53 PM PDT 24
Finished Apr 21 01:51:54 PM PDT 24
Peak memory 183912 kb
Host smart-91b08f47-0bc1-4b0a-b242-71989e674361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218484865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4218484865
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.792793560
Short name T319
Test name
Test status
Simulation time 349635925 ps
CPU time 0.61 seconds
Started Apr 21 01:51:54 PM PDT 24
Finished Apr 21 01:51:55 PM PDT 24
Peak memory 183928 kb
Host smart-8d7c9976-4658-4c5f-8c1d-a90e13ef185d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792793560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.792793560
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2590529091
Short name T380
Test name
Test status
Simulation time 371296893 ps
CPU time 1.13 seconds
Started Apr 21 01:51:54 PM PDT 24
Finished Apr 21 01:51:55 PM PDT 24
Peak memory 183916 kb
Host smart-368549a6-00b6-4fe6-b8cf-d5be75d4c353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590529091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2590529091
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2290803282
Short name T347
Test name
Test status
Simulation time 617117366 ps
CPU time 0.75 seconds
Started Apr 21 01:50:44 PM PDT 24
Finished Apr 21 01:50:45 PM PDT 24
Peak memory 193428 kb
Host smart-0bca69f6-d5ed-49af-af8c-772c4418fc8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290803282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2290803282
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1933556955
Short name T377
Test name
Test status
Simulation time 13864969310 ps
CPU time 18.63 seconds
Started Apr 21 01:50:43 PM PDT 24
Finished Apr 21 01:51:02 PM PDT 24
Peak memory 192472 kb
Host smart-f2fc2f48-3a97-47f1-ab3e-7cd84220e271
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933556955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1933556955
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.185738730
Short name T51
Test name
Test status
Simulation time 1152663167 ps
CPU time 0.94 seconds
Started Apr 21 01:50:43 PM PDT 24
Finished Apr 21 01:50:44 PM PDT 24
Peak memory 184048 kb
Host smart-97755d1e-e815-4d1f-ba4b-a57de0c7a6fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185738730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.185738730
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3918042917
Short name T381
Test name
Test status
Simulation time 541885873 ps
CPU time 0.92 seconds
Started Apr 21 01:50:50 PM PDT 24
Finished Apr 21 01:50:51 PM PDT 24
Peak memory 197288 kb
Host smart-90420cf4-6f80-44d3-89e7-270087419c66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918042917 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3918042917
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1665629616
Short name T57
Test name
Test status
Simulation time 372408508 ps
CPU time 1.08 seconds
Started Apr 21 01:50:44 PM PDT 24
Finished Apr 21 01:50:45 PM PDT 24
Peak memory 193340 kb
Host smart-2ec09c6b-7fa2-4fa0-a4df-755f656f067e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665629616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1665629616
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2277421500
Short name T337
Test name
Test status
Simulation time 487434440 ps
CPU time 0.88 seconds
Started Apr 21 01:50:39 PM PDT 24
Finished Apr 21 01:50:40 PM PDT 24
Peak memory 183944 kb
Host smart-d8b83e22-4cfe-4a30-acf1-f8ff89f0282d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277421500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2277421500
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1893997133
Short name T412
Test name
Test status
Simulation time 438759428 ps
CPU time 0.79 seconds
Started Apr 21 01:50:44 PM PDT 24
Finished Apr 21 01:50:45 PM PDT 24
Peak memory 183860 kb
Host smart-7545c3ec-45d8-4a98-8a03-0361a2d1ab8b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893997133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1893997133
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1280726980
Short name T355
Test name
Test status
Simulation time 353852192 ps
CPU time 0.99 seconds
Started Apr 21 01:50:40 PM PDT 24
Finished Apr 21 01:50:41 PM PDT 24
Peak memory 183884 kb
Host smart-0a45565f-57b4-4655-89b9-bf0fc40287d9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280726980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1280726980
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4256098747
Short name T415
Test name
Test status
Simulation time 2748415607 ps
CPU time 4.04 seconds
Started Apr 21 01:50:49 PM PDT 24
Finished Apr 21 01:50:53 PM PDT 24
Peak memory 194712 kb
Host smart-0b76d0fe-51a3-4bd3-983b-f02b72191785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256098747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4256098747
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.880738040
Short name T293
Test name
Test status
Simulation time 362432548 ps
CPU time 2.15 seconds
Started Apr 21 01:50:35 PM PDT 24
Finished Apr 21 01:50:38 PM PDT 24
Peak memory 198896 kb
Host smart-3f367ace-177f-4d78-908c-bebb12d2c344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880738040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.880738040
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2514405405
Short name T92
Test name
Test status
Simulation time 8124401886 ps
CPU time 4.16 seconds
Started Apr 21 01:50:38 PM PDT 24
Finished Apr 21 01:50:43 PM PDT 24
Peak memory 198152 kb
Host smart-3e5d22d8-c79e-49dd-b6ea-de4d60994bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514405405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2514405405
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.4187909340
Short name T416
Test name
Test status
Simulation time 500464752 ps
CPU time 0.72 seconds
Started Apr 21 01:51:56 PM PDT 24
Finished Apr 21 01:51:57 PM PDT 24
Peak memory 183944 kb
Host smart-ce42925c-8cb2-4369-9b69-b6bd5d7863be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187909340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.4187909340
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1366567556
Short name T425
Test name
Test status
Simulation time 427463464 ps
CPU time 0.59 seconds
Started Apr 21 01:51:54 PM PDT 24
Finished Apr 21 01:51:55 PM PDT 24
Peak memory 183956 kb
Host smart-c135d390-069a-4a18-b9e3-31f32a3f51c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366567556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1366567556
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.4172869313
Short name T396
Test name
Test status
Simulation time 353105409 ps
CPU time 0.64 seconds
Started Apr 21 01:51:57 PM PDT 24
Finished Apr 21 01:51:58 PM PDT 24
Peak memory 183936 kb
Host smart-675b421e-2827-4823-b003-2c4beb122723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172869313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.4172869313
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2603664070
Short name T297
Test name
Test status
Simulation time 485015699 ps
CPU time 0.89 seconds
Started Apr 21 01:51:55 PM PDT 24
Finished Apr 21 01:51:56 PM PDT 24
Peak memory 183948 kb
Host smart-d39d4b31-d704-4ba6-9f33-64a0216e48c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603664070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2603664070
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3698061577
Short name T367
Test name
Test status
Simulation time 451578898 ps
CPU time 0.99 seconds
Started Apr 21 01:51:55 PM PDT 24
Finished Apr 21 01:51:56 PM PDT 24
Peak memory 183956 kb
Host smart-f125207f-dbf1-44c8-8d41-c8e149537f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698061577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3698061577
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1184085147
Short name T386
Test name
Test status
Simulation time 349389286 ps
CPU time 0.64 seconds
Started Apr 21 01:51:56 PM PDT 24
Finished Apr 21 01:51:57 PM PDT 24
Peak memory 183948 kb
Host smart-1906fc46-6a21-4452-bb36-9062220f430d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184085147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1184085147
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1447332084
Short name T394
Test name
Test status
Simulation time 501705078 ps
CPU time 1.31 seconds
Started Apr 21 01:51:54 PM PDT 24
Finished Apr 21 01:51:55 PM PDT 24
Peak memory 183940 kb
Host smart-8f42fd3f-67d7-4d4f-9f72-6463a202cb03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447332084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1447332084
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3493097401
Short name T400
Test name
Test status
Simulation time 454199168 ps
CPU time 1.2 seconds
Started Apr 21 01:51:59 PM PDT 24
Finished Apr 21 01:52:00 PM PDT 24
Peak memory 183936 kb
Host smart-ae3fb19a-4c0e-4a15-bb48-1f4230e32d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493097401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3493097401
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3773536883
Short name T378
Test name
Test status
Simulation time 454384297 ps
CPU time 1.28 seconds
Started Apr 21 01:51:57 PM PDT 24
Finished Apr 21 01:51:59 PM PDT 24
Peak memory 183972 kb
Host smart-1d13d859-0df6-4484-afc8-f085dfe327b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773536883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3773536883
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2842882623
Short name T288
Test name
Test status
Simulation time 306414831 ps
CPU time 0.95 seconds
Started Apr 21 01:51:58 PM PDT 24
Finished Apr 21 01:51:59 PM PDT 24
Peak memory 183928 kb
Host smart-25ccc9a7-c6f7-4305-abb2-dc5c19d35c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842882623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2842882623
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1753696196
Short name T351
Test name
Test status
Simulation time 368310479 ps
CPU time 0.93 seconds
Started Apr 21 01:50:50 PM PDT 24
Finished Apr 21 01:50:51 PM PDT 24
Peak memory 196124 kb
Host smart-9f9e3bc2-a017-42fb-872c-bb7fb3b43f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753696196 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1753696196
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.971174649
Short name T37
Test name
Test status
Simulation time 335166185 ps
CPU time 0.67 seconds
Started Apr 21 01:50:51 PM PDT 24
Finished Apr 21 01:50:52 PM PDT 24
Peak memory 183976 kb
Host smart-ac5fe206-fe2d-4205-b66f-c7e9139afc63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971174649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.971174649
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1468991992
Short name T368
Test name
Test status
Simulation time 417959899 ps
CPU time 1.17 seconds
Started Apr 21 01:50:47 PM PDT 24
Finished Apr 21 01:50:49 PM PDT 24
Peak memory 184124 kb
Host smart-79803684-4e3b-426e-adc1-88f4258b3282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468991992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1468991992
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.191645660
Short name T357
Test name
Test status
Simulation time 1840605732 ps
CPU time 5.22 seconds
Started Apr 21 01:50:52 PM PDT 24
Finished Apr 21 01:50:57 PM PDT 24
Peak memory 193732 kb
Host smart-b288c727-b74c-42fd-8498-33a0f10a30c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191645660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.191645660
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3558117198
Short name T325
Test name
Test status
Simulation time 962476572 ps
CPU time 2.34 seconds
Started Apr 21 01:50:48 PM PDT 24
Finished Apr 21 01:50:50 PM PDT 24
Peak memory 198924 kb
Host smart-60a0c692-30cc-4289-9a0a-a4c737f41e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558117198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3558117198
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1135192895
Short name T91
Test name
Test status
Simulation time 8427189801 ps
CPU time 7.76 seconds
Started Apr 21 01:50:50 PM PDT 24
Finished Apr 21 01:50:58 PM PDT 24
Peak memory 197992 kb
Host smart-44688fb8-cefe-4e8e-bd6f-214184d5e0b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135192895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1135192895
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1053931108
Short name T340
Test name
Test status
Simulation time 628195490 ps
CPU time 0.89 seconds
Started Apr 21 01:50:56 PM PDT 24
Finished Apr 21 01:50:57 PM PDT 24
Peak memory 196464 kb
Host smart-dd561938-047c-44cc-88dd-cfb2b83332b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053931108 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1053931108
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3265184918
Short name T324
Test name
Test status
Simulation time 392211661 ps
CPU time 0.85 seconds
Started Apr 21 01:50:54 PM PDT 24
Finished Apr 21 01:50:55 PM PDT 24
Peak memory 184152 kb
Host smart-0588885c-fb1b-4bba-9937-48df8e8ca89d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265184918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3265184918
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3554877692
Short name T309
Test name
Test status
Simulation time 397516685 ps
CPU time 0.66 seconds
Started Apr 21 01:50:53 PM PDT 24
Finished Apr 21 01:50:54 PM PDT 24
Peak memory 183940 kb
Host smart-75d74c4c-9fe8-4a50-a094-4e460d6808d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554877692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3554877692
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1183049306
Short name T335
Test name
Test status
Simulation time 1295107316 ps
CPU time 2.2 seconds
Started Apr 21 01:50:53 PM PDT 24
Finished Apr 21 01:50:56 PM PDT 24
Peak memory 184220 kb
Host smart-fc6eb888-813b-4aa3-9973-ffea7fd21fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183049306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1183049306
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1669523244
Short name T310
Test name
Test status
Simulation time 564061422 ps
CPU time 2.21 seconds
Started Apr 21 01:50:50 PM PDT 24
Finished Apr 21 01:50:52 PM PDT 24
Peak memory 198872 kb
Host smart-305303c7-4f4f-413e-9ed3-1319754f940f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669523244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1669523244
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1163873409
Short name T93
Test name
Test status
Simulation time 4151073431 ps
CPU time 4.17 seconds
Started Apr 21 01:50:51 PM PDT 24
Finished Apr 21 01:50:55 PM PDT 24
Peak memory 197724 kb
Host smart-8e4504c4-da6d-4da4-99e9-5f9320477f52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163873409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1163873409
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1826426829
Short name T393
Test name
Test status
Simulation time 407998674 ps
CPU time 1.29 seconds
Started Apr 21 01:51:02 PM PDT 24
Finished Apr 21 01:51:03 PM PDT 24
Peak memory 195888 kb
Host smart-85c2d268-3da7-4988-aafe-3575884e5b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826426829 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1826426829
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.30203642
Short name T60
Test name
Test status
Simulation time 463653104 ps
CPU time 1.29 seconds
Started Apr 21 01:50:57 PM PDT 24
Finished Apr 21 01:50:59 PM PDT 24
Peak memory 183948 kb
Host smart-44fd2cb3-bd7a-428f-b4aa-f858ed004622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.30203642
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1119512691
Short name T287
Test name
Test status
Simulation time 294561537 ps
CPU time 0.63 seconds
Started Apr 21 01:50:56 PM PDT 24
Finished Apr 21 01:50:57 PM PDT 24
Peak memory 183960 kb
Host smart-25772705-be42-4614-ac27-37c4a53d6459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119512691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1119512691
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4033315758
Short name T413
Test name
Test status
Simulation time 1205144654 ps
CPU time 2.9 seconds
Started Apr 21 01:50:56 PM PDT 24
Finished Apr 21 01:50:59 PM PDT 24
Peak memory 183996 kb
Host smart-9e709752-a798-4cfd-b95e-5f0a532b0d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033315758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4033315758
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2007841025
Short name T331
Test name
Test status
Simulation time 507996651 ps
CPU time 1.94 seconds
Started Apr 21 01:50:57 PM PDT 24
Finished Apr 21 01:50:59 PM PDT 24
Peak memory 198948 kb
Host smart-429438bd-a83a-4a9b-a5c9-6ad684320e31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007841025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2007841025
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3167040173
Short name T365
Test name
Test status
Simulation time 8482241144 ps
CPU time 8.08 seconds
Started Apr 21 01:50:56 PM PDT 24
Finished Apr 21 01:51:04 PM PDT 24
Peak memory 198276 kb
Host smart-f5e7eccd-88e6-4afd-9997-b14503d60183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167040173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3167040173
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2492249776
Short name T318
Test name
Test status
Simulation time 860115462 ps
CPU time 1.19 seconds
Started Apr 21 01:51:01 PM PDT 24
Finished Apr 21 01:51:02 PM PDT 24
Peak memory 198908 kb
Host smart-8d2f8f1f-6e38-435f-8094-ae0cd87fbb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492249776 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2492249776
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.201948963
Short name T52
Test name
Test status
Simulation time 493773989 ps
CPU time 0.75 seconds
Started Apr 21 01:51:02 PM PDT 24
Finished Apr 21 01:51:03 PM PDT 24
Peak memory 193320 kb
Host smart-17c1b193-d4f0-475c-aa58-ca33eab3eeda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201948963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.201948963
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.478673552
Short name T329
Test name
Test status
Simulation time 462497194 ps
CPU time 1.17 seconds
Started Apr 21 01:50:58 PM PDT 24
Finished Apr 21 01:50:59 PM PDT 24
Peak memory 183948 kb
Host smart-6d002669-23b5-46cc-a444-7dd880467f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478673552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.478673552
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1110965402
Short name T72
Test name
Test status
Simulation time 1789332323 ps
CPU time 4.8 seconds
Started Apr 21 01:51:02 PM PDT 24
Finished Apr 21 01:51:07 PM PDT 24
Peak memory 184068 kb
Host smart-dd6f8c40-9ff4-4e86-bff7-06c7fe7df3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110965402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1110965402
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3804979117
Short name T303
Test name
Test status
Simulation time 454592339 ps
CPU time 2.59 seconds
Started Apr 21 01:51:02 PM PDT 24
Finished Apr 21 01:51:05 PM PDT 24
Peak memory 198844 kb
Host smart-1bbdc628-8ba8-466b-836d-8cb79462a71d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804979117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3804979117
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1815678550
Short name T341
Test name
Test status
Simulation time 8638738921 ps
CPU time 3.9 seconds
Started Apr 21 01:51:01 PM PDT 24
Finished Apr 21 01:51:05 PM PDT 24
Peak memory 198076 kb
Host smart-2636f703-a50e-4756-843d-59b26af05291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815678550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1815678550
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2130337505
Short name T360
Test name
Test status
Simulation time 393419337 ps
CPU time 0.87 seconds
Started Apr 21 01:51:07 PM PDT 24
Finished Apr 21 01:51:08 PM PDT 24
Peak memory 195684 kb
Host smart-d79a403e-389b-4739-9f0d-ad5bf7746ab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130337505 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2130337505
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2234235895
Short name T398
Test name
Test status
Simulation time 362563951 ps
CPU time 0.66 seconds
Started Apr 21 01:51:07 PM PDT 24
Finished Apr 21 01:51:08 PM PDT 24
Peak memory 183896 kb
Host smart-2ca9ad50-383c-498b-9dbc-6ea7c7b1d98f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234235895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2234235895
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3882006751
Short name T397
Test name
Test status
Simulation time 408839654 ps
CPU time 0.6 seconds
Started Apr 21 01:51:06 PM PDT 24
Finished Apr 21 01:51:06 PM PDT 24
Peak memory 183956 kb
Host smart-aaba3962-0ff3-4be5-8e7a-6abccd6f1347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882006751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3882006751
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3059116593
Short name T73
Test name
Test status
Simulation time 1219790875 ps
CPU time 0.84 seconds
Started Apr 21 01:51:07 PM PDT 24
Finished Apr 21 01:51:09 PM PDT 24
Peak memory 193536 kb
Host smart-65ba0ca1-6d6f-4eab-af64-671f57afd71f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059116593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3059116593
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4061908036
Short name T364
Test name
Test status
Simulation time 809624659 ps
CPU time 1.88 seconds
Started Apr 21 01:51:02 PM PDT 24
Finished Apr 21 01:51:05 PM PDT 24
Peak memory 198860 kb
Host smart-947dfeb8-d7b1-41cd-a9db-9a06e56b06c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061908036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4061908036
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4069551426
Short name T345
Test name
Test status
Simulation time 8086472394 ps
CPU time 3.46 seconds
Started Apr 21 01:51:05 PM PDT 24
Finished Apr 21 01:51:09 PM PDT 24
Peak memory 198224 kb
Host smart-1dd48220-a831-4e74-9e44-b65cd73b73e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069551426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4069551426
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3684553922
Short name T225
Test name
Test status
Simulation time 545078402 ps
CPU time 0.65 seconds
Started Apr 21 12:49:18 PM PDT 24
Finished Apr 21 12:49:19 PM PDT 24
Peak memory 183284 kb
Host smart-50823018-29b8-4dc5-8a8a-83cb4603f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684553922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3684553922
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4028702804
Short name T188
Test name
Test status
Simulation time 5455847473 ps
CPU time 7.66 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 183364 kb
Host smart-44e91d90-10f0-4b00-9bc2-fca8fffade92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028702804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4028702804
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.693614513
Short name T257
Test name
Test status
Simulation time 450112126 ps
CPU time 0.74 seconds
Started Apr 21 12:49:16 PM PDT 24
Finished Apr 21 12:49:17 PM PDT 24
Peak memory 183300 kb
Host smart-245c9481-3a7d-4009-ae62-16e74e771322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693614513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.693614513
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.927036938
Short name T246
Test name
Test status
Simulation time 141727295142 ps
CPU time 130.5 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:51:40 PM PDT 24
Peak memory 183272 kb
Host smart-e048b10e-e33c-4b8c-8b33-ce866db017ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927036938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.927036938
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1785573321
Short name T153
Test name
Test status
Simulation time 361605219 ps
CPU time 1.07 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 183244 kb
Host smart-74a5c443-fe0b-4519-a624-3554da019e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785573321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1785573321
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4238745141
Short name T274
Test name
Test status
Simulation time 46258614603 ps
CPU time 18.9 seconds
Started Apr 21 12:49:14 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 183336 kb
Host smart-5406d518-8cfe-4900-966b-50b1f8713ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238745141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4238745141
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2628124348
Short name T16
Test name
Test status
Simulation time 3959362607 ps
CPU time 6.99 seconds
Started Apr 21 12:49:24 PM PDT 24
Finished Apr 21 12:49:31 PM PDT 24
Peak memory 214728 kb
Host smart-30a24158-37bd-4e4f-b4fa-a4f96a5f5fff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628124348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2628124348
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3004669981
Short name T238
Test name
Test status
Simulation time 570933913 ps
CPU time 0.93 seconds
Started Apr 21 12:49:25 PM PDT 24
Finished Apr 21 12:49:27 PM PDT 24
Peak memory 183248 kb
Host smart-f1a7d8f2-a01e-4bd6-8e4f-196f61c5bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004669981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3004669981
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2812753385
Short name T275
Test name
Test status
Simulation time 122977675686 ps
CPU time 161.14 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:52:17 PM PDT 24
Peak memory 194568 kb
Host smart-f9a27c34-62e3-4898-9e79-f86b9548d8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812753385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2812753385
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1784433975
Short name T221
Test name
Test status
Simulation time 61136167886 ps
CPU time 348.98 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:55:19 PM PDT 24
Peak memory 198288 kb
Host smart-8ee2b522-e2ab-46a3-b026-b5fbb654a3fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784433975 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1784433975
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.486847063
Short name T165
Test name
Test status
Simulation time 484593490 ps
CPU time 1.3 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:49:36 PM PDT 24
Peak memory 183244 kb
Host smart-c3702f84-f779-49ca-94a0-027e4dc366fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486847063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.486847063
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3155399555
Short name T241
Test name
Test status
Simulation time 6817049452 ps
CPU time 1.11 seconds
Started Apr 21 12:49:40 PM PDT 24
Finished Apr 21 12:49:41 PM PDT 24
Peak memory 183280 kb
Host smart-0a7dc459-ad05-44e1-821c-1f430a2924b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155399555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3155399555
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3980357435
Short name T103
Test name
Test status
Simulation time 502134397 ps
CPU time 1.37 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 183292 kb
Host smart-cd69d7f9-91f3-46d0-a206-8678fa7984c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980357435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3980357435
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.230159777
Short name T150
Test name
Test status
Simulation time 36550178454 ps
CPU time 63.53 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:50:42 PM PDT 24
Peak memory 183372 kb
Host smart-b578ffc0-5c2f-4d56-ac60-5806f57e85c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230159777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.230159777
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.644066944
Short name T158
Test name
Test status
Simulation time 425395217 ps
CPU time 1.3 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:29 PM PDT 24
Peak memory 183296 kb
Host smart-4e5cb396-d3cd-457e-948d-f7258b18d5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644066944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.644066944
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4161497389
Short name T205
Test name
Test status
Simulation time 23965893250 ps
CPU time 39.21 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 183336 kb
Host smart-1e9ceb5b-1092-4806-9df6-77ec858afc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161497389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4161497389
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1639492727
Short name T121
Test name
Test status
Simulation time 397953790 ps
CPU time 0.78 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 183296 kb
Host smart-d5de1e2e-b2a6-46a2-b264-afd7d6fbaf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639492727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1639492727
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.390069169
Short name T243
Test name
Test status
Simulation time 52043102819 ps
CPU time 73.5 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:50:52 PM PDT 24
Peak memory 193720 kb
Host smart-c6c6e9c0-53ac-4fa8-b78c-324a9d154072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390069169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.390069169
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2233057964
Short name T249
Test name
Test status
Simulation time 70262544793 ps
CPU time 119.98 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:51:30 PM PDT 24
Peak memory 198252 kb
Host smart-71eae1ca-917c-4e57-8909-48846bddcfa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233057964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2233057964
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1300534163
Short name T202
Test name
Test status
Simulation time 572824886 ps
CPU time 0.79 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:49:47 PM PDT 24
Peak memory 183244 kb
Host smart-ead481ee-088c-4ac3-90cb-0335eaaca81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300534163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1300534163
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.946008189
Short name T174
Test name
Test status
Simulation time 12348825285 ps
CPU time 18.11 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:45 PM PDT 24
Peak memory 183328 kb
Host smart-ba376a46-1bcc-48ef-841e-c19786d674f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946008189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.946008189
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2071844319
Short name T171
Test name
Test status
Simulation time 624113689 ps
CPU time 1.45 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183296 kb
Host smart-c37caf41-f01f-46b7-bd7e-9b9240309454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071844319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2071844319
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2868838183
Short name T212
Test name
Test status
Simulation time 156286156363 ps
CPU time 65.01 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:50:38 PM PDT 24
Peak memory 183216 kb
Host smart-63fa133c-0dd0-44bb-8038-6ea9d073d122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868838183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2868838183
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3746648384
Short name T42
Test name
Test status
Simulation time 83718095200 ps
CPU time 143.89 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:51:54 PM PDT 24
Peak memory 198172 kb
Host smart-ba1d7753-a521-4bed-88c7-9f539b04b697
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746648384 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3746648384
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2516452125
Short name T43
Test name
Test status
Simulation time 466226207 ps
CPU time 0.9 seconds
Started Apr 21 12:49:46 PM PDT 24
Finished Apr 21 12:49:47 PM PDT 24
Peak memory 183324 kb
Host smart-dcc4b229-b012-4432-9f76-2b4242524969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516452125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2516452125
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1886153000
Short name T125
Test name
Test status
Simulation time 1556767492 ps
CPU time 1.03 seconds
Started Apr 21 12:49:42 PM PDT 24
Finished Apr 21 12:49:44 PM PDT 24
Peak memory 183200 kb
Host smart-3752e9e0-3a8b-4713-8df5-a70f0bab651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886153000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1886153000
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2076954403
Short name T232
Test name
Test status
Simulation time 342409335 ps
CPU time 0.83 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:39 PM PDT 24
Peak memory 183248 kb
Host smart-c539566e-f1c4-4c03-bc44-c6e5e27f90f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076954403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2076954403
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.214263337
Short name T134
Test name
Test status
Simulation time 279794020324 ps
CPU time 383.73 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:56:25 PM PDT 24
Peak memory 193032 kb
Host smart-774da3e4-157e-4f05-a06e-a79a51262205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214263337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.214263337
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.673056737
Short name T172
Test name
Test status
Simulation time 161298933827 ps
CPU time 187.02 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:52:34 PM PDT 24
Peak memory 198236 kb
Host smart-4fa8b268-f685-40fd-9a4c-1625b8ac8de9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673056737 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.673056737
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2098838665
Short name T140
Test name
Test status
Simulation time 423186766 ps
CPU time 1.26 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:49:41 PM PDT 24
Peak memory 183304 kb
Host smart-0aad17fe-80e5-46f8-87d0-e2a6fc52278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098838665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2098838665
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.933662675
Short name T279
Test name
Test status
Simulation time 55086478382 ps
CPU time 46 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 183356 kb
Host smart-63576708-2c40-4a0c-96cf-2199baf9a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933662675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.933662675
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1450354889
Short name T253
Test name
Test status
Simulation time 429166327 ps
CPU time 1.2 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 12:49:36 PM PDT 24
Peak memory 183276 kb
Host smart-9efa85fb-aef6-43bd-93d5-a431f041d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450354889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1450354889
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.4137588440
Short name T62
Test name
Test status
Simulation time 224567348762 ps
CPU time 178.11 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:52:35 PM PDT 24
Peak memory 194092 kb
Host smart-36411fa1-1bb4-4a4f-b58d-cf4520a6c20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137588440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.4137588440
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1101851232
Short name T272
Test name
Test status
Simulation time 10488595084 ps
CPU time 103.68 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 198284 kb
Host smart-30bbf4c0-50cd-44c0-add2-6848ab04aa1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101851232 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1101851232
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1842807392
Short name T29
Test name
Test status
Simulation time 560723601 ps
CPU time 1.32 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:49:37 PM PDT 24
Peak memory 183304 kb
Host smart-87864836-47ce-4473-a665-5fc18c82b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842807392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1842807392
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1176260517
Short name T170
Test name
Test status
Simulation time 13493131601 ps
CPU time 18.83 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 183364 kb
Host smart-dc028371-6f30-4b6d-8f0a-849428860cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176260517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1176260517
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.891211289
Short name T264
Test name
Test status
Simulation time 574218292 ps
CPU time 1.27 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 12:49:29 PM PDT 24
Peak memory 183268 kb
Host smart-8a912f7e-3185-4490-be29-79931a31525f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891211289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.891211289
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3908082938
Short name T195
Test name
Test status
Simulation time 317236835323 ps
CPU time 477.15 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:57:34 PM PDT 24
Peak memory 195272 kb
Host smart-1f13e0f0-a59f-4dca-b3b0-91d494052800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908082938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3908082938
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1017365559
Short name T67
Test name
Test status
Simulation time 309640393293 ps
CPU time 600.45 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:59:57 PM PDT 24
Peak memory 199096 kb
Host smart-3ddcb9d5-f0b5-4f22-bd8b-91659e318d7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017365559 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1017365559
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.3376661807
Short name T261
Test name
Test status
Simulation time 399722355 ps
CPU time 0.87 seconds
Started Apr 21 12:49:43 PM PDT 24
Finished Apr 21 12:49:44 PM PDT 24
Peak memory 183212 kb
Host smart-1e7933aa-5f8e-45be-9013-028b115e5a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376661807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.3376661807
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3634704260
Short name T229
Test name
Test status
Simulation time 40224800486 ps
CPU time 59.13 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:50:38 PM PDT 24
Peak memory 183368 kb
Host smart-fd273f91-679a-41cd-b16d-65d2f8ce9fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634704260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3634704260
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.483782846
Short name T210
Test name
Test status
Simulation time 462609314 ps
CPU time 0.6 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:49:36 PM PDT 24
Peak memory 183300 kb
Host smart-b47982f8-0543-4046-a116-b9c052aec88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483782846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.483782846
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3004313736
Short name T8
Test name
Test status
Simulation time 213178089061 ps
CPU time 320 seconds
Started Apr 21 12:49:31 PM PDT 24
Finished Apr 21 12:54:52 PM PDT 24
Peak memory 194136 kb
Host smart-ba6e5631-7127-471e-9439-58e07c55fdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004313736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3004313736
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.897298209
Short name T110
Test name
Test status
Simulation time 79751909575 ps
CPU time 228.04 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:53:44 PM PDT 24
Peak memory 198324 kb
Host smart-0df61992-bee3-4b1d-8b7c-78f007496d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897298209 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.897298209
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.507970551
Short name T256
Test name
Test status
Simulation time 577285195 ps
CPU time 0.75 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 183316 kb
Host smart-deda8256-a8fd-49ec-9f74-38bdfd60570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507970551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.507970551
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2229082222
Short name T187
Test name
Test status
Simulation time 47928204325 ps
CPU time 71.76 seconds
Started Apr 21 12:49:40 PM PDT 24
Finished Apr 21 12:50:52 PM PDT 24
Peak memory 183364 kb
Host smart-8c862dc1-dba2-491e-a9dd-acd4ed734a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229082222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2229082222
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.539905533
Short name T231
Test name
Test status
Simulation time 412539856 ps
CPU time 0.68 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:49:46 PM PDT 24
Peak memory 183180 kb
Host smart-a89dca76-8923-4438-ae0c-eeadcf00c947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539905533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.539905533
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3343669390
Short name T66
Test name
Test status
Simulation time 12027908265 ps
CPU time 6.47 seconds
Started Apr 21 12:49:28 PM PDT 24
Finished Apr 21 12:49:35 PM PDT 24
Peak memory 194544 kb
Host smart-5ce2e70d-40a5-49e9-b1c4-5fbe62b9ab73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343669390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3343669390
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2185745270
Short name T85
Test name
Test status
Simulation time 437095875854 ps
CPU time 280.83 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:54:40 PM PDT 24
Peak memory 198224 kb
Host smart-59a1a8e9-0e6f-45e0-a82d-260f2a40d41d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185745270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2185745270
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3792706780
Short name T99
Test name
Test status
Simulation time 632184988 ps
CPU time 0.6 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 183248 kb
Host smart-e659bdc6-bfd1-4494-81ef-5089d49a0889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792706780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3792706780
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2892415095
Short name T139
Test name
Test status
Simulation time 52232149209 ps
CPU time 37.92 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 183364 kb
Host smart-e59187f6-7ba8-45f4-b6ca-09f2b53298c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892415095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2892415095
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2365008433
Short name T283
Test name
Test status
Simulation time 373498668 ps
CPU time 0.67 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183284 kb
Host smart-19943d1c-3b6b-4a24-8620-8eb3827d1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365008433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2365008433
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1533151673
Short name T138
Test name
Test status
Simulation time 51786033112 ps
CPU time 22.21 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:50:12 PM PDT 24
Peak memory 183364 kb
Host smart-48cb4a57-85b8-4c7e-a729-70ebe13df7a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533151673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1533151673
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2660509068
Short name T21
Test name
Test status
Simulation time 134018682834 ps
CPU time 366.6 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 198236 kb
Host smart-bf80a90f-190f-407d-9f43-448ad663179e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660509068 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2660509068
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.476362307
Short name T104
Test name
Test status
Simulation time 458336275 ps
CPU time 0.66 seconds
Started Apr 21 12:49:42 PM PDT 24
Finished Apr 21 12:49:43 PM PDT 24
Peak memory 183272 kb
Host smart-368d315b-2486-4809-a588-fdb2f38b43f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476362307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.476362307
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.107760644
Short name T159
Test name
Test status
Simulation time 15702923316 ps
CPU time 6.64 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183280 kb
Host smart-1e61bf75-f268-41eb-8095-fa2be8d8c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107760644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.107760644
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1343391439
Short name T102
Test name
Test status
Simulation time 449109546 ps
CPU time 1.17 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183300 kb
Host smart-4c70f512-ea35-4bb7-869b-a5959620da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343391439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1343391439
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.428680033
Short name T168
Test name
Test status
Simulation time 80909906509 ps
CPU time 31.95 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:50:22 PM PDT 24
Peak memory 183292 kb
Host smart-343046c9-9a2b-4215-8d66-2bf3c9004ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428680033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.428680033
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.131739877
Short name T82
Test name
Test status
Simulation time 280635577038 ps
CPU time 485.05 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:57:43 PM PDT 24
Peak memory 206500 kb
Host smart-82caad25-ed54-44cf-ac04-54e4c8100159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131739877 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.131739877
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1587065153
Short name T164
Test name
Test status
Simulation time 399760654 ps
CPU time 1.21 seconds
Started Apr 21 12:49:21 PM PDT 24
Finished Apr 21 12:49:23 PM PDT 24
Peak memory 183276 kb
Host smart-3470c02c-31a0-4317-a7c7-db1016810453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587065153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1587065153
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2666552699
Short name T25
Test name
Test status
Simulation time 50610359276 ps
CPU time 35.83 seconds
Started Apr 21 12:49:19 PM PDT 24
Finished Apr 21 12:49:56 PM PDT 24
Peak memory 183356 kb
Host smart-4765f322-e5b0-40c6-b6f9-0c1ebeb797d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666552699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2666552699
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3478486480
Short name T19
Test name
Test status
Simulation time 7912317789 ps
CPU time 12.94 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:49:48 PM PDT 24
Peak memory 215432 kb
Host smart-3807e3c2-1041-42ce-9a4b-2939300a7321
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478486480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3478486480
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1056585764
Short name T124
Test name
Test status
Simulation time 388868112 ps
CPU time 1.15 seconds
Started Apr 21 12:49:20 PM PDT 24
Finished Apr 21 12:49:21 PM PDT 24
Peak memory 183184 kb
Host smart-d7a125e3-c525-4c45-8245-0a34520f9809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056585764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1056585764
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2622516945
Short name T166
Test name
Test status
Simulation time 76936372013 ps
CPU time 114 seconds
Started Apr 21 12:49:17 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 193848 kb
Host smart-4f6a9905-b2d1-4299-840f-b9eee577f8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622516945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2622516945
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3704009772
Short name T222
Test name
Test status
Simulation time 102212694966 ps
CPU time 805.12 seconds
Started Apr 21 12:49:30 PM PDT 24
Finished Apr 21 01:02:56 PM PDT 24
Peak memory 206404 kb
Host smart-3a61d8d3-beae-4642-9c29-82e920737544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704009772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3704009772
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4040273902
Short name T30
Test name
Test status
Simulation time 516298582 ps
CPU time 0.78 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183240 kb
Host smart-72119d89-3e41-40fb-9b31-66656fbe430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040273902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4040273902
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3208599941
Short name T27
Test name
Test status
Simulation time 22031999395 ps
CPU time 32.82 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 183284 kb
Host smart-0ee34dfc-1ee3-4081-b110-a069b398472a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208599941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3208599941
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3455845579
Short name T6
Test name
Test status
Simulation time 551328641 ps
CPU time 1.38 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183292 kb
Host smart-f4557162-61f4-40dd-8ac6-c8df539288f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455845579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3455845579
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3221017752
Short name T213
Test name
Test status
Simulation time 259447920281 ps
CPU time 45.95 seconds
Started Apr 21 12:49:41 PM PDT 24
Finished Apr 21 12:50:27 PM PDT 24
Peak memory 183300 kb
Host smart-f7ce7bac-da05-4654-b2eb-09e9af3df678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221017752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3221017752
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2040290529
Short name T260
Test name
Test status
Simulation time 171428644184 ps
CPU time 451.61 seconds
Started Apr 21 12:49:41 PM PDT 24
Finished Apr 21 12:57:13 PM PDT 24
Peak memory 198184 kb
Host smart-8d7cf376-d5db-434d-b5e5-5112cd4061a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040290529 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2040290529
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1943079823
Short name T197
Test name
Test status
Simulation time 658225336 ps
CPU time 0.69 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 183300 kb
Host smart-a75be9e1-b655-4e82-acd4-1b478c7d2657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943079823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1943079823
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1526201150
Short name T277
Test name
Test status
Simulation time 27725345521 ps
CPU time 40.51 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:50:31 PM PDT 24
Peak memory 183368 kb
Host smart-95c59df0-8077-40ef-bbfe-e478c085f2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526201150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1526201150
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1344609923
Short name T131
Test name
Test status
Simulation time 457085467 ps
CPU time 1.18 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:01 PM PDT 24
Peak memory 183276 kb
Host smart-f7475320-9650-4563-a6a6-c4cf216217d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344609923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1344609923
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1274429489
Short name T250
Test name
Test status
Simulation time 147932141512 ps
CPU time 61.94 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:50:41 PM PDT 24
Peak memory 194772 kb
Host smart-cbf4d20a-82d0-42ed-9c4f-49244e6fa8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274429489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1274429489
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.807905981
Short name T271
Test name
Test status
Simulation time 181512819730 ps
CPU time 387.68 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 198280 kb
Host smart-0466dd25-100b-4639-a02f-0b57fd91b3a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807905981 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.807905981
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4272200036
Short name T26
Test name
Test status
Simulation time 469553459 ps
CPU time 0.69 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183244 kb
Host smart-dfa50c5a-cecc-48cd-a9ad-bdac9587c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272200036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4272200036
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2290668733
Short name T214
Test name
Test status
Simulation time 3307042584 ps
CPU time 1.46 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183344 kb
Host smart-5492e7d9-7b94-4197-baab-8f26e650a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290668733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2290668733
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2898761187
Short name T183
Test name
Test status
Simulation time 425876540 ps
CPU time 0.65 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:49:41 PM PDT 24
Peak memory 183264 kb
Host smart-7980d61f-3bf1-4718-914f-0dd301153e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898761187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2898761187
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.905460696
Short name T227
Test name
Test status
Simulation time 20137131778 ps
CPU time 8.83 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:49:42 PM PDT 24
Peak memory 194116 kb
Host smart-a6f7d9df-264f-474d-86bb-38cc3f78aed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905460696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.905460696
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4213387500
Short name T242
Test name
Test status
Simulation time 91685300320 ps
CPU time 438.87 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:57:11 PM PDT 24
Peak memory 198240 kb
Host smart-590058c0-51b0-4aa3-a791-d9ad2bc12cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213387500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4213387500
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2635688074
Short name T5
Test name
Test status
Simulation time 372887754 ps
CPU time 1.11 seconds
Started Apr 21 12:49:43 PM PDT 24
Finished Apr 21 12:49:44 PM PDT 24
Peak memory 183236 kb
Host smart-ec7adbf6-3fb4-4fac-b0a3-6efffa5edaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635688074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2635688074
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.369947687
Short name T113
Test name
Test status
Simulation time 15953075345 ps
CPU time 6.81 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183360 kb
Host smart-f8598ec2-9fcd-4cfd-8fc3-29ac4b30fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369947687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.369947687
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3060524932
Short name T239
Test name
Test status
Simulation time 554123912 ps
CPU time 1.28 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:49:47 PM PDT 24
Peak memory 183192 kb
Host smart-c533f313-3540-4852-8aaa-66e34d284a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060524932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3060524932
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.117378026
Short name T117
Test name
Test status
Simulation time 151349147841 ps
CPU time 60.69 seconds
Started Apr 21 12:49:35 PM PDT 24
Finished Apr 21 12:50:36 PM PDT 24
Peak memory 183372 kb
Host smart-0c641111-90d5-417e-8389-5be4c743bd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117378026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.117378026
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1062537357
Short name T86
Test name
Test status
Simulation time 47254688268 ps
CPU time 98.06 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 198340 kb
Host smart-d5435ccc-ff82-4726-81b2-ccafcc7382a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062537357 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1062537357
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1256770034
Short name T132
Test name
Test status
Simulation time 500299492 ps
CPU time 0.8 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183284 kb
Host smart-f7203d94-f883-440f-95df-a1d2b93a4830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256770034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1256770034
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1234012708
Short name T268
Test name
Test status
Simulation time 31345958890 ps
CPU time 50.52 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:50:43 PM PDT 24
Peak memory 183280 kb
Host smart-d5037c68-3de0-4f3e-aa7f-92d5f2978927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234012708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1234012708
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2325436208
Short name T276
Test name
Test status
Simulation time 356937739 ps
CPU time 1.12 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:49:50 PM PDT 24
Peak memory 183212 kb
Host smart-410b352e-7ae2-4d91-be9d-354335f8983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325436208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2325436208
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.570533062
Short name T240
Test name
Test status
Simulation time 343944074258 ps
CPU time 561.6 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:59:07 PM PDT 24
Peak memory 195084 kb
Host smart-a56b96a3-f12a-4592-a632-d4e72c9fba64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570533062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.570533062
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1903937110
Short name T88
Test name
Test status
Simulation time 235022850550 ps
CPU time 444.53 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:57:19 PM PDT 24
Peak memory 198152 kb
Host smart-df0e9950-c596-461d-a64c-e09b72237658
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903937110 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1903937110
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2182239933
Short name T255
Test name
Test status
Simulation time 518654224 ps
CPU time 0.75 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:58 PM PDT 24
Peak memory 183280 kb
Host smart-908f6cfe-42c1-42be-9626-abcf939cfb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182239933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2182239933
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.763512300
Short name T234
Test name
Test status
Simulation time 41092867936 ps
CPU time 14.17 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 183364 kb
Host smart-6c18f986-5089-4be8-a160-8b4bd2594921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763512300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.763512300
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3391584550
Short name T245
Test name
Test status
Simulation time 401286026 ps
CPU time 1.19 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:49:46 PM PDT 24
Peak memory 183264 kb
Host smart-c2cfa1da-e87e-409d-b516-6aead587d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391584550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3391584550
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3147763189
Short name T258
Test name
Test status
Simulation time 74461850594 ps
CPU time 14.5 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 183288 kb
Host smart-3f28dcab-6264-4bc2-b632-04cae838face
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147763189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3147763189
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.687633340
Short name T218
Test name
Test status
Simulation time 47945400901 ps
CPU time 402.6 seconds
Started Apr 21 12:50:10 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 198168 kb
Host smart-621b9b96-d035-422a-915d-74e38b2ffd71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687633340 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.687633340
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3384579318
Short name T194
Test name
Test status
Simulation time 452885191 ps
CPU time 0.98 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:49:48 PM PDT 24
Peak memory 183288 kb
Host smart-8e1e0e5c-eb6a-4af8-8be2-ca2ef326dc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384579318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3384579318
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2635335159
Short name T14
Test name
Test status
Simulation time 2932136958 ps
CPU time 1.3 seconds
Started Apr 21 12:50:02 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 183356 kb
Host smart-96d64856-1661-438c-989a-768faf11b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635335159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2635335159
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4242037212
Short name T185
Test name
Test status
Simulation time 464197335 ps
CPU time 1.19 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183188 kb
Host smart-ec33146f-4431-4c27-a1f2-faa211823e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242037212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4242037212
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2018678046
Short name T262
Test name
Test status
Simulation time 115632209582 ps
CPU time 173.94 seconds
Started Apr 21 12:49:40 PM PDT 24
Finished Apr 21 12:52:34 PM PDT 24
Peak memory 194760 kb
Host smart-d161eabf-5f48-4b5c-962b-6c20383307dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018678046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2018678046
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.146629171
Short name T35
Test name
Test status
Simulation time 205716910026 ps
CPU time 422.21 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:56:54 PM PDT 24
Peak memory 198264 kb
Host smart-46c69e57-1e57-4d97-bf79-af25107a9a95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146629171 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.146629171
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2139216153
Short name T108
Test name
Test status
Simulation time 622857771 ps
CPU time 0.8 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:50:01 PM PDT 24
Peak memory 183312 kb
Host smart-1eb3eba7-08ed-49d1-95e2-53d3e3db08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139216153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2139216153
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2085290956
Short name T282
Test name
Test status
Simulation time 5018091828 ps
CPU time 5.85 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:49:39 PM PDT 24
Peak memory 183364 kb
Host smart-aaed2a24-3afb-40c9-bb4c-eb7b2c40788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085290956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2085290956
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.4108195844
Short name T270
Test name
Test status
Simulation time 573360193 ps
CPU time 1.44 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 183268 kb
Host smart-095a5d83-1565-4bfc-a83c-0bab9ae189f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108195844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.4108195844
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1761924745
Short name T269
Test name
Test status
Simulation time 77361304263 ps
CPU time 332.86 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 198336 kb
Host smart-e25e2b69-afaa-43e2-aea8-2eb3a4d528e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761924745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1761924745
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.441606569
Short name T203
Test name
Test status
Simulation time 451981174 ps
CPU time 0.68 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183296 kb
Host smart-5912b82e-4d91-4ded-9d72-7b43cd647d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441606569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.441606569
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2264107061
Short name T191
Test name
Test status
Simulation time 53912456275 ps
CPU time 79.64 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 183356 kb
Host smart-99fec715-f4f1-443c-88bf-4c7015a0a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264107061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2264107061
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1197197393
Short name T244
Test name
Test status
Simulation time 498005046 ps
CPU time 0.78 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 183280 kb
Host smart-75aa36aa-d32b-41cd-8150-b69140fdc17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197197393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1197197393
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3934649573
Short name T149
Test name
Test status
Simulation time 139784936121 ps
CPU time 214.6 seconds
Started Apr 21 12:49:43 PM PDT 24
Finished Apr 21 12:53:18 PM PDT 24
Peak memory 193736 kb
Host smart-8fddbec0-8d8f-42b5-9eb7-291c731b3e98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934649573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3934649573
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2594218423
Short name T176
Test name
Test status
Simulation time 104503543002 ps
CPU time 193.56 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:53:04 PM PDT 24
Peak memory 198284 kb
Host smart-ef55a0ce-ec7c-4f71-b20c-9efda7a9edf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594218423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2594218423
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.956309848
Short name T3
Test name
Test status
Simulation time 369822381 ps
CPU time 1.08 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183316 kb
Host smart-7fcd6ea3-86f6-406f-921a-fbdf6f8213da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956309848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.956309848
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3996650691
Short name T142
Test name
Test status
Simulation time 36811180706 ps
CPU time 31.34 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:50:24 PM PDT 24
Peak memory 183372 kb
Host smart-b6492cee-f459-40e9-bffb-4650f2e46144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996650691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3996650691
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2565894988
Short name T204
Test name
Test status
Simulation time 510048702 ps
CPU time 0.7 seconds
Started Apr 21 12:49:40 PM PDT 24
Finished Apr 21 12:49:41 PM PDT 24
Peak memory 183292 kb
Host smart-aeb29b74-790e-45d7-b508-0e9521f9f58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565894988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2565894988
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3494548770
Short name T15
Test name
Test status
Simulation time 398230621016 ps
CPU time 630.95 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 01:00:27 PM PDT 24
Peak memory 194836 kb
Host smart-2f3456fd-23af-4848-b6ba-f235542dd429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494548770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3494548770
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2126187328
Short name T157
Test name
Test status
Simulation time 66885257502 ps
CPU time 562.66 seconds
Started Apr 21 12:49:42 PM PDT 24
Finished Apr 21 12:59:05 PM PDT 24
Peak memory 198316 kb
Host smart-82af5a92-b7a0-412e-946a-3342612352c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126187328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2126187328
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.473397517
Short name T65
Test name
Test status
Simulation time 381939327 ps
CPU time 0.88 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:49:35 PM PDT 24
Peak memory 183312 kb
Host smart-0657fd69-29d0-44fe-a15d-d855548d589e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473397517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.473397517
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1938966186
Short name T228
Test name
Test status
Simulation time 37678491618 ps
CPU time 62.68 seconds
Started Apr 21 12:49:24 PM PDT 24
Finished Apr 21 12:50:27 PM PDT 24
Peak memory 183308 kb
Host smart-6fe45e63-3175-49cb-a0bb-6e25131dc1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938966186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1938966186
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3878039483
Short name T20
Test name
Test status
Simulation time 8133438252 ps
CPU time 6.97 seconds
Started Apr 21 12:49:24 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 215216 kb
Host smart-0b334194-a6da-4ad4-9a28-797957d4459b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878039483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3878039483
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2767537419
Short name T248
Test name
Test status
Simulation time 524918080 ps
CPU time 0.75 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 183288 kb
Host smart-34f3cd1e-c46d-4735-802b-ca987ef84c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767537419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2767537419
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1630397015
Short name T189
Test name
Test status
Simulation time 774530195252 ps
CPU time 143.31 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:51:57 PM PDT 24
Peak memory 183496 kb
Host smart-e67ff8e2-57d0-4586-a479-e5ed58af634d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630397015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1630397015
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2510275208
Short name T4
Test name
Test status
Simulation time 26338683822 ps
CPU time 169.96 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:52:23 PM PDT 24
Peak memory 198144 kb
Host smart-b67bb0be-9713-4f78-988f-ecc1a13839eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510275208 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2510275208
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1874482258
Short name T217
Test name
Test status
Simulation time 654798361 ps
CPU time 0.58 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:53 PM PDT 24
Peak memory 183184 kb
Host smart-c4f96582-0a02-4fd9-b134-acc44c4da3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874482258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1874482258
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3529808633
Short name T235
Test name
Test status
Simulation time 47353948772 ps
CPU time 36.89 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:50:34 PM PDT 24
Peak memory 183348 kb
Host smart-fc4e28c7-d755-44e4-bac7-a63ae3d31191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529808633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3529808633
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1970742749
Short name T215
Test name
Test status
Simulation time 374167213 ps
CPU time 0.67 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183296 kb
Host smart-02c56931-be15-4328-a2e9-e75dd7222a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970742749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1970742749
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2612686977
Short name T254
Test name
Test status
Simulation time 164032140727 ps
CPU time 67.19 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:51:05 PM PDT 24
Peak memory 195076 kb
Host smart-e3cc2367-1936-43eb-9861-8ac7b5b25945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612686977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2612686977
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3254179453
Short name T12
Test name
Test status
Simulation time 14796100498 ps
CPU time 113.44 seconds
Started Apr 21 12:49:43 PM PDT 24
Finished Apr 21 12:51:37 PM PDT 24
Peak memory 198332 kb
Host smart-bfcd1cbc-335f-4d5e-8322-a8fc53214760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254179453 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3254179453
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.696310774
Short name T224
Test name
Test status
Simulation time 456799014 ps
CPU time 0.87 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:49:59 PM PDT 24
Peak memory 183284 kb
Host smart-911084ac-35cc-4d49-aa1f-3f9aefbb46e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696310774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.696310774
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3090517387
Short name T46
Test name
Test status
Simulation time 3355669435 ps
CPU time 5.27 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:49:56 PM PDT 24
Peak memory 183328 kb
Host smart-90f8e426-2f80-42da-acd1-f4e809a9371e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090517387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3090517387
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1768207816
Short name T123
Test name
Test status
Simulation time 444049667 ps
CPU time 0.68 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 183224 kb
Host smart-3d0fc6a4-7686-4e74-b806-c005fc51e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768207816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1768207816
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.4294825022
Short name T9
Test name
Test status
Simulation time 202038654832 ps
CPU time 292.51 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:54:46 PM PDT 24
Peak memory 183312 kb
Host smart-e4fe5600-23ff-450a-9063-b0e23d75c9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294825022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.4294825022
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3709091500
Short name T40
Test name
Test status
Simulation time 382994455829 ps
CPU time 397.39 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 198336 kb
Host smart-c14ea0ca-bcaa-4c59-99d6-17d263242ac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709091500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3709091500
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2018065596
Short name T69
Test name
Test status
Simulation time 415920265 ps
CPU time 0.84 seconds
Started Apr 21 12:50:06 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 183216 kb
Host smart-c86487b0-dc7f-4926-b067-bf546f48f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018065596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2018065596
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.105058130
Short name T280
Test name
Test status
Simulation time 2750874810 ps
CPU time 0.96 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:49:58 PM PDT 24
Peak memory 183256 kb
Host smart-dbcf533b-2c0d-49ec-9fdb-4275cc07ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105058130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.105058130
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1393165888
Short name T161
Test name
Test status
Simulation time 404298960 ps
CPU time 0.61 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183204 kb
Host smart-979f8d36-47d2-4433-bfaf-32eba6e8e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393165888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1393165888
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.305590762
Short name T223
Test name
Test status
Simulation time 139081310319 ps
CPU time 48.92 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:50:47 PM PDT 24
Peak memory 183488 kb
Host smart-ecc698ee-cccc-4b12-92ed-33a5828b93db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305590762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.305590762
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3039042953
Short name T97
Test name
Test status
Simulation time 601693901 ps
CPU time 1.1 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183232 kb
Host smart-632d02d0-1af5-4046-b767-ab83c026a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039042953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3039042953
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1249299324
Short name T216
Test name
Test status
Simulation time 43816390685 ps
CPU time 9.89 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 183328 kb
Host smart-f81d855c-130b-41e2-897f-f1afd03f300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249299324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1249299324
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3037665500
Short name T167
Test name
Test status
Simulation time 525292078 ps
CPU time 0.68 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183212 kb
Host smart-563e0222-9e8b-4803-9f1f-b63d9a45c61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037665500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3037665500
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2961528043
Short name T116
Test name
Test status
Simulation time 354247754017 ps
CPU time 110.75 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:51:40 PM PDT 24
Peak memory 192672 kb
Host smart-fbea90fc-c4e6-465c-b2fe-943b68ec09de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961528043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2961528043
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.271814546
Short name T83
Test name
Test status
Simulation time 37870611202 ps
CPU time 147.66 seconds
Started Apr 21 12:49:46 PM PDT 24
Finished Apr 21 12:52:14 PM PDT 24
Peak memory 198292 kb
Host smart-49a51961-5cf9-4cda-a998-56a8ef192c99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271814546 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.271814546
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1841535768
Short name T267
Test name
Test status
Simulation time 459285118 ps
CPU time 1.31 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183300 kb
Host smart-b247358f-9e5e-46c0-a089-971e2ff9e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841535768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1841535768
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3283904168
Short name T175
Test name
Test status
Simulation time 24299580754 ps
CPU time 9.92 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 183364 kb
Host smart-e9c5b4da-1b36-429b-9099-c2a5deaecf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283904168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3283904168
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4249039298
Short name T130
Test name
Test status
Simulation time 492055684 ps
CPU time 1.27 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:49:56 PM PDT 24
Peak memory 183132 kb
Host smart-289ab673-ce97-4263-9926-863731cc7a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249039298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4249039298
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3550656561
Short name T207
Test name
Test status
Simulation time 205398597219 ps
CPU time 246.3 seconds
Started Apr 21 12:49:38 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 193948 kb
Host smart-62a908b2-46e2-499f-9a12-ccea80a4c392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550656561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3550656561
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1868284670
Short name T201
Test name
Test status
Simulation time 12391318171 ps
CPU time 122.93 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:51:42 PM PDT 24
Peak memory 198228 kb
Host smart-dc4b9a8e-2bf7-48ef-b8bc-eca95b3e051e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868284670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1868284670
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2515857786
Short name T105
Test name
Test status
Simulation time 445431416 ps
CPU time 1.25 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:49:52 PM PDT 24
Peak memory 183248 kb
Host smart-6bb70060-30dc-44a3-a746-40daa854ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515857786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2515857786
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.920707956
Short name T144
Test name
Test status
Simulation time 35049395414 ps
CPU time 46.88 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:48 PM PDT 24
Peak memory 183352 kb
Host smart-d026dd90-5a83-4396-88b9-7953fb2b9c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920707956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.920707956
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1963769681
Short name T198
Test name
Test status
Simulation time 572675881 ps
CPU time 1.42 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:49:49 PM PDT 24
Peak memory 183280 kb
Host smart-c4a8efd6-1f12-4762-8973-2277d78c65a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963769681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1963769681
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2259335682
Short name T266
Test name
Test status
Simulation time 144083155739 ps
CPU time 117.82 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:51:50 PM PDT 24
Peak memory 183364 kb
Host smart-5d24ac2b-3cc5-4b31-a950-2d7792e95b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259335682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2259335682
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1729693571
Short name T259
Test name
Test status
Simulation time 921902910917 ps
CPU time 434.11 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:57:07 PM PDT 24
Peak memory 198304 kb
Host smart-0d2f50c2-c887-4981-a467-78ac1e412eed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729693571 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1729693571
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1177711256
Short name T119
Test name
Test status
Simulation time 596540896 ps
CPU time 0.77 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:53 PM PDT 24
Peak memory 183296 kb
Host smart-2c6775d4-a8f4-498b-851a-543ffe222f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177711256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1177711256
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.80694717
Short name T219
Test name
Test status
Simulation time 16780099753 ps
CPU time 28.68 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:29 PM PDT 24
Peak memory 183308 kb
Host smart-8310c49b-0b70-4b7b-a226-c53f766bdeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80694717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.80694717
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.88466052
Short name T96
Test name
Test status
Simulation time 546388327 ps
CPU time 1.38 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:49:59 PM PDT 24
Peak memory 183272 kb
Host smart-5b5188a0-113f-4987-88d7-e460d46c2e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88466052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.88466052
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3961712423
Short name T127
Test name
Test status
Simulation time 602151891538 ps
CPU time 176.24 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:52:53 PM PDT 24
Peak memory 193700 kb
Host smart-0262acd2-5e40-4782-a2ae-ad40ef8c1e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961712423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3961712423
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.2985413441
Short name T133
Test name
Test status
Simulation time 44773149403 ps
CPU time 492.23 seconds
Started Apr 21 12:49:47 PM PDT 24
Finished Apr 21 12:58:00 PM PDT 24
Peak memory 198292 kb
Host smart-b8ae2520-b46a-4bf3-95e5-f8a720dc9405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985413441 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.2985413441
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.2494321717
Short name T178
Test name
Test status
Simulation time 476215150 ps
CPU time 1.39 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 183304 kb
Host smart-80e59ead-353e-4feb-b032-bdee87cbc1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494321717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.2494321717
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3722047905
Short name T115
Test name
Test status
Simulation time 31394945959 ps
CPU time 13.22 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 183320 kb
Host smart-610c6d7c-c9d5-472a-8c42-f2181ddfb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722047905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3722047905
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1045252436
Short name T63
Test name
Test status
Simulation time 554041264 ps
CPU time 1.27 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 183296 kb
Host smart-6eb312c5-0517-4814-97ee-a94b31fef779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045252436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1045252436
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2592263110
Short name T106
Test name
Test status
Simulation time 337090677209 ps
CPU time 207.57 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:53:35 PM PDT 24
Peak memory 198220 kb
Host smart-f71fc467-dddc-4e7f-b238-d559bfdda13a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592263110 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2592263110
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1788668445
Short name T179
Test name
Test status
Simulation time 421144498 ps
CPU time 0.69 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 183316 kb
Host smart-8e9e6dfc-839c-41cb-be1f-5ce000d9cc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788668445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1788668445
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3062846118
Short name T45
Test name
Test status
Simulation time 57253776554 ps
CPU time 83.13 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:51:20 PM PDT 24
Peak memory 183552 kb
Host smart-33334449-8625-4890-9a01-a6bd26168b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062846118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3062846118
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3522902654
Short name T181
Test name
Test status
Simulation time 400930846 ps
CPU time 0.86 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:01 PM PDT 24
Peak memory 183292 kb
Host smart-80c35907-7c95-48a0-8855-db6b9fdc39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522902654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3522902654
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1102160206
Short name T263
Test name
Test status
Simulation time 193989830633 ps
CPU time 78.76 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:51:10 PM PDT 24
Peak memory 183360 kb
Host smart-02a1878a-9160-4788-b98a-98bd4d9005e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102160206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1102160206
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3926437244
Short name T79
Test name
Test status
Simulation time 88521609428 ps
CPU time 171.19 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:52:50 PM PDT 24
Peak memory 198232 kb
Host smart-0482268e-d771-4645-a5a3-9a54903dbae4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926437244 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3926437244
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2637161363
Short name T233
Test name
Test status
Simulation time 500799682 ps
CPU time 0.83 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:51 PM PDT 24
Peak memory 183264 kb
Host smart-ac7a9a0e-9020-4727-be72-e62cc295bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637161363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2637161363
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1518406470
Short name T190
Test name
Test status
Simulation time 5181435168 ps
CPU time 7.65 seconds
Started Apr 21 12:49:49 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 183352 kb
Host smart-49480700-a482-42d7-9f16-5e792872e476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518406470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1518406470
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2847690333
Short name T182
Test name
Test status
Simulation time 607828430 ps
CPU time 0.7 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183216 kb
Host smart-76eda257-2424-41b8-8341-eabaa525358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847690333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2847690333
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2714104020
Short name T236
Test name
Test status
Simulation time 77979034725 ps
CPU time 117.53 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:51:56 PM PDT 24
Peak memory 193856 kb
Host smart-2b97a116-277a-4e6e-88c5-8205acca0737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714104020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2714104020
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3179807358
Short name T81
Test name
Test status
Simulation time 88276350153 ps
CPU time 747.15 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 01:02:22 PM PDT 24
Peak memory 200496 kb
Host smart-8862a283-42cc-4327-b72b-f5621b6a7710
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179807358 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3179807358
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2286586917
Short name T68
Test name
Test status
Simulation time 457358413 ps
CPU time 1.22 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183220 kb
Host smart-0f6fa15a-76cf-4332-bf8e-b8c11c0deffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286586917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2286586917
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.822681952
Short name T220
Test name
Test status
Simulation time 13785983176 ps
CPU time 5.5 seconds
Started Apr 21 12:49:37 PM PDT 24
Finished Apr 21 12:49:43 PM PDT 24
Peak memory 183352 kb
Host smart-cae9f5a9-4ee8-492a-b8be-b5f5a8f85644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822681952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.822681952
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.769103319
Short name T18
Test name
Test status
Simulation time 8561350581 ps
CPU time 2.39 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:49:42 PM PDT 24
Peak memory 215192 kb
Host smart-107e4dc5-0f93-40ed-ac24-ee43fcc548cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769103319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.769103319
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3479378117
Short name T154
Test name
Test status
Simulation time 447248297 ps
CPU time 0.7 seconds
Started Apr 21 12:49:28 PM PDT 24
Finished Apr 21 12:49:29 PM PDT 24
Peak memory 183292 kb
Host smart-0f5a026f-e79b-48fa-a482-901f8bd6a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479378117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3479378117
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4057457276
Short name T80
Test name
Test status
Simulation time 128504927646 ps
CPU time 701.02 seconds
Started Apr 21 12:49:27 PM PDT 24
Finished Apr 21 01:01:09 PM PDT 24
Peak memory 200592 kb
Host smart-ae431837-fbc2-4603-a550-f9aae27b36b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057457276 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4057457276
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.700844457
Short name T163
Test name
Test status
Simulation time 459151564 ps
CPU time 0.73 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 183300 kb
Host smart-ef9ab3df-624e-4fe2-81b3-c591b2ebfde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700844457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.700844457
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1761539097
Short name T177
Test name
Test status
Simulation time 60346610455 ps
CPU time 86.1 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 183340 kb
Host smart-6994dbe3-fd62-4dbd-97f9-2382247bbe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761539097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1761539097
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.626892429
Short name T186
Test name
Test status
Simulation time 446112416 ps
CPU time 0.72 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:53 PM PDT 24
Peak memory 183128 kb
Host smart-585bcbbf-d56b-41bd-a4f1-f7196ebdd07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626892429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.626892429
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1379561535
Short name T111
Test name
Test status
Simulation time 106853033446 ps
CPU time 38.21 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:43 PM PDT 24
Peak memory 183280 kb
Host smart-9adcfbe8-9e08-4eb1-8c80-6eb2cec3970d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379561535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1379561535
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3589558155
Short name T126
Test name
Test status
Simulation time 663314372464 ps
CPU time 305.61 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:55:11 PM PDT 24
Peak memory 198216 kb
Host smart-03d84440-90a2-47ec-bd7d-03b1f36b8095
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589558155 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3589558155
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.549972821
Short name T169
Test name
Test status
Simulation time 580986763 ps
CPU time 1.6 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 183304 kb
Host smart-90ec0315-e96a-4e15-835d-1f7910236eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549972821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.549972821
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1294582991
Short name T137
Test name
Test status
Simulation time 34171578032 ps
CPU time 41.22 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:50:38 PM PDT 24
Peak memory 183284 kb
Host smart-79524edf-5142-4107-8c23-28fbaf914f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294582991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1294582991
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3009855613
Short name T209
Test name
Test status
Simulation time 378127394 ps
CPU time 0.82 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:49:52 PM PDT 24
Peak memory 183132 kb
Host smart-bb60aadf-15c2-4534-89ba-a42638ee313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009855613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3009855613
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2028318370
Short name T147
Test name
Test status
Simulation time 40972434434 ps
CPU time 68.12 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 194568 kb
Host smart-f1f49506-a6a6-4054-9aa3-813c77164066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028318370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2028318370
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2532929822
Short name T87
Test name
Test status
Simulation time 994879868582 ps
CPU time 419.4 seconds
Started Apr 21 12:50:09 PM PDT 24
Finished Apr 21 12:57:10 PM PDT 24
Peak memory 198280 kb
Host smart-68a57ca6-28f5-44c4-a5ea-17e67f1f41a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532929822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2532929822
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.479963436
Short name T173
Test name
Test status
Simulation time 567299678 ps
CPU time 0.78 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:49:46 PM PDT 24
Peak memory 183280 kb
Host smart-52317434-e365-47f6-899c-d422b4c16b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479963436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.479963436
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.701791607
Short name T141
Test name
Test status
Simulation time 47806200834 ps
CPU time 68.76 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:51:03 PM PDT 24
Peak memory 183304 kb
Host smart-23097e45-1400-4713-99fa-6f08a3fb4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701791607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.701791607
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1330929
Short name T211
Test name
Test status
Simulation time 357726084 ps
CPU time 0.79 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 183304 kb
Host smart-e5a33b6a-afca-47c5-8f84-95f8950b13f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1330929
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3213311610
Short name T47
Test name
Test status
Simulation time 34554852978 ps
CPU time 39.12 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:50:32 PM PDT 24
Peak memory 193508 kb
Host smart-057a1002-1369-41d2-b546-fe204ca49161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213311610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3213311610
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2507819748
Short name T107
Test name
Test status
Simulation time 470931540 ps
CPU time 1.31 seconds
Started Apr 21 12:49:50 PM PDT 24
Finished Apr 21 12:49:52 PM PDT 24
Peak memory 183304 kb
Host smart-bf62a39e-6de4-4b85-8db4-039a881b29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507819748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2507819748
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.161916016
Short name T284
Test name
Test status
Simulation time 29574138137 ps
CPU time 24.27 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 183196 kb
Host smart-79dec080-44a3-46c6-80da-1afc9172ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161916016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.161916016
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1752097800
Short name T24
Test name
Test status
Simulation time 417581032 ps
CPU time 0.87 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 183208 kb
Host smart-db72a314-3c71-4cb3-9e09-4535699dd475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752097800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1752097800
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.611907136
Short name T122
Test name
Test status
Simulation time 250535688559 ps
CPU time 341.82 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 194632 kb
Host smart-21ca6791-b723-40c3-8681-da4a93a014e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611907136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.611907136
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1488507220
Short name T84
Test name
Test status
Simulation time 39069725445 ps
CPU time 299.57 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:55:01 PM PDT 24
Peak memory 198220 kb
Host smart-ceff4898-7138-4cb5-964e-1a43c8032551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488507220 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1488507220
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2123237757
Short name T160
Test name
Test status
Simulation time 530279798 ps
CPU time 0.77 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183228 kb
Host smart-ec4ef003-ccfb-4243-9fe2-4c3a653e87f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123237757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2123237757
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3014759401
Short name T2
Test name
Test status
Simulation time 14643631061 ps
CPU time 23.45 seconds
Started Apr 21 12:49:48 PM PDT 24
Finished Apr 21 12:50:12 PM PDT 24
Peak memory 183304 kb
Host smart-96068c93-77ca-4dc1-8be3-238f50a90586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014759401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3014759401
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2369218745
Short name T61
Test name
Test status
Simulation time 411700378 ps
CPU time 1.15 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 183244 kb
Host smart-bc815763-f5e5-4feb-896e-2aa787a562c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369218745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2369218745
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2822421715
Short name T143
Test name
Test status
Simulation time 213256339174 ps
CPU time 67.78 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:51:04 PM PDT 24
Peak memory 183356 kb
Host smart-03ae7538-9691-4752-a93f-5e033ee91c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822421715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2822421715
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3520070216
Short name T146
Test name
Test status
Simulation time 155999159340 ps
CPU time 278.26 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:54:39 PM PDT 24
Peak memory 198276 kb
Host smart-e326fa9b-d35d-42c6-a53d-5a0841b37ab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520070216 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3520070216
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.411676972
Short name T129
Test name
Test status
Simulation time 366998135 ps
CPU time 0.8 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:03 PM PDT 24
Peak memory 183396 kb
Host smart-a54dde73-eb92-4144-9868-6fe031c091c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411676972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.411676972
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.221059801
Short name T265
Test name
Test status
Simulation time 32458516296 ps
CPU time 30.26 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:31 PM PDT 24
Peak memory 183296 kb
Host smart-4eeeb548-75c1-4355-bde9-4d924a547f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221059801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.221059801
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.110903343
Short name T112
Test name
Test status
Simulation time 499053797 ps
CPU time 1.26 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:49:55 PM PDT 24
Peak memory 183188 kb
Host smart-0979135c-a864-4f57-b18c-9d6dd2bc99da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110903343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.110903343
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3187684200
Short name T252
Test name
Test status
Simulation time 211777965209 ps
CPU time 82.54 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:51:23 PM PDT 24
Peak memory 193612 kb
Host smart-90cc5519-754a-4857-be3e-48b457afb43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187684200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3187684200
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3921205369
Short name T162
Test name
Test status
Simulation time 103458536072 ps
CPU time 210.64 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:53:24 PM PDT 24
Peak memory 198220 kb
Host smart-c8779bbf-9793-474e-922f-d542349c125e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921205369 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3921205369
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.919252581
Short name T148
Test name
Test status
Simulation time 579259344 ps
CPU time 0.63 seconds
Started Apr 21 12:50:09 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 183392 kb
Host smart-6a8cdbde-e8ff-48e7-8c44-e3bd985a50ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919252581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.919252581
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2845090079
Short name T206
Test name
Test status
Simulation time 41392735888 ps
CPU time 19.85 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:26 PM PDT 24
Peak memory 183372 kb
Host smart-0fc497fa-6466-41a2-9929-c3af97bcfc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845090079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2845090079
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2313723814
Short name T114
Test name
Test status
Simulation time 355797185 ps
CPU time 0.84 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 183408 kb
Host smart-09a58240-f74c-4b82-9e10-9addd6073d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313723814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2313723814
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1671684872
Short name T199
Test name
Test status
Simulation time 452172067828 ps
CPU time 330.55 seconds
Started Apr 21 12:50:02 PM PDT 24
Finished Apr 21 12:55:34 PM PDT 24
Peak memory 192832 kb
Host smart-fb9b9d35-d2d7-454d-af01-aa310f5a2bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671684872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1671684872
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1892584999
Short name T44
Test name
Test status
Simulation time 431025822 ps
CPU time 1.13 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 183292 kb
Host smart-b6f3c70b-0038-4caa-b74a-6daf9706fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892584999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1892584999
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2294862192
Short name T155
Test name
Test status
Simulation time 7024517269 ps
CPU time 12.2 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 183336 kb
Host smart-91628f38-1e1e-401a-89c5-6d47b6e11f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294862192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2294862192
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3280299925
Short name T136
Test name
Test status
Simulation time 457575573 ps
CPU time 0.73 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 183296 kb
Host smart-4d56ca25-bb55-483e-a5df-16a8ba3f2b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280299925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3280299925
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.813744084
Short name T281
Test name
Test status
Simulation time 197309380920 ps
CPU time 364.23 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 198328 kb
Host smart-51ae9d6d-b199-4486-bd0a-4f6636c6f572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813744084 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.813744084
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3351295521
Short name T64
Test name
Test status
Simulation time 468113886 ps
CPU time 1.05 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 183152 kb
Host smart-d272e6af-4bd0-4295-b2e4-55c033583a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351295521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3351295521
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1548467514
Short name T145
Test name
Test status
Simulation time 23792917394 ps
CPU time 33.55 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:41 PM PDT 24
Peak memory 183356 kb
Host smart-1f142501-aeb2-476c-bb95-ae24adfe44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548467514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1548467514
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.421302864
Short name T128
Test name
Test status
Simulation time 394592094 ps
CPU time 1.04 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 183300 kb
Host smart-85983695-4259-49c8-a428-34388b2d36ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421302864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.421302864
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1865385055
Short name T156
Test name
Test status
Simulation time 50464734276 ps
CPU time 81.28 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 183380 kb
Host smart-c6532aa7-bbb2-4309-b673-f53a15d2057f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865385055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1865385055
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1320942077
Short name T226
Test name
Test status
Simulation time 52796733281 ps
CPU time 301.26 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:55:02 PM PDT 24
Peak memory 198116 kb
Host smart-1ade470e-c4c6-4b8b-b1eb-e3a7929d30b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320942077 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1320942077
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1308270111
Short name T7
Test name
Test status
Simulation time 378889623 ps
CPU time 0.67 seconds
Started Apr 21 12:49:51 PM PDT 24
Finished Apr 21 12:49:52 PM PDT 24
Peak memory 183208 kb
Host smart-84d9634d-6a30-4382-9ce1-43673cab2c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308270111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1308270111
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2559143985
Short name T109
Test name
Test status
Simulation time 52033608764 ps
CPU time 18.76 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:19 PM PDT 24
Peak memory 183356 kb
Host smart-54bceda3-4ddc-442e-b6be-6ae155c7112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559143985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2559143985
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3753033116
Short name T251
Test name
Test status
Simulation time 379182455 ps
CPU time 1.14 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 183296 kb
Host smart-916d4487-47f1-40b9-ba6d-651d019ead3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753033116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3753033116
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1293995766
Short name T152
Test name
Test status
Simulation time 20467725661 ps
CPU time 14.35 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 183304 kb
Host smart-f7e87000-2615-409b-975f-a8e32e843e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293995766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1293995766
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3720698599
Short name T247
Test name
Test status
Simulation time 462133893 ps
CPU time 0.75 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183220 kb
Host smart-22d8fc17-ea1c-4795-894e-43e8206d156d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720698599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3720698599
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3704737787
Short name T278
Test name
Test status
Simulation time 3521127575 ps
CPU time 3 seconds
Started Apr 21 12:49:24 PM PDT 24
Finished Apr 21 12:49:27 PM PDT 24
Peak memory 183344 kb
Host smart-0db3cee0-d6cf-4e03-8ebe-c7a4a0c4e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704737787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3704737787
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.103805464
Short name T100
Test name
Test status
Simulation time 452568033 ps
CPU time 0.85 seconds
Started Apr 21 12:49:31 PM PDT 24
Finished Apr 21 12:49:32 PM PDT 24
Peak memory 183192 kb
Host smart-a370da1e-f92b-4e59-b7a9-fa8d3425a87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103805464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.103805464
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.687679966
Short name T101
Test name
Test status
Simulation time 91164954817 ps
CPU time 29.81 seconds
Started Apr 21 12:49:45 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 183284 kb
Host smart-573943f3-f373-4d20-ab70-d8025eca0856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687679966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.687679966
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3269228844
Short name T13
Test name
Test status
Simulation time 167712037951 ps
CPU time 348.14 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:55:27 PM PDT 24
Peak memory 198252 kb
Host smart-a0b4d12c-527a-4ab2-8c7b-5bce43652024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269228844 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3269228844
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1152563807
Short name T151
Test name
Test status
Simulation time 577049311 ps
CPU time 0.74 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:49:33 PM PDT 24
Peak memory 183320 kb
Host smart-f127d557-188c-416c-9088-793ab2615ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152563807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1152563807
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2135384999
Short name T98
Test name
Test status
Simulation time 22281518253 ps
CPU time 7.89 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 183336 kb
Host smart-a4309ba4-10a8-47f8-87ce-6d22a7b233ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135384999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2135384999
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3685176844
Short name T192
Test name
Test status
Simulation time 384963319 ps
CPU time 0.72 seconds
Started Apr 21 12:49:23 PM PDT 24
Finished Apr 21 12:49:24 PM PDT 24
Peak memory 183284 kb
Host smart-aac56e9b-4b4d-4cc1-bb18-4649644600e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685176844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3685176844
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1023230892
Short name T120
Test name
Test status
Simulation time 176985206986 ps
CPU time 247.49 seconds
Started Apr 21 12:49:28 PM PDT 24
Finished Apr 21 12:53:36 PM PDT 24
Peak memory 193868 kb
Host smart-ecf37dfb-4ffe-4506-bf1b-7ae93fdc60fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023230892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1023230892
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2800711669
Short name T22
Test name
Test status
Simulation time 22363486684 ps
CPU time 173.05 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:52:24 PM PDT 24
Peak memory 198180 kb
Host smart-54e780b0-84c4-4214-a4aa-c9f422bc808f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800711669 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2800711669
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.2685094031
Short name T1
Test name
Test status
Simulation time 370812544 ps
CPU time 1.12 seconds
Started Apr 21 12:49:29 PM PDT 24
Finished Apr 21 12:49:31 PM PDT 24
Peak memory 183188 kb
Host smart-be32efac-a5f2-4168-befb-0715fbea6d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685094031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.2685094031
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2966374945
Short name T193
Test name
Test status
Simulation time 15187270097 ps
CPU time 3.09 seconds
Started Apr 21 12:49:25 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 183356 kb
Host smart-3a1fdfe2-88be-4d72-b013-b1bf1d133386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966374945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2966374945
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1181644974
Short name T184
Test name
Test status
Simulation time 472064477 ps
CPU time 1.17 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:49:38 PM PDT 24
Peak memory 183268 kb
Host smart-180fedc3-6a4e-440f-a462-4332b57fb392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181644974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1181644974
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2510003828
Short name T118
Test name
Test status
Simulation time 206951880094 ps
CPU time 355.94 seconds
Started Apr 21 12:49:28 PM PDT 24
Finished Apr 21 12:55:24 PM PDT 24
Peak memory 192720 kb
Host smart-fa5aabf7-eb8a-4855-9d2f-45d295e79d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510003828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2510003828
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.319138676
Short name T36
Test name
Test status
Simulation time 20688382045 ps
CPU time 228.15 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 12:53:30 PM PDT 24
Peak memory 198232 kb
Host smart-63f07aab-fdc2-4745-81a7-4cac3a195335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319138676 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.319138676
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1204235970
Short name T180
Test name
Test status
Simulation time 345581003 ps
CPU time 1.14 seconds
Started Apr 21 12:49:26 PM PDT 24
Finished Apr 21 12:49:28 PM PDT 24
Peak memory 183228 kb
Host smart-4e5035fc-ea26-4eb5-9daa-7ae8a3e024d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204235970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1204235970
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3535054539
Short name T237
Test name
Test status
Simulation time 38700460124 ps
CPU time 15.84 seconds
Started Apr 21 12:49:34 PM PDT 24
Finished Apr 21 12:49:50 PM PDT 24
Peak memory 183272 kb
Host smart-62cee311-eb12-4b6a-aeb3-a86901dc594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535054539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3535054539
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3872395956
Short name T196
Test name
Test status
Simulation time 554225894 ps
CPU time 0.97 seconds
Started Apr 21 12:49:32 PM PDT 24
Finished Apr 21 12:49:33 PM PDT 24
Peak memory 183280 kb
Host smart-f35f99c4-3333-4ebd-a1bd-cda76d889337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872395956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3872395956
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.752447938
Short name T135
Test name
Test status
Simulation time 150183854190 ps
CPU time 46.9 seconds
Started Apr 21 12:49:28 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 194724 kb
Host smart-c3f8ad46-deed-490c-97b3-13287ee04551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752447938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.752447938
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1259050528
Short name T200
Test name
Test status
Simulation time 20386089796 ps
CPU time 228.87 seconds
Started Apr 21 12:49:21 PM PDT 24
Finished Apr 21 12:53:10 PM PDT 24
Peak memory 198268 kb
Host smart-f0d75444-14b9-4b1f-b318-cac163d8faf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259050528 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1259050528
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2741311882
Short name T273
Test name
Test status
Simulation time 462110914 ps
CPU time 0.72 seconds
Started Apr 21 12:49:39 PM PDT 24
Finished Apr 21 12:49:40 PM PDT 24
Peak memory 183216 kb
Host smart-c58b3aa2-b7f2-4a99-a5b9-f88bd4cf2643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741311882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2741311882
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2398690399
Short name T28
Test name
Test status
Simulation time 14341872130 ps
CPU time 5.91 seconds
Started Apr 21 12:49:31 PM PDT 24
Finished Apr 21 12:49:37 PM PDT 24
Peak memory 183340 kb
Host smart-81eabe1d-876a-40ea-b21a-4972a67031c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398690399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2398690399
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1198615869
Short name T208
Test name
Test status
Simulation time 532837838 ps
CPU time 1.26 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 12:49:34 PM PDT 24
Peak memory 183200 kb
Host smart-b4851998-5bad-49eb-887b-a3bf645bbf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198615869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1198615869
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1475648324
Short name T230
Test name
Test status
Simulation time 531491243019 ps
CPU time 814.87 seconds
Started Apr 21 12:49:36 PM PDT 24
Finished Apr 21 01:03:11 PM PDT 24
Peak memory 183336 kb
Host smart-b8ea8684-1759-479d-a665-45f50002ac93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475648324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1475648324
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3560266733
Short name T48
Test name
Test status
Simulation time 120881215322 ps
CPU time 980.89 seconds
Started Apr 21 12:49:33 PM PDT 24
Finished Apr 21 01:05:55 PM PDT 24
Peak memory 202720 kb
Host smart-ca417a3a-e2f0-459d-b21a-1709883ed72a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560266733 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3560266733
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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