ASSERT | PROPERTIES | SEQUENCES | |
Total | 396 | 0 | 10 |
Category 0 | 396 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 396 | 0 | 10 |
Severity 0 | 396 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 396 | 100.00 |
Uncovered | 2 | 0.51 |
Success | 394 | 99.49 |
Failure | 0 | 0.00 |
Incomplete | 5 | 1.26 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3817681 | 0 | 0 | 425 | |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.HwIdSelCheck_A | 0 | 0 | 3817681 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A | 0 | 0 | 3760365 | 3697965 | 0 | 738 | |
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3817681 | 402 | 0 | 426 | |
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3817681 | 1217 | 0 | 425 | |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3817681 | 0 | 0 | 425 | |
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3817681 | 2786 | 0 | 425 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 810104740 | 148876 | 148876 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 810104740 | 131 | 131 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 810104740 | 135 | 135 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 810104740 | 91 | 91 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 810104740 | 28 | 28 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 810104740 | 74 | 74 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 810104740 | 49 | 49 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 810104740 | 2207 | 2207 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 810104740 | 3055 | 3055 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 810104740 | 16874 | 16874 | 303 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 810104740 | 148876 | 148876 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 810104740 | 131 | 131 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 810104740 | 135 | 135 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 810104740 | 91 | 91 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 810104740 | 28 | 28 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 810104740 | 74 | 74 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 810104740 | 49 | 49 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 810104740 | 2207 | 2207 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 810104740 | 3055 | 3055 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 810104740 | 16874 | 16874 | 303 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |