Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	289403	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3459893	1		T1	98976		T2	15		T3	17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	923277	1		T1	26137		T2	1		T3	1
values[0x0]	1323201	1		T1	38021		T2	10		T3	11
values[0x1]	1502818	1		T1	42625		T2	11		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130792	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	3618504	1		T1	103328		T2	16		T3	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	14376	1		T1	543		T5	351		T10	612
valid_sources[0x01]	14671	1		T1	428		T5	667		T10	535
valid_sources[0x02]	14207	1		T1	458		T5	388		T6	2
valid_sources[0x03]	15494	1		T1	424		T5	1184		T10	620
valid_sources[0x04]	13983	1		T1	377		T5	978		T10	582
valid_sources[0x05]	15698	1		T1	421		T5	983		T10	635
valid_sources[0x06]	13741	1		T1	369		T5	815		T10	578
valid_sources[0x07]	12763	1		T1	327		T5	225		T10	524
valid_sources[0x08]	14584	1		T1	463		T3	1		T5	393
valid_sources[0x09]	14559	1		T1	535		T5	640		T10	553
valid_sources[0x0a]	14527	1		T1	418		T5	996		T10	545
valid_sources[0x0b]	14193	1		T1	407		T5	426		T6	1
valid_sources[0x0c]	15147	1		T1	368		T5	405		T10	585
valid_sources[0x0d]	14883	1		T1	489		T5	405		T10	588
valid_sources[0x0e]	14706	1		T1	446		T4	1		T5	603
valid_sources[0x0f]	14772	1		T1	406		T5	1584		T10	544
valid_sources[0x10]	14559	1		T1	444		T3	3		T5	504
valid_sources[0x11]	13642	1		T1	441		T5	375		T10	519
valid_sources[0x12]	17387	1		T1	398		T5	941		T10	577
valid_sources[0x13]	14323	1		T1	500		T5	617		T8	1
valid_sources[0x14]	15056	1		T1	365		T5	331		T10	612
valid_sources[0x15]	14371	1		T1	455		T5	1076		T10	496
valid_sources[0x16]	15693	1		T1	414		T5	697		T6	1
valid_sources[0x17]	14762	1		T1	358		T5	514		T10	562
valid_sources[0x18]	13682	1		T1	363		T5	483		T10	577
valid_sources[0x19]	15400	1		T1	413		T5	478		T10	549
valid_sources[0x1a]	13378	1		T1	335		T5	601		T10	622
valid_sources[0x1b]	14200	1		T1	468		T5	722		T6	1
valid_sources[0x1c]	15346	1		T1	398		T5	874		T10	596
valid_sources[0x1d]	14586	1		T1	472		T5	518		T10	591
valid_sources[0x1e]	14806	1		T1	518		T5	615		T8	6
valid_sources[0x1f]	14454	1		T1	335		T5	678		T8	1
valid_sources[0x20]	13616	1		T1	366		T5	664		T10	633
valid_sources[0x21]	14513	1		T1	528		T5	1152		T10	611
valid_sources[0x22]	15497	1		T1	376		T5	784		T10	548
valid_sources[0x23]	12780	1		T1	432		T5	230		T10	664
valid_sources[0x24]	14675	1		T1	386		T5	256		T10	566
valid_sources[0x25]	13805	1		T1	435		T5	611		T10	565
valid_sources[0x26]	15252	1		T1	359		T5	430		T10	571
valid_sources[0x27]	15226	1		T1	411		T5	506		T10	552
valid_sources[0x28]	15344	1		T1	561		T5	957		T10	595
valid_sources[0x29]	15372	1		T1	446		T5	296		T10	559
valid_sources[0x2a]	14785	1		T1	314		T5	739		T10	563
valid_sources[0x2b]	15527	1		T1	533		T5	720		T10	570
valid_sources[0x2c]	15141	1		T1	352		T5	424		T10	552
valid_sources[0x2d]	13088	1		T1	553		T2	22		T5	1248
valid_sources[0x2e]	15307	1		T1	504		T4	1		T5	972
valid_sources[0x2f]	16007	1		T1	373		T5	898		T10	547
valid_sources[0x30]	14791	1		T1	451		T5	392		T10	612
valid_sources[0x31]	16284	1		T1	388		T5	526		T8	1
valid_sources[0x32]	13982	1		T1	420		T3	1		T5	292
valid_sources[0x33]	14464	1		T1	428		T5	538		T10	522
valid_sources[0x34]	14949	1		T1	431		T5	1044		T10	580
valid_sources[0x35]	15015	1		T1	420		T5	201		T10	576
valid_sources[0x36]	15388	1		T1	293		T5	915		T10	608
valid_sources[0x37]	14149	1		T1	376		T5	597		T10	585
valid_sources[0x38]	14920	1		T1	502		T5	952		T10	577
valid_sources[0x39]	13348	1		T1	427		T5	829		T10	566
valid_sources[0x3a]	14688	1		T1	284		T5	808		T6	1
valid_sources[0x3b]	13534	1		T1	396		T5	470		T10	604
valid_sources[0x3c]	15035	1		T1	445		T5	509		T10	556
valid_sources[0x3d]	14260	1		T1	430		T5	850		T10	558
valid_sources[0x3e]	14241	1		T1	373		T5	810		T10	563
valid_sources[0x3f]	12452	1		T1	336		T5	111		T10	524
valid_sources[0x40]	13873	1		T1	458		T5	273		T10	592
valid_sources[0x41]	14540	1		T1	327		T5	600		T10	488
valid_sources[0x42]	15051	1		T1	345		T5	475		T10	606
valid_sources[0x43]	13769	1		T1	349		T5	559		T6	1
valid_sources[0x44]	13432	1		T1	451		T5	1102		T6	1
valid_sources[0x45]	15546	1		T1	360		T5	546		T10	590
valid_sources[0x46]	15003	1		T1	457		T5	892		T10	598
valid_sources[0x47]	13474	1		T1	472		T5	505		T10	514
valid_sources[0x48]	14554	1		T1	412		T5	468		T10	620
valid_sources[0x49]	14936	1		T1	326		T3	3		T5	569
valid_sources[0x4a]	14500	1		T1	344		T5	365		T10	575
valid_sources[0x4b]	14031	1		T1	403		T5	387		T9	7
valid_sources[0x4c]	15170	1		T1	382		T5	487		T10	573
valid_sources[0x4d]	16328	1		T1	480		T5	1010		T10	599
valid_sources[0x4e]	14496	1		T1	443		T5	815		T10	556
valid_sources[0x4f]	13982	1		T1	376		T5	550		T10	593
valid_sources[0x50]	16011	1		T1	390		T5	816		T10	586
valid_sources[0x51]	14725	1		T1	375		T5	386		T10	540
valid_sources[0x52]	15064	1		T1	444		T5	456		T8	2
valid_sources[0x53]	15222	1		T1	489		T5	681		T10	627
valid_sources[0x54]	15570	1		T1	401		T5	612		T10	618
valid_sources[0x55]	14656	1		T1	416		T5	1005		T6	1
valid_sources[0x56]	13926	1		T1	353		T5	559		T9	2
valid_sources[0x57]	15348	1		T1	455		T3	1		T5	751
valid_sources[0x58]	14007	1		T1	370		T5	234		T10	546
valid_sources[0x59]	12800	1		T1	443		T5	318		T10	579
valid_sources[0x5a]	15284	1		T1	330		T5	903		T10	617
valid_sources[0x5b]	14408	1		T1	360		T3	1		T5	528
valid_sources[0x5c]	15499	1		T1	445		T5	1322		T10	557
valid_sources[0x5d]	13109	1		T1	389		T5	926		T10	499
valid_sources[0x5e]	16003	1		T1	454		T5	371		T10	515
valid_sources[0x5f]	13887	1		T1	477		T4	3		T5	420
valid_sources[0x60]	15192	1		T1	465		T5	434		T10	580
valid_sources[0x61]	15862	1		T1	464		T5	807		T10	652
valid_sources[0x62]	15374	1		T1	384		T5	351		T10	571
valid_sources[0x63]	13687	1		T1	301		T5	782		T6	1
valid_sources[0x64]	14984	1		T1	345		T5	619		T10	559
valid_sources[0x65]	14592	1		T1	480		T5	669		T9	4
valid_sources[0x66]	13301	1		T1	460		T5	721		T10	629
valid_sources[0x67]	13385	1		T1	418		T5	800		T10	580
valid_sources[0x68]	14249	1		T1	420		T5	129		T10	551
valid_sources[0x69]	14991	1		T1	315		T5	871		T10	569
valid_sources[0x6a]	16359	1		T1	404		T5	1079		T10	528
valid_sources[0x6b]	14863	1		T1	505		T4	1		T5	498
valid_sources[0x6c]	16010	1		T1	413		T5	934		T10	600
valid_sources[0x6d]	15959	1		T1	440		T5	756		T10	592
valid_sources[0x6e]	15204	1		T1	404		T3	1		T5	546
valid_sources[0x6f]	15919	1		T1	517		T5	461		T9	1
valid_sources[0x70]	15831	1		T1	345		T5	870		T9	4
valid_sources[0x71]	14704	1		T1	480		T5	484		T10	636
valid_sources[0x72]	12936	1		T1	360		T5	837		T10	510
valid_sources[0x73]	14375	1		T1	447		T5	504		T10	585
valid_sources[0x74]	14379	1		T1	426		T5	558		T10	574
valid_sources[0x75]	13854	1		T1	417		T5	623		T10	574
valid_sources[0x76]	15478	1		T1	298		T5	690		T10	581
valid_sources[0x77]	15209	1		T1	419		T5	833		T6	1
valid_sources[0x78]	15456	1		T1	450		T5	743		T10	554
valid_sources[0x79]	13596	1		T1	473		T5	405		T10	537
valid_sources[0x7a]	15023	1		T1	486		T5	516		T10	574
valid_sources[0x7b]	13862	1		T1	377		T4	1		T5	815
valid_sources[0x7c]	13493	1		T1	410		T5	522		T10	590
valid_sources[0x7d]	16041	1		T1	397		T5	776		T7	373
valid_sources[0x7e]	13841	1		T1	427		T5	705		T10	571
valid_sources[0x7f]	14751	1		T1	435		T5	705		T10	556
valid_sources[0x80]	15914	1		T1	374		T5	1150		T10	594

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

863752

1

T1

24619

T2

1

T5

38335

values[0x0]

all_enables

biggest_size

1297870

1

T1

37362

T2

7

T3

11

values[0x1]

all_enables

biggest_size

1298271

1

T1

36995

T2

7

T3

6