Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	650010646	4106406	0	0
wdog_bark_thold_rd_A	650010646	118283	0	0
wdog_bite_thold_rd_A	650010646	104228	0	0
wdog_ctrl_rd_A	650010646	103025	0	0
wdog_regwen_rd_A	650010646	119979	0	0
wkup_ctrl_rd_A	650010646	102797	0	0
wkup_thold_hi_rd_A	650010646	116675	0	0
wkup_thold_lo_rd_A	650010646	103068	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	4106406	0	0
T1	307087	114889	0	0
T2	11579	0	0	0
T3	42399	0	0	0
T4	632412	0	0	0
T5	757437	173961	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	159192	0	0
T12	0	103721	0	0
T38	0	169905	0	0
T39	0	87436	0	0
T40	0	124197	0	0
T41	0	93865	0	0
T42	0	90528	0	0
T43	0	76672	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	118283	0	0
T5	757437	18422	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	8469	0	0
T38	0	8730	0	0
T39	0	8334	0	0
T42	0	4709	0	0
T79	0	1993	0	0
T80	0	6976	0	0
T81	0	12443	0	0
T82	0	2487	0	0
T83	0	5971	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	104228	0	0
T5	757437	16151	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	7482	0	0
T38	0	7746	0	0
T39	0	7313	0	0
T42	0	4410	0	0
T79	0	1623	0	0
T80	0	6321	0	0
T81	0	10882	0	0
T82	0	2209	0	0
T83	0	5543	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	103025	0	0
T5	757437	15126	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	7836	0	0
T38	0	7684	0	0
T39	0	7386	0	0
T42	0	3883	0	0
T79	0	1713	0	0
T80	0	6244	0	0
T81	0	11067	0	0
T82	0	2324	0	0
T83	0	5014	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	119979	0	0
T5	757437	18141	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	8779	0	0
T38	0	8979	0	0
T39	0	8758	0	0
T42	0	4840	0	0
T79	0	2031	0	0
T80	0	7433	0	0
T81	0	12455	0	0
T82	0	2671	0	0
T83	0	6187	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	102797	0	0
T5	757437	16237	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	7295	0	0
T38	0	7601	0	0
T39	0	7230	0	0
T42	0	4421	0	0
T79	0	1697	0	0
T80	0	6276	0	0
T81	0	10473	0	0
T82	0	2370	0	0
T83	0	5194	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	116675	0	0
T5	757437	17763	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	8585	0	0
T38	0	8906	0	0
T39	0	8193	0	0
T42	0	4916	0	0
T79	0	1830	0	0
T80	0	6841	0	0
T81	0	12126	0	0
T82	0	2396	0	0
T83	0	5778	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650010646	103068	0	0
T5	757437	15718	0	0
T6	400569	0	0	0
T7	186563	0	0	0
T8	366154	0	0	0
T9	681409	0	0	0
T10	438861	0	0	0
T11	135930	0	0	0
T12	412942	0	0	0
T13	38134	0	0	0
T14	13354	0	0	0
T27	0	7731	0	0
T38	0	7722	0	0
T39	0	7286	0	0
T42	0	4280	0	0
T79	0	1558	0	0
T80	0	6326	0	0
T81	0	11072	0	0
T82	0	2072	0	0
T83	0	5052	0	0