Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318330	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3890348	1		T1	116572		T2	128693		T3	224

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1035284	1		T1	30765		T2	33744		T3	46
values[0x0]	1487702	1		T1	44419		T2	49652		T3	160
values[0x1]	1685692	1		T1	50175		T2	55657		T3	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142515	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4066163	1		T1	121585		T2	134485		T3	247

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15889	1		T1	455		T2	487		T3	4
valid_sources[0x01]	19003	1		T1	477		T2	488		T5	300
valid_sources[0x02]	15007	1		T1	500		T2	521		T3	2
valid_sources[0x03]	16400	1		T1	549		T2	517		T3	4
valid_sources[0x04]	16686	1		T1	529		T2	565		T5	430
valid_sources[0x05]	17695	1		T1	546		T2	596		T5	203
valid_sources[0x06]	17024	1		T1	466		T2	507		T5	273
valid_sources[0x07]	16845	1		T1	407		T2	490		T3	1
valid_sources[0x08]	16965	1		T1	497		T2	512		T4	9
valid_sources[0x09]	16334	1		T1	461		T2	569		T3	1
valid_sources[0x0a]	16554	1		T1	543		T2	602		T3	1
valid_sources[0x0b]	17179	1		T1	505		T2	506		T3	1
valid_sources[0x0c]	16573	1		T1	485		T2	519		T5	192
valid_sources[0x0d]	15955	1		T1	515		T2	493		T5	278
valid_sources[0x0e]	16080	1		T1	440		T2	693		T5	191
valid_sources[0x0f]	16385	1		T1	473		T2	525		T3	2
valid_sources[0x10]	15753	1		T1	443		T2	573		T5	257
valid_sources[0x11]	16977	1		T1	457		T2	487		T5	314
valid_sources[0x12]	16352	1		T1	501		T2	631		T3	1
valid_sources[0x13]	16334	1		T1	502		T2	552		T5	301
valid_sources[0x14]	17068	1		T1	524		T2	517		T3	3
valid_sources[0x15]	16397	1		T1	504		T2	547		T5	273
valid_sources[0x16]	17459	1		T1	556		T2	541		T5	283
valid_sources[0x17]	15135	1		T1	495		T2	495		T5	239
valid_sources[0x18]	17558	1		T1	507		T2	567		T3	1
valid_sources[0x19]	16185	1		T1	476		T2	483		T5	256
valid_sources[0x1a]	17250	1		T1	605		T2	557		T5	233
valid_sources[0x1b]	17206	1		T1	487		T2	591		T3	3
valid_sources[0x1c]	16252	1		T1	504		T2	567		T5	304
valid_sources[0x1d]	15998	1		T1	493		T2	491		T5	273
valid_sources[0x1e]	16857	1		T1	467		T2	625		T3	3
valid_sources[0x1f]	17387	1		T1	439		T2	511		T3	4
valid_sources[0x20]	15387	1		T1	551		T2	463		T3	1
valid_sources[0x21]	15700	1		T1	460		T2	498		T3	2
valid_sources[0x22]	16585	1		T1	435		T2	565		T3	3
valid_sources[0x23]	16055	1		T1	508		T2	475		T3	2
valid_sources[0x24]	17679	1		T1	517		T2	488		T5	237
valid_sources[0x25]	15570	1		T1	438		T2	542		T3	1
valid_sources[0x26]	16360	1		T1	450		T2	540		T3	1
valid_sources[0x27]	16328	1		T1	504		T2	562		T3	3
valid_sources[0x28]	17313	1		T1	446		T2	471		T3	1
valid_sources[0x29]	15528	1		T1	475		T2	496		T3	1
valid_sources[0x2a]	15885	1		T1	490		T2	531		T5	236
valid_sources[0x2b]	17528	1		T1	485		T2	518		T3	2
valid_sources[0x2c]	16295	1		T1	427		T2	552		T3	3
valid_sources[0x2d]	15691	1		T1	533		T2	492		T3	2
valid_sources[0x2e]	15741	1		T1	482		T2	622		T5	261
valid_sources[0x2f]	15542	1		T1	451		T2	475		T3	1
valid_sources[0x30]	17109	1		T1	596		T2	564		T3	1
valid_sources[0x31]	16851	1		T1	543		T2	603		T3	1
valid_sources[0x32]	16774	1		T1	439		T2	651		T3	1
valid_sources[0x33]	16612	1		T1	544		T2	505		T3	1
valid_sources[0x34]	15971	1		T1	537		T2	546		T3	2
valid_sources[0x35]	15061	1		T1	424		T2	612		T3	1
valid_sources[0x36]	15007	1		T1	460		T2	530		T3	2
valid_sources[0x37]	16783	1		T1	489		T2	600		T5	288
valid_sources[0x38]	17966	1		T1	594		T2	598		T3	1
valid_sources[0x39]	15991	1		T1	539		T2	613		T3	1
valid_sources[0x3a]	17499	1		T1	493		T2	498		T3	2
valid_sources[0x3b]	16948	1		T1	478		T2	488		T3	5
valid_sources[0x3c]	15482	1		T1	425		T2	499		T3	5
valid_sources[0x3d]	16673	1		T1	446		T2	523		T3	1
valid_sources[0x3e]	16260	1		T1	499		T2	533		T3	4
valid_sources[0x3f]	15457	1		T1	516		T2	523		T3	1
valid_sources[0x40]	16253	1		T1	453		T2	466		T3	3
valid_sources[0x41]	16334	1		T1	538		T2	565		T3	3
valid_sources[0x42]	17854	1		T1	470		T2	602		T3	4
valid_sources[0x43]	15733	1		T1	448		T2	610		T3	1
valid_sources[0x44]	16546	1		T1	491		T2	493		T5	225
valid_sources[0x45]	16650	1		T1	459		T2	516		T3	2
valid_sources[0x46]	15510	1		T1	433		T2	534		T3	1
valid_sources[0x47]	16528	1		T1	522		T2	565		T3	1
valid_sources[0x48]	16063	1		T1	453		T2	569		T5	272
valid_sources[0x49]	17294	1		T1	499		T2	625		T3	2
valid_sources[0x4a]	16404	1		T1	460		T2	619		T3	1
valid_sources[0x4b]	15464	1		T1	475		T2	537		T3	1
valid_sources[0x4c]	16045	1		T1	549		T2	548		T3	2
valid_sources[0x4d]	15242	1		T1	448		T2	502		T5	259
valid_sources[0x4e]	15150	1		T1	541		T2	553		T3	1
valid_sources[0x4f]	17513	1		T1	460		T2	677		T3	2
valid_sources[0x50]	16191	1		T1	392		T2	549		T5	221
valid_sources[0x51]	16588	1		T1	495		T2	401		T3	1
valid_sources[0x52]	15601	1		T1	555		T2	525		T3	4
valid_sources[0x53]	16141	1		T1	497		T2	608		T3	3
valid_sources[0x54]	15585	1		T1	473		T2	481		T3	1
valid_sources[0x55]	16186	1		T1	509		T2	583		T5	271
valid_sources[0x56]	15920	1		T1	422		T2	512		T3	2
valid_sources[0x57]	16112	1		T1	551		T2	523		T3	1
valid_sources[0x58]	15332	1		T1	542		T2	516		T3	1
valid_sources[0x59]	16494	1		T1	470		T2	472		T3	2
valid_sources[0x5a]	16506	1		T1	609		T2	459		T3	2
valid_sources[0x5b]	15587	1		T1	449		T2	440		T3	3
valid_sources[0x5c]	16722	1		T1	497		T2	484		T3	1
valid_sources[0x5d]	14175	1		T1	485		T2	706		T3	3
valid_sources[0x5e]	16090	1		T1	449		T2	449		T3	1
valid_sources[0x5f]	15968	1		T1	487		T2	491		T3	1
valid_sources[0x60]	17352	1		T1	500		T2	689		T5	322
valid_sources[0x61]	17733	1		T1	455		T2	571		T3	2
valid_sources[0x62]	17302	1		T1	471		T2	603		T3	1
valid_sources[0x63]	15649	1		T1	487		T2	512		T3	2
valid_sources[0x64]	17568	1		T1	482		T2	590		T3	1
valid_sources[0x65]	17190	1		T1	495		T2	557		T3	1
valid_sources[0x66]	16387	1		T1	534		T2	564		T3	1
valid_sources[0x67]	17020	1		T1	471		T2	393		T3	2
valid_sources[0x68]	16842	1		T1	477		T2	578		T3	1
valid_sources[0x69]	16201	1		T1	493		T2	560		T3	3
valid_sources[0x6a]	16684	1		T1	512		T2	454		T3	1
valid_sources[0x6b]	15747	1		T1	559		T2	554		T5	227
valid_sources[0x6c]	14265	1		T1	468		T2	410		T3	2
valid_sources[0x6d]	16236	1		T1	508		T2	508		T3	2
valid_sources[0x6e]	16890	1		T1	470		T2	551		T3	2
valid_sources[0x6f]	16214	1		T1	545		T2	498		T3	2
valid_sources[0x70]	16939	1		T1	448		T2	558		T3	1
valid_sources[0x71]	15402	1		T1	487		T2	509		T3	3
valid_sources[0x72]	18223	1		T1	457		T2	510		T3	5
valid_sources[0x73]	17045	1		T1	511		T2	473		T3	2
valid_sources[0x74]	16989	1		T1	474		T2	521		T3	3
valid_sources[0x75]	15245	1		T1	464		T2	524		T3	1
valid_sources[0x76]	16390	1		T1	425		T2	549		T5	220
valid_sources[0x77]	18096	1		T1	486		T2	520		T3	3
valid_sources[0x78]	15342	1		T1	521		T2	463		T3	1
valid_sources[0x79]	16059	1		T1	490		T2	533		T5	209
valid_sources[0x7a]	17037	1		T1	549		T2	610		T3	1
valid_sources[0x7b]	17517	1		T1	494		T2	592		T3	2
valid_sources[0x7c]	15066	1		T1	455		T2	527		T5	220
valid_sources[0x7d]	15590	1		T1	513		T2	564		T3	1
valid_sources[0x7e]	17111	1		T1	531		T2	477		T3	5
valid_sources[0x7f]	15016	1		T1	492		T2	498		T3	2
valid_sources[0x80]	15834	1		T1	464		T2	560		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

970261

1

T1

29080

T2

31811

T3

20

values[0x0]

all_enables

biggest_size

1460806

1

T1

43795

T2

48816

T3

115

values[0x1]

all_enables

biggest_size

1459281

1

T1

43697

T2

48066

T3

89