Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	695504359	4620480	0	0
wdog_bark_thold_rd_A	695504359	42792	0	0
wdog_bite_thold_rd_A	695504359	38066	0	0
wdog_ctrl_rd_A	695504359	38586	0	0
wdog_regwen_rd_A	695504359	43544	0	0
wkup_ctrl_rd_A	695504359	37248	0	0
wkup_thold_hi_rd_A	695504359	42909	0	0
wkup_thold_lo_rd_A	695504359	36705	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	4620480	0	0
T1	380337	137934	0	0
T2	416635	153668	0	0
T3	569432	0	0	0
T4	45726	0	0	0
T5	305893	81366	0	0
T6	35289	0	0	0
T7	335797	0	0	0
T8	276113	100000	0	0
T9	14326	0	0	0
T10	360624	0	0	0
T25	0	323541	0	0
T32	0	61113	0	0
T39	0	53067	0	0
T40	0	43667	0	0
T41	0	154529	0	0
T42	0	37158	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	42792	0	0
T34	0	36	0	0
T48	0	8201	0	0
T49	0	108	0	0
T69	0	4284	0	0
T82	215497	5385	0	0
T83	0	2889	0	0
T84	0	7943	0	0
T85	0	4399	0	0
T86	0	8401	0	0
T87	0	22	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	38066	0	0
T34	0	14	0	0
T48	0	7256	0	0
T49	0	70	0	0
T69	0	3798	0	0
T82	215497	4676	0	0
T83	0	2408	0	0
T84	0	7222	0	0
T85	0	3985	0	0
T86	0	7391	0	0
T87	0	15	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	38586	0	0
T34	0	44	0	0
T48	0	7796	0	0
T49	0	75	0	0
T69	0	3579	0	0
T82	215497	5022	0	0
T83	0	2343	0	0
T84	0	7516	0	0
T85	0	3859	0	0
T86	0	7070	0	0
T87	0	17	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	43544	0	0
T34	0	47	0	0
T48	0	8283	0	0
T49	0	95	0	0
T69	0	4170	0	0
T82	215497	5726	0	0
T83	0	2794	0	0
T84	0	8124	0	0
T85	0	4484	0	0
T86	0	8340	0	0
T87	0	20	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	37248	0	0
T34	0	25	0	0
T48	0	6998	0	0
T49	0	85	0	0
T69	0	3626	0	0
T82	215497	4816	0	0
T83	0	2555	0	0
T84	0	7193	0	0
T85	0	3637	0	0
T86	0	6975	0	0
T87	0	22	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	42909	0	0
T34	0	33	0	0
T48	0	8029	0	0
T49	0	88	0	0
T69	0	4141	0	0
T82	215497	5605	0	0
T83	0	2844	0	0
T84	0	8348	0	0
T85	0	4381	0	0
T86	0	8193	0	0
T87	0	22	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695504359	36705	0	0
T34	0	4	0	0
T48	0	6889	0	0
T49	0	69	0	0
T69	0	3585	0	0
T82	215497	4551	0	0
T83	0	2333	0	0
T84	0	7032	0	0
T85	0	4026	0	0
T86	0	6847	0	0
T87	0	9	0	0
T88	9058	0	0	0
T89	10874	0	0	0
T90	10666	0	0	0
T91	426199	0	0	0
T92	349421	0	0	0
T93	537513	0	0	0
T94	5582	0	0	0
T95	34171	0	0	0
T96	57978	0	0	0