Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	643012934	5530973	0	0
wdog_bark_thold_rd_A	643012934	61257	0	0
wdog_bite_thold_rd_A	643012934	54322	0	0
wdog_ctrl_rd_A	643012934	52638	0	0
wdog_regwen_rd_A	643012934	62398	0	0
wkup_ctrl_rd_A	643012934	53952	0	0
wkup_thold_hi_rd_A	643012934	62022	0	0
wkup_thold_lo_rd_A	643012934	52824	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	5530973	0	0
T13	323900	83321	0	0
T14	704461	90346	0	0
T15	371395	140928	0	0
T30	11546	0	0	0
T31	107864	26562	0	0
T38	116540	23996	0	0
T39	0	56533	0	0
T40	0	76380	0	0
T41	0	23613	0	0
T42	0	70918	0	0
T43	0	301587	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	61257	0	0
T14	704461	4451	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1280	0	0
T38	116540	2248	0	0
T40	0	8017	0	0
T41	0	1321	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	908	0	0
T84	0	4439	0	0
T85	0	7588	0	0
T86	0	4536	0	0
T87	0	5354	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	54322	0	0
T14	704461	4294	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1156	0	0
T38	116540	1980	0	0
T40	0	7193	0	0
T41	0	1166	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	688	0	0
T84	0	3715	0	0
T85	0	7002	0	0
T86	0	3864	0	0
T87	0	4944	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	52638	0	0
T14	704461	4006	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1092	0	0
T38	116540	1696	0	0
T40	0	6560	0	0
T41	0	1101	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	885	0	0
T84	0	3641	0	0
T85	0	6600	0	0
T86	0	3568	0	0
T87	0	4964	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	62398	0	0
T14	704461	4663	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1291	0	0
T38	116540	2226	0	0
T40	0	8194	0	0
T41	0	1413	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	979	0	0
T84	0	4218	0	0
T85	0	7807	0	0
T86	0	4194	0	0
T87	0	5824	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	53952	0	0
T14	704461	3872	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1065	0	0
T38	116540	1868	0	0
T40	0	6941	0	0
T41	0	1269	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	860	0	0
T84	0	3742	0	0
T85	0	6641	0	0
T86	0	3621	0	0
T87	0	5204	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	62022	0	0
T14	704461	4649	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1377	0	0
T38	116540	2223	0	0
T40	0	8036	0	0
T41	0	1523	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	909	0	0
T84	0	4288	0	0
T85	0	7959	0	0
T86	0	4107	0	0
T87	0	5310	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643012934	52824	0	0
T14	704461	3945	0	0
T15	371395	0	0	0
T30	11546	0	0	0
T31	107864	1132	0	0
T38	116540	1943	0	0
T40	0	6675	0	0
T41	0	1059	0	0
T44	13768	0	0	0
T45	718428	0	0	0
T46	314767	0	0	0
T47	427941	0	0	0
T50	247899	0	0	0
T69	0	889	0	0
T84	0	3568	0	0
T85	0	6613	0	0
T86	0	3567	0	0
T87	0	4742	0	0