Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	422439	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5163850	1		T1	51948		T2	14		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1372512	1		T1	13692		T2	1		T3	1
values[0x0]	1973758	1		T1	20130		T2	10		T3	11
values[0x1]	2240019	1		T1	22386		T2	11		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188006	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5398283	1		T1	54337		T2	14		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20315	1		T1	222		T13	739		T15	673
valid_sources[0x01]	22119	1		T1	216		T8	3		T13	1082
valid_sources[0x02]	20846	1		T1	215		T12	1		T13	647
valid_sources[0x03]	21379	1		T1	214		T6	3		T13	535
valid_sources[0x04]	21969	1		T1	202		T13	408		T15	664
valid_sources[0x05]	21477	1		T1	231		T9	2		T12	1
valid_sources[0x06]	22307	1		T1	238		T13	712		T15	643
valid_sources[0x07]	20600	1		T1	222		T13	987		T15	653
valid_sources[0x08]	22565	1		T1	240		T13	1296		T15	642
valid_sources[0x09]	20521	1		T1	232		T12	1		T13	305
valid_sources[0x0a]	21815	1		T1	228		T13	577		T15	660
valid_sources[0x0b]	22960	1		T1	209		T13	1121		T15	666
valid_sources[0x0c]	22268	1		T1	225		T13	589		T15	668
valid_sources[0x0d]	21409	1		T1	205		T31	2		T11	1
valid_sources[0x0e]	21138	1		T1	260		T13	745		T14	1
valid_sources[0x0f]	20915	1		T1	238		T13	410		T15	670
valid_sources[0x10]	21954	1		T1	220		T13	547		T15	646
valid_sources[0x11]	21941	1		T1	246		T13	1864		T15	644
valid_sources[0x12]	21198	1		T1	222		T9	1		T13	623
valid_sources[0x13]	22113	1		T1	223		T13	398		T14	1
valid_sources[0x14]	21769	1		T1	204		T13	544		T15	664
valid_sources[0x15]	22257	1		T1	218		T13	956		T15	714
valid_sources[0x16]	24435	1		T1	218		T13	1286		T15	679
valid_sources[0x17]	22894	1		T1	235		T11	1		T13	1549
valid_sources[0x18]	22462	1		T1	227		T13	1292		T15	662
valid_sources[0x19]	22501	1		T1	232		T13	577		T15	681
valid_sources[0x1a]	23015	1		T1	199		T13	1123		T15	699
valid_sources[0x1b]	22418	1		T1	225		T13	860		T15	655
valid_sources[0x1c]	21317	1		T1	238		T13	994		T15	649
valid_sources[0x1d]	19579	1		T1	216		T31	1		T13	298
valid_sources[0x1e]	21852	1		T1	218		T13	789		T15	656
valid_sources[0x1f]	22209	1		T1	226		T13	591		T15	673
valid_sources[0x20]	22513	1		T1	225		T7	1		T13	444
valid_sources[0x21]	20804	1		T1	228		T13	335		T15	652
valid_sources[0x22]	21959	1		T1	233		T9	1		T13	238
valid_sources[0x23]	23325	1		T1	205		T2	5		T13	886
valid_sources[0x24]	20558	1		T1	240		T13	921		T15	610
valid_sources[0x25]	21697	1		T1	217		T13	1149		T15	662
valid_sources[0x26]	22866	1		T1	243		T13	757		T15	673
valid_sources[0x27]	22335	1		T1	235		T13	701		T15	684
valid_sources[0x28]	22623	1		T1	223		T9	2		T13	690
valid_sources[0x29]	21909	1		T1	225		T13	964		T15	717
valid_sources[0x2a]	21815	1		T1	215		T3	2		T13	579
valid_sources[0x2b]	20537	1		T1	220		T13	665		T15	627
valid_sources[0x2c]	22529	1		T1	264		T7	3		T13	1544
valid_sources[0x2d]	21831	1		T1	224		T13	1234		T15	668
valid_sources[0x2e]	22139	1		T1	224		T5	360		T8	5
valid_sources[0x2f]	20688	1		T1	213		T13	136		T15	647
valid_sources[0x30]	21357	1		T1	228		T13	370		T15	667
valid_sources[0x31]	22441	1		T1	222		T13	923		T15	666
valid_sources[0x32]	23285	1		T1	218		T9	1		T13	878
valid_sources[0x33]	21693	1		T1	167		T13	463		T15	665
valid_sources[0x34]	21693	1		T1	208		T13	457		T15	657
valid_sources[0x35]	21036	1		T1	223		T13	428		T15	647
valid_sources[0x36]	21273	1		T1	202		T13	757		T15	686
valid_sources[0x37]	24263	1		T1	238		T13	992		T15	645
valid_sources[0x38]	21804	1		T1	238		T13	751		T15	587
valid_sources[0x39]	21273	1		T1	219		T13	738		T15	640
valid_sources[0x3a]	21643	1		T1	211		T13	162		T15	684
valid_sources[0x3b]	21279	1		T1	230		T13	480		T15	657
valid_sources[0x3c]	20918	1		T1	230		T13	536		T15	677
valid_sources[0x3d]	20917	1		T1	213		T13	369		T15	677
valid_sources[0x3e]	20792	1		T1	218		T3	1		T13	383
valid_sources[0x3f]	20658	1		T1	256		T3	1		T13	738
valid_sources[0x40]	21978	1		T1	231		T13	533		T15	673
valid_sources[0x41]	20885	1		T1	223		T11	3		T13	755
valid_sources[0x42]	20601	1		T1	207		T13	462		T15	653
valid_sources[0x43]	21437	1		T1	242		T13	1077		T15	641
valid_sources[0x44]	21475	1		T1	217		T13	333		T15	693
valid_sources[0x45]	22890	1		T1	201		T13	736		T15	682
valid_sources[0x46]	22667	1		T1	225		T13	800		T15	695
valid_sources[0x47]	22193	1		T1	212		T13	499		T15	634
valid_sources[0x48]	21142	1		T1	191		T13	313		T15	632
valid_sources[0x49]	23500	1		T1	208		T13	548		T15	624
valid_sources[0x4a]	22424	1		T1	203		T2	2		T13	1096
valid_sources[0x4b]	22377	1		T1	239		T6	2		T13	1109
valid_sources[0x4c]	21134	1		T1	226		T13	238		T14	1
valid_sources[0x4d]	21662	1		T1	205		T12	1		T13	314
valid_sources[0x4e]	21738	1		T1	225		T13	679		T15	645
valid_sources[0x4f]	21656	1		T1	220		T13	849		T15	653
valid_sources[0x50]	20694	1		T1	217		T2	1		T13	518
valid_sources[0x51]	21554	1		T1	208		T13	567		T15	673
valid_sources[0x52]	22175	1		T1	217		T13	445		T15	682
valid_sources[0x53]	21315	1		T1	246		T13	437		T15	635
valid_sources[0x54]	22178	1		T1	225		T13	1449		T15	668
valid_sources[0x55]	21825	1		T1	252		T31	1		T12	1
valid_sources[0x56]	21145	1		T1	224		T13	459		T15	691
valid_sources[0x57]	20974	1		T1	235		T12	2		T13	716
valid_sources[0x58]	21299	1		T1	214		T12	1		T13	488
valid_sources[0x59]	21926	1		T1	213		T12	1		T13	426
valid_sources[0x5a]	21988	1		T1	242		T7	1		T13	737
valid_sources[0x5b]	23628	1		T1	221		T9	3		T13	1125
valid_sources[0x5c]	20070	1		T1	207		T3	2		T13	345
valid_sources[0x5d]	22293	1		T1	209		T3	1		T13	941
valid_sources[0x5e]	21395	1		T1	223		T13	300		T15	664
valid_sources[0x5f]	23921	1		T1	211		T8	1		T13	823
valid_sources[0x60]	20964	1		T1	208		T13	449		T15	706
valid_sources[0x61]	22247	1		T1	225		T13	967		T15	665
valid_sources[0x62]	22206	1		T1	236		T13	431		T15	683
valid_sources[0x63]	23257	1		T1	214		T13	1436		T15	680
valid_sources[0x64]	21366	1		T1	187		T13	151		T15	718
valid_sources[0x65]	21387	1		T1	208		T13	509		T15	667
valid_sources[0x66]	20741	1		T1	215		T13	686		T15	655
valid_sources[0x67]	21021	1		T1	214		T13	167		T15	668
valid_sources[0x68]	21832	1		T1	195		T11	1		T13	1027
valid_sources[0x69]	24179	1		T1	222		T13	749		T15	679
valid_sources[0x6a]	22231	1		T1	223		T12	1		T13	567
valid_sources[0x6b]	21007	1		T1	238		T12	1		T13	389
valid_sources[0x6c]	21553	1		T1	224		T13	458		T15	670
valid_sources[0x6d]	21485	1		T1	188		T31	5		T13	423
valid_sources[0x6e]	23644	1		T1	190		T13	1160		T15	681
valid_sources[0x6f]	20872	1		T1	209		T13	927		T15	662
valid_sources[0x70]	21716	1		T1	211		T3	1		T11	2
valid_sources[0x71]	21889	1		T1	240		T13	384		T14	2
valid_sources[0x72]	22177	1		T1	211		T13	1134		T15	673
valid_sources[0x73]	22812	1		T1	243		T3	1		T13	1129
valid_sources[0x74]	20333	1		T1	223		T7	3		T13	612
valid_sources[0x75]	20505	1		T1	194		T13	420		T15	650
valid_sources[0x76]	21164	1		T1	202		T13	721		T15	669
valid_sources[0x77]	21721	1		T1	226		T13	767		T15	662
valid_sources[0x78]	22047	1		T1	222		T13	199		T15	630
valid_sources[0x79]	21676	1		T1	225		T3	1		T7	1
valid_sources[0x7a]	21264	1		T1	211		T11	1		T13	686
valid_sources[0x7b]	22116	1		T1	181		T3	2		T13	658
valid_sources[0x7c]	22381	1		T1	237		T13	322		T14	1
valid_sources[0x7d]	22623	1		T1	225		T9	1		T13	1263
valid_sources[0x7e]	20784	1		T1	219		T13	231		T15	611
valid_sources[0x7f]	20376	1		T1	224		T3	1		T13	692
valid_sources[0x80]	23210	1		T1	213		T13	1454		T15	657

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1287456

1

T1

12865

T3

1

T5

14

values[0x0]

all_enables

biggest_size

1938166

1

T1

19765

T2

7

T3

7

values[0x1]

all_enables

biggest_size

1938228

1

T1

19318

T2

7

T3

7