Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	750484459	6173949	0	0
wdog_bark_thold_rd_A	750484459	95995	0	0
wdog_bite_thold_rd_A	750484459	81856	0	0
wdog_ctrl_rd_A	750484459	83074	0	0
wdog_regwen_rd_A	750484459	95565	0	0
wkup_ctrl_rd_A	750484459	82620	0	0
wkup_thold_hi_rd_A	750484459	94410	0	0
wkup_thold_lo_rd_A	750484459	82979	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	6173949	0	0
T1	244652	67437	0	0
T2	56243	0	0	0
T3	10238	0	0	0
T4	40905	0	0	0
T5	106467	0	0	0
T6	41523	0	0	0
T7	12448	0	0	0
T8	519548	0	0	0
T9	18898	0	0	0
T10	52071	0	0	0
T13	0	200888	0	0
T15	0	180893	0	0
T38	0	198088	0	0
T39	0	43097	0	0
T40	0	276753	0	0
T41	0	331548	0	0
T42	0	40496	0	0
T43	0	212149	0	0
T44	0	191251	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	95995	0	0
T15	814811	18034	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2465	0	0
T45	11318	0	0	0
T56	0	7878	0	0
T83	0	8985	0	0
T84	0	1572	0	0
T85	0	2962	0	0
T86	0	5295	0	0
T87	0	12428	0	0
T88	0	8700	0	0
T89	0	5497	0	0
T90	250525	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	81856	0	0
T15	814811	15340	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2132	0	0
T45	11318	0	0	0
T56	0	6662	0	0
T83	0	7514	0	0
T84	0	1285	0	0
T85	0	2533	0	0
T86	0	4230	0	0
T87	0	10641	0	0
T88	0	7307	0	0
T89	0	4803	0	0
T90	250525	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	83074	0	0
T15	814811	15378	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2046	0	0
T45	11318	0	0	0
T56	0	7002	0	0
T83	0	8134	0	0
T84	0	1299	0	0
T85	0	2490	0	0
T86	0	4312	0	0
T87	0	10857	0	0
T88	0	7381	0	0
T89	0	4604	0	0
T90	250525	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	95565	0	0
T15	814811	17673	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2370	0	0
T45	11318	0	0	0
T56	0	7908	0	0
T83	0	9201	0	0
T84	0	1583	0	0
T85	0	2760	0	0
T86	0	5128	0	0
T87	0	12764	0	0
T88	0	8542	0	0
T89	0	5470	0	0
T90	250525	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	82620	0	0
T15	814811	16047	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	1968	0	0
T45	11318	0	0	0
T56	0	7211	0	0
T83	0	7688	0	0
T84	0	1259	0	0
T85	0	2456	0	0
T86	0	4390	0	0
T87	0	10562	0	0
T88	0	7146	0	0
T89	0	4951	0	0
T90	250525	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	94410	0	0
T15	814811	18023	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2343	0	0
T45	11318	0	0	0
T56	0	7765	0	0
T83	0	8707	0	0
T84	0	1275	0	0
T85	0	2819	0	0
T86	0	5024	0	0
T87	0	12429	0	0
T88	0	8660	0	0
T89	0	5653	0	0
T90	250525	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	750484459	82979	0	0
T15	814811	15431	0	0
T16	367458	0	0	0
T23	10147	0	0	0
T24	14032	0	0	0
T25	265745	0	0	0
T26	59672	0	0	0
T27	15329	0	0	0
T28	17500	0	0	0
T39	0	2132	0	0
T45	11318	0	0	0
T56	0	6790	0	0
T83	0	7565	0	0
T84	0	1275	0	0
T85	0	2390	0	0
T86	0	4244	0	0
T87	0	11219	0	0
T88	0	7653	0	0
T89	0	4856	0	0
T90	250525	0	0	0