Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	375790	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4594022	1		T1	16		T2	11		T3	95045

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1221326	1		T1	1		T2	1		T3	25214
values[0x0]	1754998	1		T1	11		T2	10		T3	36173
values[0x1]	1993488	1		T1	10		T2	8		T3	40990

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167129	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4802683	1		T1	16		T2	12		T3	99224

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18559	1		T3	255		T8	2		T12	111
valid_sources[0x01]	19344	1		T3	414		T8	2		T12	127
valid_sources[0x02]	19352	1		T3	796		T7	1		T8	1
valid_sources[0x03]	19756	1		T3	711		T8	2		T12	206
valid_sources[0x04]	17601	1		T2	2		T3	507		T4	1
valid_sources[0x05]	19672	1		T3	469		T8	3		T12	28
valid_sources[0x06]	19508	1		T3	411		T8	1		T12	21
valid_sources[0x07]	20454	1		T3	340		T6	1		T8	2
valid_sources[0x08]	18928	1		T3	307		T8	3		T12	92
valid_sources[0x09]	19385	1		T3	359		T8	1		T12	87
valid_sources[0x0a]	18807	1		T1	6		T3	462		T8	1
valid_sources[0x0b]	19943	1		T3	203		T7	1		T8	2
valid_sources[0x0c]	22794	1		T3	634		T12	86		T14	621
valid_sources[0x0d]	18826	1		T2	1		T3	273		T8	1
valid_sources[0x0e]	19203	1		T3	254		T8	3		T9	1
valid_sources[0x0f]	19715	1		T3	206		T8	2		T12	512
valid_sources[0x10]	20671	1		T3	638		T8	2		T12	39
valid_sources[0x11]	19574	1		T3	427		T8	1		T12	268
valid_sources[0x12]	19706	1		T3	824		T8	4		T12	209
valid_sources[0x13]	18512	1		T2	1		T3	462		T8	3
valid_sources[0x14]	19058	1		T3	361		T7	1		T12	166
valid_sources[0x15]	18930	1		T3	316		T7	1		T12	435
valid_sources[0x16]	19722	1		T3	360		T4	1		T8	1
valid_sources[0x17]	18970	1		T2	1		T3	109		T8	1
valid_sources[0x18]	18983	1		T3	484		T12	238		T14	587
valid_sources[0x19]	19210	1		T3	815		T4	1		T8	1
valid_sources[0x1a]	20392	1		T3	622		T7	1		T12	116
valid_sources[0x1b]	19469	1		T3	668		T8	1		T12	116
valid_sources[0x1c]	19336	1		T3	376		T12	401		T13	1
valid_sources[0x1d]	19270	1		T3	236		T8	5		T9	1
valid_sources[0x1e]	19187	1		T3	196		T5	1		T12	34
valid_sources[0x1f]	18981	1		T3	402		T8	2		T12	452
valid_sources[0x20]	20495	1		T3	371		T8	1		T9	1
valid_sources[0x21]	19082	1		T3	717		T8	1		T12	299
valid_sources[0x22]	19713	1		T3	323		T4	1		T8	1
valid_sources[0x23]	21200	1		T3	751		T8	2		T12	356
valid_sources[0x24]	18215	1		T3	346		T6	6		T8	1
valid_sources[0x25]	18477	1		T3	464		T8	1		T9	1
valid_sources[0x26]	20520	1		T3	313		T8	1		T12	210
valid_sources[0x27]	18517	1		T3	312		T8	4		T12	103
valid_sources[0x28]	19134	1		T3	768		T8	2		T12	117
valid_sources[0x29]	20558	1		T3	163		T8	1		T12	429
valid_sources[0x2a]	21270	1		T3	587		T5	1		T8	4
valid_sources[0x2b]	20390	1		T3	575		T8	3		T12	104
valid_sources[0x2c]	21089	1		T2	1		T3	332		T8	1
valid_sources[0x2d]	19089	1		T3	477		T8	1		T12	4
valid_sources[0x2e]	18546	1		T3	478		T8	1		T12	251
valid_sources[0x2f]	19858	1		T3	497		T8	1		T12	323
valid_sources[0x30]	19071	1		T3	627		T8	1		T12	221
valid_sources[0x31]	19457	1		T3	289		T8	2		T10	323
valid_sources[0x32]	19426	1		T3	47		T12	150		T17	3
valid_sources[0x33]	20112	1		T3	490		T4	1		T12	114
valid_sources[0x34]	19142	1		T3	197		T12	246		T17	2
valid_sources[0x35]	19554	1		T3	87		T8	1		T12	300
valid_sources[0x36]	19659	1		T3	383		T12	355		T14	741
valid_sources[0x37]	20795	1		T3	628		T8	1		T12	757
valid_sources[0x38]	18871	1		T3	604		T5	1		T8	2
valid_sources[0x39]	18875	1		T3	305		T8	2		T12	26
valid_sources[0x3a]	19699	1		T3	445		T7	1		T8	1
valid_sources[0x3b]	18451	1		T3	324		T8	1		T12	11
valid_sources[0x3c]	19377	1		T3	492		T5	1		T12	4
valid_sources[0x3d]	20855	1		T3	663		T5	1		T8	1
valid_sources[0x3e]	21850	1		T3	752		T4	1		T7	1
valid_sources[0x3f]	19767	1		T3	520		T8	2		T12	51
valid_sources[0x40]	19683	1		T3	290		T8	2		T12	377
valid_sources[0x41]	19745	1		T3	165		T12	163		T13	1
valid_sources[0x42]	19126	1		T3	571		T8	2		T12	138
valid_sources[0x43]	18987	1		T3	157		T8	4		T12	20
valid_sources[0x44]	20147	1		T3	75		T12	7		T17	2
valid_sources[0x45]	19509	1		T3	350		T12	62		T17	1
valid_sources[0x46]	19257	1		T3	215		T4	1		T12	649
valid_sources[0x47]	18356	1		T3	263		T6	9		T8	2
valid_sources[0x48]	18490	1		T3	402		T8	2		T9	1
valid_sources[0x49]	19460	1		T3	273		T8	2		T12	127
valid_sources[0x4a]	18135	1		T3	267		T8	5		T9	2
valid_sources[0x4b]	19396	1		T3	421		T8	3		T12	123
valid_sources[0x4c]	20067	1		T3	623		T8	2		T12	11
valid_sources[0x4d]	19132	1		T3	448		T12	50		T14	645
valid_sources[0x4e]	19071	1		T2	1		T3	141		T8	2
valid_sources[0x4f]	19967	1		T3	676		T8	3		T12	425
valid_sources[0x50]	19273	1		T3	474		T8	2		T12	5
valid_sources[0x51]	20757	1		T3	443		T4	2		T5	1
valid_sources[0x52]	19832	1		T3	708		T5	2		T8	2
valid_sources[0x53]	19155	1		T3	508		T12	210		T17	1
valid_sources[0x54]	18499	1		T3	249		T8	4		T12	4
valid_sources[0x55]	18965	1		T3	624		T8	2		T12	72
valid_sources[0x56]	19503	1		T3	472		T8	2		T12	175
valid_sources[0x57]	19429	1		T3	146		T4	1		T5	1
valid_sources[0x58]	19709	1		T2	1		T3	511		T8	1
valid_sources[0x59]	20015	1		T3	269		T8	3		T12	19
valid_sources[0x5a]	18413	1		T3	307		T8	1		T12	406
valid_sources[0x5b]	19322	1		T3	332		T8	2		T12	204
valid_sources[0x5c]	19515	1		T3	106		T4	2		T8	1
valid_sources[0x5d]	17218	1		T3	349		T8	1		T12	42
valid_sources[0x5e]	18505	1		T3	390		T12	6		T13	1
valid_sources[0x5f]	20200	1		T3	512		T8	4		T12	175
valid_sources[0x60]	18727	1		T3	337		T8	1		T9	1
valid_sources[0x61]	17548	1		T3	521		T12	91		T17	1
valid_sources[0x62]	19408	1		T3	142		T8	1		T12	268
valid_sources[0x63]	19106	1		T3	180		T12	8		T14	688
valid_sources[0x64]	17136	1		T3	372		T8	3		T12	63
valid_sources[0x65]	18654	1		T3	448		T8	1		T12	30
valid_sources[0x66]	20143	1		T3	272		T8	4		T12	65
valid_sources[0x67]	19134	1		T3	360		T8	2		T12	389
valid_sources[0x68]	19436	1		T3	448		T5	1		T8	4
valid_sources[0x69]	20919	1		T3	225		T8	4		T12	551
valid_sources[0x6a]	18495	1		T3	309		T8	1		T12	6
valid_sources[0x6b]	18917	1		T3	600		T8	1		T12	347
valid_sources[0x6c]	19818	1		T3	206		T8	1		T12	32
valid_sources[0x6d]	18691	1		T3	593		T5	2		T8	2
valid_sources[0x6e]	19686	1		T3	519		T8	1		T12	334
valid_sources[0x6f]	19399	1		T3	310		T7	1		T8	1
valid_sources[0x70]	19202	1		T3	113		T8	3		T12	16
valid_sources[0x71]	19650	1		T3	578		T8	3		T12	33
valid_sources[0x72]	19372	1		T3	433		T8	1		T12	8
valid_sources[0x73]	17822	1		T3	357		T8	1		T12	1
valid_sources[0x74]	18400	1		T3	926		T8	2		T12	250
valid_sources[0x75]	17293	1		T3	358		T12	128		T14	630
valid_sources[0x76]	21284	1		T3	774		T8	2		T12	529
valid_sources[0x77]	19291	1		T3	395		T8	1		T12	222
valid_sources[0x78]	20394	1		T3	454		T8	1		T12	8
valid_sources[0x79]	17485	1		T3	47		T8	1		T12	45
valid_sources[0x7a]	17927	1		T3	619		T12	101		T17	5
valid_sources[0x7b]	19548	1		T2	1		T3	65		T8	4
valid_sources[0x7c]	19352	1		T3	226		T5	1		T8	1
valid_sources[0x7d]	19817	1		T3	308		T4	1		T12	333
valid_sources[0x7e]	19775	1		T3	183		T8	3		T12	240
valid_sources[0x7f]	19822	1		T3	456		T8	2		T12	224
valid_sources[0x80]	21189	1		T3	453		T5	1		T12	65

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1145459

1

T1

1

T3

23742

T4

1

values[0x0]

all_enables

biggest_size

1723681

1

T1

8

T2

5

T3

35631

values[0x1]

all_enables

biggest_size

1724882

1

T1

7

T2

6

T3

35672