Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	634036572	5478100	0	0
wdog_bark_thold_rd_A	634036572	58372	0	0
wdog_bite_thold_rd_A	634036572	52240	0	0
wdog_ctrl_rd_A	634036572	51327	0	0
wdog_regwen_rd_A	634036572	58288	0	0
wkup_ctrl_rd_A	634036572	51062	0	0
wkup_thold_hi_rd_A	634036572	57817	0	0
wkup_thold_lo_rd_A	634036572	51192	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	5478100	0	0
T3	501039	113608	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	46459	0	0
T14	0	184808	0	0
T23	0	185706	0	0
T29	0	38477	0	0
T30	0	155723	0	0
T31	0	131420	0	0
T32	0	55128	0	0
T33	0	31214	0	0
T34	0	77597	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	58372	0	0
T3	501039	11112	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3677	0	0
T91	0	2861	0	0
T95	0	2343	0	0
T96	0	13752	0	0
T97	0	3354	0	0
T98	0	2377	0	0
T99	0	5570	0	0
T100	0	2286	0	0
T101	0	1077	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	52240	0	0
T3	501039	9904	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3293	0	0
T91	0	2330	0	0
T95	0	2061	0	0
T96	0	12096	0	0
T97	0	3185	0	0
T98	0	2458	0	0
T99	0	5227	0	0
T100	0	2068	0	0
T101	0	960	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	51327	0	0
T3	501039	9622	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3198	0	0
T91	0	2296	0	0
T95	0	1907	0	0
T96	0	11977	0	0
T97	0	2963	0	0
T98	0	2200	0	0
T99	0	5205	0	0
T100	0	2093	0	0
T101	0	947	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	58288	0	0
T3	501039	11385	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3392	0	0
T91	0	2786	0	0
T95	0	2149	0	0
T96	0	13613	0	0
T97	0	3388	0	0
T98	0	2598	0	0
T99	0	5970	0	0
T100	0	2344	0	0
T101	0	1122	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	51062	0	0
T3	501039	9871	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3361	0	0
T91	0	2417	0	0
T95	0	1862	0	0
T96	0	11687	0	0
T97	0	2982	0	0
T98	0	2294	0	0
T99	0	4840	0	0
T100	0	1921	0	0
T101	0	1026	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	57817	0	0
T3	501039	10866	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3868	0	0
T91	0	2782	0	0
T95	0	2355	0	0
T96	0	13467	0	0
T97	0	3346	0	0
T98	0	2328	0	0
T99	0	5950	0	0
T100	0	2370	0	0
T101	0	1296	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634036572	51192	0	0
T3	501039	9111	0	0
T4	127233	0	0	0
T5	334032	0	0	0
T6	164703	0	0	0
T7	38846	0	0	0
T8	674209	0	0	0
T9	596771	0	0	0
T10	257439	0	0	0
T11	379232	0	0	0
T12	125846	0	0	0
T29	0	3298	0	0
T91	0	2245	0	0
T95	0	2048	0	0
T96	0	12335	0	0
T97	0	3104	0	0
T98	0	2269	0	0
T99	0	5253	0	0
T100	0	2030	0	0
T101	0	1080	0	0