Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	556495653	4760463	0	0
wdog_bark_thold_rd_A	556495653	103967	0	0
wdog_bite_thold_rd_A	556495653	90750	0	0
wdog_ctrl_rd_A	556495653	91831	0	0
wdog_regwen_rd_A	556495653	104459	0	0
wkup_ctrl_rd_A	556495653	91219	0	0
wkup_thold_hi_rd_A	556495653	105626	0	0
wkup_thold_lo_rd_A	556495653	91235	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	4760463	0	0
T1	199793	37189	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	62586	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	88911	0	0
T31	0	64302	0	0
T40	0	83460	0	0
T41	0	71403	0	0
T42	0	89977	0	0
T43	0	322710	0	0
T44	0	120668	0	0
T45	0	161567	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	103967	0	0
T1	199793	3460	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	6182	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4963	0	0
T31	0	6295	0	0
T40	0	8082	0	0
T42	0	4600	0	0
T44	0	6593	0	0
T92	0	5433	0	0
T93	0	17789	0	0
T94	0	3484	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	90750	0	0
T1	199793	3229	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	5693	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	3869	0	0
T31	0	5649	0	0
T40	0	7420	0	0
T42	0	3896	0	0
T44	0	5593	0	0
T92	0	4691	0	0
T93	0	15514	0	0
T94	0	2715	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	91831	0	0
T1	199793	3049	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	5641	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4332	0	0
T31	0	5810	0	0
T40	0	7707	0	0
T42	0	3816	0	0
T44	0	5559	0	0
T92	0	4614	0	0
T93	0	15738	0	0
T94	0	3033	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	104459	0	0
T1	199793	3579	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	6643	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4943	0	0
T31	0	7002	0	0
T40	0	8206	0	0
T42	0	4630	0	0
T44	0	6439	0	0
T92	0	5357	0	0
T93	0	17165	0	0
T94	0	3387	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	91219	0	0
T1	199793	3295	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	5791	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4266	0	0
T31	0	5407	0	0
T40	0	7537	0	0
T42	0	3905	0	0
T44	0	5432	0	0
T92	0	4594	0	0
T93	0	15694	0	0
T94	0	3106	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	105626	0	0
T1	199793	3961	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	6302	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4842	0	0
T31	0	6957	0	0
T40	0	8251	0	0
T42	0	4580	0	0
T44	0	6713	0	0
T92	0	5342	0	0
T93	0	17814	0	0
T94	0	3285	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	556495653	91235	0	0
T1	199793	3212	0	0
T2	628189	0	0	0
T3	182696	0	0	0
T4	666529	0	0	0
T5	50771	0	0	0
T6	139447	0	0	0
T7	284652	5764	0	0
T8	160044	0	0	0
T9	236906	0	0	0
T10	362862	4338	0	0
T31	0	5753	0	0
T40	0	7242	0	0
T42	0	3889	0	0
T44	0	5509	0	0
T92	0	4997	0	0
T93	0	15680	0	0
T94	0	3074	0	0