Module Definition
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Module : aon_timer_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_core 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.56 96.15 66.67 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : aon_timer_core
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
ALWAYS4644100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5711100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
48 1 1
49 1 1
MISSING_ELSE
53 1 1
54 1 1
57 1 1
61 1 1
62 1 1
65 1 1
72 1 1
76 1 1
77 1 1
80 1 1
82 1 1
84 1 1


Cond Coverage for Module : aon_timer_core
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       41
 EXPRESSION (wkup_incr ? 12'b0 : ((prescale_count_q + 12'b1)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       65
 EXPRESSION (wkup_incr & (wkup_count >= wkup_thold))
             ----1----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       80
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bark_thold.q))
             ----1----   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T5

 LINE       82
 EXPRESSION (wdog_incr & (reg2hw_i.wdog_count.q >= reg2hw_i.wdog_bite_thold.q))
             ----1----   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T7
11CoveredT1,T2,T5

Branch Coverage for Module : aon_timer_core
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 41 2 2 100.00
IF 46 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv' or '../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 41 (wkup_incr) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 46 if ((!rst_aon_ni)) -2-: 48 if (prescale_en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%