Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
12274 |
1 |
|
T1 |
302 |
|
T7 |
112 |
|
T10 |
48 |
all_values[1] |
12274 |
1 |
|
T1 |
302 |
|
T7 |
112 |
|
T10 |
48 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_intr_en
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
[auto[1]] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24548 |
1 |
|
T1 |
604 |
|
T7 |
224 |
|
T10 |
96 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6448 |
1 |
|
T1 |
144 |
|
T7 |
72 |
|
T10 |
8 |
auto[1] |
18100 |
1 |
|
T1 |
460 |
|
T7 |
152 |
|
T10 |
88 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13850 |
1 |
|
T1 |
354 |
|
T7 |
134 |
|
T10 |
52 |
auto[1] |
10698 |
1 |
|
T1 |
250 |
|
T7 |
90 |
|
T10 |
44 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
6 |
6 |
50.00 |
6 |
Automatically Generated Cross Bins |
12 |
6 |
6 |
50.00 |
6 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
* |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
4 |
* |
[auto[1]] |
[auto[1]] |
[auto[1]] |
-- |
-- |
2 |
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
3084 |
1 |
|
T1 |
82 |
|
T7 |
40 |
|
T10 |
6 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
3788 |
1 |
|
T1 |
104 |
|
T7 |
30 |
|
T10 |
24 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
5402 |
1 |
|
T1 |
116 |
|
T7 |
42 |
|
T10 |
18 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
3364 |
1 |
|
T1 |
62 |
|
T7 |
32 |
|
T10 |
2 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
3614 |
1 |
|
T1 |
106 |
|
T7 |
32 |
|
T10 |
20 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
5296 |
1 |
|
T1 |
134 |
|
T7 |
48 |
|
T10 |
26 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |