ASSERT | PROPERTIES | SEQUENCES | |
Total | 396 | 0 | 10 |
Category 0 | 396 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 396 | 0 | 10 |
Severity 0 | 396 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 396 | 100.00 |
Uncovered | 2 | 0.51 |
Success | 394 | 99.49 |
Failure | 0 | 0.00 |
Incomplete | 5 | 1.26 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3282083 | 0 | 0 | 417 | |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.HwIdSelCheck_A | 0 | 0 | 3282083 | 0 | 0 | 0 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_sync_escalate_en.gen_flops.OutputDelay_A | 0 | 0 | 3227765 | 3169046 | 0 | 716 | |
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3282083 | 432 | 0 | 417 | |
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3282083 | 1296 | 0 | 417 | |
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3282083 | 0 | 0 | 417 | |
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 3282083 | 2772 | 0 | 417 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 692750170 | 352277 | 352277 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 692750170 | 635 | 635 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 692750170 | 1667 | 1667 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 692750170 | 991 | 991 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 692750170 | 1623 | 1623 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 692750170 | 803 | 803 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 692750170 | 740 | 740 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 692750170 | 1959 | 1959 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 692750170 | 2967 | 2967 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 692750170 | 15134 | 15134 | 300 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 692750170 | 352277 | 352277 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 692750170 | 635 | 635 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 692750170 | 1667 | 1667 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 692750170 | 991 | 991 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 692750170 | 1623 | 1623 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 692750170 | 803 | 803 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 692750170 | 740 | 740 | 2 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 692750170 | 1959 | 1959 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 692750170 | 2967 | 2967 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 692750170 | 15134 | 15134 | 300 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |