Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 417
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T277 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4075796385 May 07 03:21:46 PM PDT 24 May 07 03:21:49 PM PDT 24 431901577 ps
T278 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.41573312 May 07 03:21:53 PM PDT 24 May 07 03:21:57 PM PDT 24 500402473 ps
T110 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4083153996 May 07 03:21:26 PM PDT 24 May 07 03:21:28 PM PDT 24 401920590 ps
T111 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.96537033 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 501333846 ps
T77 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2510501998 May 07 03:21:18 PM PDT 24 May 07 03:21:21 PM PDT 24 3042205831 ps
T279 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.946615653 May 07 03:21:26 PM PDT 24 May 07 03:21:28 PM PDT 24 737926155 ps
T280 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.91285823 May 07 03:21:55 PM PDT 24 May 07 03:21:58 PM PDT 24 525599204 ps
T63 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2899248917 May 07 03:21:36 PM PDT 24 May 07 03:21:39 PM PDT 24 357937842 ps
T78 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1129617076 May 07 03:21:38 PM PDT 24 May 07 03:21:40 PM PDT 24 349374257 ps
T281 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2357538168 May 07 03:21:25 PM PDT 24 May 07 03:21:27 PM PDT 24 328384675 ps
T40 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3116261464 May 07 03:21:37 PM PDT 24 May 07 03:21:46 PM PDT 24 4254706196 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2398175454 May 07 03:21:30 PM PDT 24 May 07 03:21:32 PM PDT 24 543220342 ps
T282 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2058050825 May 07 03:21:22 PM PDT 24 May 07 03:21:25 PM PDT 24 319235931 ps
T41 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.93136236 May 07 03:21:35 PM PDT 24 May 07 03:21:37 PM PDT 24 4983691530 ps
T283 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.743470050 May 07 03:21:49 PM PDT 24 May 07 03:21:52 PM PDT 24 341156035 ps
T107 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3265675704 May 07 03:21:36 PM PDT 24 May 07 03:21:53 PM PDT 24 8233671475 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4111997464 May 07 03:21:36 PM PDT 24 May 07 03:21:38 PM PDT 24 362350292 ps
T109 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3808609591 May 07 03:21:18 PM PDT 24 May 07 03:21:22 PM PDT 24 8514580841 ps
T284 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1024885751 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 462684182 ps
T285 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2790271983 May 07 03:21:24 PM PDT 24 May 07 03:21:30 PM PDT 24 4445115992 ps
T286 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2077565354 May 07 03:21:29 PM PDT 24 May 07 03:21:31 PM PDT 24 395014947 ps
T287 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3041495263 May 07 03:21:31 PM PDT 24 May 07 03:21:35 PM PDT 24 474505897 ps
T80 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.581415687 May 07 03:21:21 PM PDT 24 May 07 03:21:27 PM PDT 24 2641422100 ps
T288 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.303194143 May 07 03:21:21 PM PDT 24 May 07 03:21:24 PM PDT 24 461858335 ps
T81 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.87640750 May 07 03:21:32 PM PDT 24 May 07 03:21:35 PM PDT 24 2832785426 ps
T289 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1913356459 May 07 03:21:33 PM PDT 24 May 07 03:21:35 PM PDT 24 442577873 ps
T290 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.105086684 May 07 03:21:43 PM PDT 24 May 07 03:21:45 PM PDT 24 452721365 ps
T291 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1325885206 May 07 03:21:57 PM PDT 24 May 07 03:22:00 PM PDT 24 270847145 ps
T292 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3092501770 May 07 03:21:49 PM PDT 24 May 07 03:21:51 PM PDT 24 413414209 ps
T293 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2869243534 May 07 03:21:25 PM PDT 24 May 07 03:21:28 PM PDT 24 326400301 ps
T65 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3538098875 May 07 03:21:31 PM PDT 24 May 07 03:21:33 PM PDT 24 433712071 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3398330057 May 07 03:21:36 PM PDT 24 May 07 03:21:38 PM PDT 24 585213651 ps
T108 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4127576329 May 07 03:21:54 PM PDT 24 May 07 03:22:01 PM PDT 24 8680442977 ps
T295 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1095084943 May 07 03:21:43 PM PDT 24 May 07 03:21:46 PM PDT 24 381282919 ps
T296 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1212723164 May 07 03:21:43 PM PDT 24 May 07 03:21:45 PM PDT 24 2531625186 ps
T297 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3526779854 May 07 03:21:30 PM PDT 24 May 07 03:21:35 PM PDT 24 537956827 ps
T298 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1862277915 May 07 03:21:44 PM PDT 24 May 07 03:21:45 PM PDT 24 303091058 ps
T299 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.207551153 May 07 03:21:21 PM PDT 24 May 07 03:21:24 PM PDT 24 549806703 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2755372902 May 07 03:21:18 PM PDT 24 May 07 03:21:21 PM PDT 24 457919992 ps
T301 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.93012967 May 07 03:21:48 PM PDT 24 May 07 03:21:50 PM PDT 24 408739133 ps
T302 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2468627040 May 07 03:21:45 PM PDT 24 May 07 03:21:48 PM PDT 24 449329765 ps
T303 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2191600172 May 07 03:21:55 PM PDT 24 May 07 03:21:59 PM PDT 24 319306884 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.106638517 May 07 03:21:20 PM PDT 24 May 07 03:21:24 PM PDT 24 1230187817 ps
T305 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4093219799 May 07 03:21:24 PM PDT 24 May 07 03:21:27 PM PDT 24 486379257 ps
T306 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2482702941 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 536464337 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1674901473 May 07 03:21:44 PM PDT 24 May 07 03:21:47 PM PDT 24 823472009 ps
T308 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.164488545 May 07 03:21:31 PM PDT 24 May 07 03:21:33 PM PDT 24 419133001 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.694725516 May 07 03:21:19 PM PDT 24 May 07 03:21:22 PM PDT 24 441061304 ps
T310 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1633609906 May 07 03:21:25 PM PDT 24 May 07 03:21:32 PM PDT 24 302844899 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1199719571 May 07 03:21:20 PM PDT 24 May 07 03:21:23 PM PDT 24 331829042 ps
T312 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.768556532 May 07 03:21:27 PM PDT 24 May 07 03:21:32 PM PDT 24 686561654 ps
T66 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.478899752 May 07 03:21:44 PM PDT 24 May 07 03:21:45 PM PDT 24 524641721 ps
T313 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.940733917 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 380793646 ps
T314 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.873481271 May 07 03:21:43 PM PDT 24 May 07 03:21:46 PM PDT 24 1224689101 ps
T315 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1867460640 May 07 03:21:39 PM PDT 24 May 07 03:21:43 PM PDT 24 324683433 ps
T316 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2042557065 May 07 03:21:21 PM PDT 24 May 07 03:21:24 PM PDT 24 1216525103 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1671545702 May 07 03:21:20 PM PDT 24 May 07 03:21:25 PM PDT 24 8279335957 ps
T67 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3716441488 May 07 03:21:30 PM PDT 24 May 07 03:21:33 PM PDT 24 402030629 ps
T318 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2577538841 May 07 03:21:38 PM PDT 24 May 07 03:21:40 PM PDT 24 1395382298 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3686649350 May 07 03:21:22 PM PDT 24 May 07 03:21:25 PM PDT 24 435720232 ps
T320 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1135433291 May 07 03:21:41 PM PDT 24 May 07 03:21:44 PM PDT 24 1330755900 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4173003687 May 07 03:21:28 PM PDT 24 May 07 03:21:31 PM PDT 24 4485281933 ps
T322 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.448876682 May 07 03:21:30 PM PDT 24 May 07 03:21:33 PM PDT 24 2375887349 ps
T323 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2680070910 May 07 03:21:41 PM PDT 24 May 07 03:21:43 PM PDT 24 388295298 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1046387734 May 07 03:21:20 PM PDT 24 May 07 03:21:23 PM PDT 24 357287797 ps
T325 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2622403376 May 07 03:21:34 PM PDT 24 May 07 03:21:40 PM PDT 24 8588847699 ps
T68 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2952490282 May 07 03:21:24 PM PDT 24 May 07 03:21:26 PM PDT 24 522789460 ps
T326 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3699663929 May 07 03:21:47 PM PDT 24 May 07 03:21:50 PM PDT 24 1521429720 ps
T327 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2788793516 May 07 03:21:18 PM PDT 24 May 07 03:21:21 PM PDT 24 726815846 ps
T328 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2473714038 May 07 03:21:29 PM PDT 24 May 07 03:21:32 PM PDT 24 472577609 ps
T329 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2438756929 May 07 03:21:25 PM PDT 24 May 07 03:21:38 PM PDT 24 7676064822 ps
T330 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3264160882 May 07 03:21:25 PM PDT 24 May 07 03:21:27 PM PDT 24 589594357 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3811084865 May 07 03:21:30 PM PDT 24 May 07 03:21:33 PM PDT 24 463292320 ps
T332 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3059991118 May 07 03:21:41 PM PDT 24 May 07 03:21:43 PM PDT 24 446672795 ps
T333 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1054058761 May 07 03:21:25 PM PDT 24 May 07 03:21:28 PM PDT 24 646198120 ps
T334 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1426071310 May 07 03:21:46 PM PDT 24 May 07 03:21:49 PM PDT 24 339566777 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2705599740 May 07 03:21:27 PM PDT 24 May 07 03:21:30 PM PDT 24 472675103 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2500429369 May 07 03:21:20 PM PDT 24 May 07 03:21:41 PM PDT 24 6987445557 ps
T337 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3840308703 May 07 03:21:42 PM PDT 24 May 07 03:21:48 PM PDT 24 8640049165 ps
T338 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2690149612 May 07 03:21:42 PM PDT 24 May 07 03:21:46 PM PDT 24 1458236139 ps
T339 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2253130166 May 07 03:21:44 PM PDT 24 May 07 03:21:46 PM PDT 24 568040276 ps
T340 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2766339497 May 07 03:21:25 PM PDT 24 May 07 03:21:29 PM PDT 24 776911324 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1397125125 May 07 03:21:33 PM PDT 24 May 07 03:21:41 PM PDT 24 4232002375 ps
T342 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1994335093 May 07 03:21:49 PM PDT 24 May 07 03:21:52 PM PDT 24 468025098 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.69601899 May 07 03:21:21 PM PDT 24 May 07 03:21:23 PM PDT 24 506646332 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2426730735 May 07 03:21:20 PM PDT 24 May 07 03:21:23 PM PDT 24 493260448 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.195832241 May 07 03:21:27 PM PDT 24 May 07 03:21:30 PM PDT 24 369346870 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1166647421 May 07 03:21:24 PM PDT 24 May 07 03:21:25 PM PDT 24 379787685 ps
T346 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1132377047 May 07 03:21:33 PM PDT 24 May 07 03:21:35 PM PDT 24 325447319 ps
T347 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.112760496 May 07 03:21:20 PM PDT 24 May 07 03:21:23 PM PDT 24 345389563 ps
T348 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2962466668 May 07 03:21:52 PM PDT 24 May 07 03:21:55 PM PDT 24 641959555 ps
T349 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.212192297 May 07 03:21:30 PM PDT 24 May 07 03:21:35 PM PDT 24 1281785548 ps
T350 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1212742055 May 07 03:21:20 PM PDT 24 May 07 03:21:23 PM PDT 24 340571840 ps
T351 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3450700025 May 07 03:21:56 PM PDT 24 May 07 03:21:59 PM PDT 24 274302803 ps
T352 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3853484497 May 07 03:21:44 PM PDT 24 May 07 03:21:47 PM PDT 24 449312397 ps
T353 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4046762757 May 07 03:21:43 PM PDT 24 May 07 03:21:45 PM PDT 24 337434287 ps
T354 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.740292171 May 07 03:21:42 PM PDT 24 May 07 03:21:44 PM PDT 24 358692369 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3686195024 May 07 03:21:22 PM PDT 24 May 07 03:21:24 PM PDT 24 349833154 ps
T356 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.753004599 May 07 03:21:42 PM PDT 24 May 07 03:21:43 PM PDT 24 427687993 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2620357979 May 07 03:21:36 PM PDT 24 May 07 03:21:38 PM PDT 24 471937617 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3187722009 May 07 03:21:21 PM PDT 24 May 07 03:21:24 PM PDT 24 799090825 ps
T359 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2634275102 May 07 03:21:44 PM PDT 24 May 07 03:21:47 PM PDT 24 2568159204 ps
T360 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2532832676 May 07 03:21:52 PM PDT 24 May 07 03:21:54 PM PDT 24 390600566 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3600977075 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 358843382 ps
T361 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2119985397 May 07 03:21:20 PM PDT 24 May 07 03:21:22 PM PDT 24 474914398 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.93420101 May 07 03:21:37 PM PDT 24 May 07 03:21:39 PM PDT 24 482281185 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3383847115 May 07 03:21:38 PM PDT 24 May 07 03:21:40 PM PDT 24 468905841 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2496095244 May 07 03:21:25 PM PDT 24 May 07 03:21:38 PM PDT 24 4661281560 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2817094882 May 07 03:21:17 PM PDT 24 May 07 03:21:19 PM PDT 24 334705874 ps
T365 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2996742315 May 07 03:21:21 PM PDT 24 May 07 03:21:23 PM PDT 24 484637217 ps
T366 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3588875850 May 07 03:21:45 PM PDT 24 May 07 03:21:48 PM PDT 24 759517746 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2951864806 May 07 03:21:24 PM PDT 24 May 07 03:21:26 PM PDT 24 353564883 ps
T368 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2539167868 May 07 03:21:27 PM PDT 24 May 07 03:21:29 PM PDT 24 589663909 ps
T369 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3287122556 May 07 03:21:37 PM PDT 24 May 07 03:21:40 PM PDT 24 4231595407 ps
T370 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2957181697 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 481283602 ps
T371 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3849224990 May 07 03:21:36 PM PDT 24 May 07 03:21:37 PM PDT 24 397816592 ps
T372 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3858034391 May 07 03:21:19 PM PDT 24 May 07 03:21:21 PM PDT 24 398930420 ps
T76 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1885528376 May 07 03:21:39 PM PDT 24 May 07 03:21:41 PM PDT 24 507839763 ps
T373 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3193337062 May 07 03:21:40 PM PDT 24 May 07 03:21:42 PM PDT 24 547608708 ps
T374 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.905211415 May 07 03:21:48 PM PDT 24 May 07 03:21:50 PM PDT 24 335668383 ps
T74 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3698291083 May 07 03:21:42 PM PDT 24 May 07 03:21:44 PM PDT 24 511672991 ps
T375 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4050118780 May 07 03:21:45 PM PDT 24 May 07 03:21:48 PM PDT 24 518002727 ps
T376 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3034188715 May 07 03:21:44 PM PDT 24 May 07 03:21:49 PM PDT 24 2281561511 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1764541036 May 07 03:21:26 PM PDT 24 May 07 03:21:29 PM PDT 24 500358226 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2688799499 May 07 03:21:23 PM PDT 24 May 07 03:21:25 PM PDT 24 474723483 ps
T379 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3977582034 May 07 03:21:48 PM PDT 24 May 07 03:21:50 PM PDT 24 374578695 ps
T380 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.349818552 May 07 03:21:25 PM PDT 24 May 07 03:21:28 PM PDT 24 453512239 ps
T381 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3787282635 May 07 03:21:54 PM PDT 24 May 07 03:21:58 PM PDT 24 435918847 ps
T382 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4294046467 May 07 03:21:33 PM PDT 24 May 07 03:21:34 PM PDT 24 491558095 ps
T383 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068050624 May 07 03:21:46 PM PDT 24 May 07 03:21:48 PM PDT 24 439442011 ps
T384 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1490435599 May 07 03:21:36 PM PDT 24 May 07 03:21:40 PM PDT 24 8723650131 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3541501780 May 07 03:21:19 PM PDT 24 May 07 03:21:21 PM PDT 24 328556167 ps
T385 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4200320709 May 07 03:21:27 PM PDT 24 May 07 03:21:41 PM PDT 24 8018010617 ps
T386 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1274822380 May 07 03:21:49 PM PDT 24 May 07 03:21:50 PM PDT 24 561366533 ps
T387 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3374816853 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 380382018 ps
T388 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1966484231 May 07 03:21:50 PM PDT 24 May 07 03:21:52 PM PDT 24 570948239 ps
T389 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.247811776 May 07 03:21:37 PM PDT 24 May 07 03:21:39 PM PDT 24 493552757 ps
T390 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.862807508 May 07 03:21:21 PM PDT 24 May 07 03:21:23 PM PDT 24 580274784 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1408287312 May 07 03:21:19 PM PDT 24 May 07 03:21:21 PM PDT 24 278534098 ps
T392 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1101974803 May 07 03:21:26 PM PDT 24 May 07 03:21:29 PM PDT 24 385433111 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.439443659 May 07 03:21:22 PM PDT 24 May 07 03:21:25 PM PDT 24 988299713 ps
T394 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1688927016 May 07 03:21:39 PM PDT 24 May 07 03:21:41 PM PDT 24 518248743 ps
T395 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3823447795 May 07 03:21:30 PM PDT 24 May 07 03:21:35 PM PDT 24 999077634 ps
T396 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3940234060 May 07 03:21:46 PM PDT 24 May 07 03:21:51 PM PDT 24 8059556126 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.447882838 May 07 03:21:26 PM PDT 24 May 07 03:21:32 PM PDT 24 2308404619 ps
T398 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2993083760 May 07 03:21:18 PM PDT 24 May 07 03:21:26 PM PDT 24 4533418755 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3790524590 May 07 03:21:19 PM PDT 24 May 07 03:21:22 PM PDT 24 745787786 ps
T400 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1109778130 May 07 03:21:31 PM PDT 24 May 07 03:21:34 PM PDT 24 512660837 ps
T401 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.419580899 May 07 03:21:35 PM PDT 24 May 07 03:21:38 PM PDT 24 545341343 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1973076061 May 07 03:21:17 PM PDT 24 May 07 03:21:29 PM PDT 24 12515967153 ps
T402 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1704692142 May 07 03:21:26 PM PDT 24 May 07 03:21:28 PM PDT 24 342171388 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2260964656 May 07 03:21:41 PM PDT 24 May 07 03:21:44 PM PDT 24 391402203 ps
T404 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.13090362 May 07 03:21:45 PM PDT 24 May 07 03:21:47 PM PDT 24 379600280 ps
T405 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1156844496 May 07 03:21:28 PM PDT 24 May 07 03:21:30 PM PDT 24 572938486 ps
T406 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3951843402 May 07 03:21:27 PM PDT 24 May 07 03:21:29 PM PDT 24 310396269 ps
T407 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1205965078 May 07 03:21:38 PM PDT 24 May 07 03:21:40 PM PDT 24 476444542 ps
T408 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1152446079 May 07 03:21:54 PM PDT 24 May 07 03:21:59 PM PDT 24 4382387794 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3531712611 May 07 03:21:19 PM PDT 24 May 07 03:21:25 PM PDT 24 8522143132 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.674640521 May 07 03:21:38 PM PDT 24 May 07 03:21:42 PM PDT 24 648555659 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3486419461 May 07 03:21:48 PM PDT 24 May 07 03:21:50 PM PDT 24 498365540 ps
T412 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.28196583 May 07 03:21:28 PM PDT 24 May 07 03:21:30 PM PDT 24 420751851 ps
T413 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3426622802 May 07 03:21:46 PM PDT 24 May 07 03:21:48 PM PDT 24 299450357 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2610776922 May 07 03:21:52 PM PDT 24 May 07 03:21:54 PM PDT 24 355413787 ps
T415 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.399549493 May 07 03:21:37 PM PDT 24 May 07 03:21:40 PM PDT 24 413581279 ps
T416 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1212628053 May 07 03:21:24 PM PDT 24 May 07 03:21:27 PM PDT 24 1189020023 ps
T417 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.250118974 May 07 03:21:53 PM PDT 24 May 07 03:21:56 PM PDT 24 318710969 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1974211463 May 07 03:21:21 PM PDT 24 May 07 03:21:30 PM PDT 24 2557680441 ps

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.664512287
Short name T7
Test name
Test status
Simulation time 53261513300 ps
CPU time 134.63 seconds
Started May 07 03:03:03 PM PDT 24
Finished May 07 03:05:19 PM PDT 24
Peak memory 198544 kb
Host smart-d38d0624-0803-4726-98fb-b61ab0638742
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664512287 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.664512287
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1165472113
Short name T39
Test name
Test status
Simulation time 7974796648 ps
CPU time 10.91 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 197916 kb
Host smart-02079650-88f7-4b9f-bb61-d96ea77742d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165472113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1165472113
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.4082508288
Short name T32
Test name
Test status
Simulation time 410792186378 ps
CPU time 432.24 seconds
Started May 07 03:02:42 PM PDT 24
Finished May 07 03:09:56 PM PDT 24
Peak memory 198500 kb
Host smart-07abf71a-5c5d-4054-93ea-a93c5cca26f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082508288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.4082508288
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3494342410
Short name T45
Test name
Test status
Simulation time 378538499657 ps
CPU time 305.97 seconds
Started May 07 03:02:25 PM PDT 24
Finished May 07 03:07:32 PM PDT 24
Peak memory 198540 kb
Host smart-a990c863-d9d3-4688-bb73-c261611131d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494342410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3494342410
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2491090130
Short name T10
Test name
Test status
Simulation time 324355917070 ps
CPU time 114.11 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:04:18 PM PDT 24
Peak memory 183840 kb
Host smart-4624817d-c794-4698-b8fe-443887970314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491090130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2491090130
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3538098875
Short name T65
Test name
Test status
Simulation time 433712071 ps
CPU time 0.92 seconds
Started May 07 03:21:31 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 183664 kb
Host smart-8ad8e8e0-a860-4c5f-8bad-7cfacc460014
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538098875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3538098875
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3897621210
Short name T15
Test name
Test status
Simulation time 4158644159 ps
CPU time 2.33 seconds
Started May 07 03:02:15 PM PDT 24
Finished May 07 03:02:19 PM PDT 24
Peak memory 214864 kb
Host smart-239a79c3-fc9f-489c-9ce6-89e046fc25bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897621210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3897621210
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2434469406
Short name T94
Test name
Test status
Simulation time 72389267673 ps
CPU time 521.59 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:11:17 PM PDT 24
Peak memory 198588 kb
Host smart-6507f041-393c-4ec6-ac94-d325ee01f587
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434469406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2434469406
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1688213746
Short name T1
Test name
Test status
Simulation time 398819434349 ps
CPU time 801.15 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:15:53 PM PDT 24
Peak memory 202084 kb
Host smart-dec70127-d982-4bee-abe9-78d923dbc746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688213746 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1688213746
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2936640531
Short name T104
Test name
Test status
Simulation time 50868331050 ps
CPU time 70.5 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:03:35 PM PDT 24
Peak memory 183568 kb
Host smart-28d9651e-a1fb-420a-babe-1858a8b80e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936640531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2936640531
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2426730735
Short name T69
Test name
Test status
Simulation time 493260448 ps
CPU time 1.49 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 193024 kb
Host smart-e014aae1-ec6e-4517-bf90-9a790e400716
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426730735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2426730735
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2500429369
Short name T336
Test name
Test status
Simulation time 6987445557 ps
CPU time 18.71 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:41 PM PDT 24
Peak memory 192172 kb
Host smart-4ac39618-5b11-493a-b973-6a0bc0eace0e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500429369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2500429369
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2042557065
Short name T316
Test name
Test status
Simulation time 1216525103 ps
CPU time 1.08 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 193120 kb
Host smart-963a26e1-1f90-4f67-9465-7b61c2b92132
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042557065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2042557065
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.694725516
Short name T309
Test name
Test status
Simulation time 441061304 ps
CPU time 1.37 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:22 PM PDT 24
Peak memory 196932 kb
Host smart-3a164712-a56b-41a6-bcbd-404c3f31529e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694725516 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.694725516
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.303194143
Short name T288
Test name
Test status
Simulation time 461858335 ps
CPU time 0.74 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 183744 kb
Host smart-ff55a643-f241-4924-b2b6-dd97cc6d6503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303194143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.303194143
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2817094882
Short name T364
Test name
Test status
Simulation time 334705874 ps
CPU time 0.64 seconds
Started May 07 03:21:17 PM PDT 24
Finished May 07 03:21:19 PM PDT 24
Peak memory 183592 kb
Host smart-a6c5c429-8037-4ccd-b2c6-2b496dec6e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817094882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2817094882
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2755372902
Short name T300
Test name
Test status
Simulation time 457919992 ps
CPU time 1.16 seconds
Started May 07 03:21:18 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 183512 kb
Host smart-98163cec-b82e-4d37-8f1c-36fa4e51b3cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755372902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2755372902
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3858034391
Short name T372
Test name
Test status
Simulation time 398930420 ps
CPU time 1.04 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 183580 kb
Host smart-91d32e56-a328-4230-8e96-4b180e51143c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858034391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3858034391
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.581415687
Short name T80
Test name
Test status
Simulation time 2641422100 ps
CPU time 4.44 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:27 PM PDT 24
Peak memory 194732 kb
Host smart-8502dfeb-0e61-4206-8db4-548ccb80089b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581415687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.581415687
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3790524590
Short name T399
Test name
Test status
Simulation time 745787786 ps
CPU time 2.54 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:22 PM PDT 24
Peak memory 198488 kb
Host smart-0c632114-e7df-4fdf-9988-8850789a276d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790524590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3790524590
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3531712611
Short name T409
Test name
Test status
Simulation time 8522143132 ps
CPU time 4.69 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 197816 kb
Host smart-dd1befb0-a183-4fc0-9167-237745254c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531712611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3531712611
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.862807508
Short name T390
Test name
Test status
Simulation time 580274784 ps
CPU time 0.75 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 193180 kb
Host smart-c42e584e-8b8e-41b6-927a-eefb2fd79523
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862807508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.862807508
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1973076061
Short name T71
Test name
Test status
Simulation time 12515967153 ps
CPU time 11.01 seconds
Started May 07 03:21:17 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 192204 kb
Host smart-629c1c53-6b3c-4138-91ca-8ea6c1002784
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973076061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1973076061
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.439443659
Short name T393
Test name
Test status
Simulation time 988299713 ps
CPU time 2.04 seconds
Started May 07 03:21:22 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 183660 kb
Host smart-fddf4195-586b-420d-b693-37744781b83a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439443659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.439443659
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.69601899
Short name T343
Test name
Test status
Simulation time 506646332 ps
CPU time 0.92 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 195876 kb
Host smart-ec338c7e-559f-4416-9043-5bf9f0b105be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69601899 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.69601899
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3541501780
Short name T70
Test name
Test status
Simulation time 328556167 ps
CPU time 0.73 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 193000 kb
Host smart-48bba7dc-5227-4827-a122-85e4a85cbae9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541501780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3541501780
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2996742315
Short name T365
Test name
Test status
Simulation time 484637217 ps
CPU time 0.59 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183572 kb
Host smart-64853a84-638f-4daa-a197-813536ebebf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996742315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2996742315
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2119985397
Short name T361
Test name
Test status
Simulation time 474914398 ps
CPU time 0.88 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:22 PM PDT 24
Peak memory 183512 kb
Host smart-55b92898-603a-46b9-a974-3162a21c90e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119985397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2119985397
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3686195024
Short name T355
Test name
Test status
Simulation time 349833154 ps
CPU time 1.03 seconds
Started May 07 03:21:22 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 183572 kb
Host smart-40addb96-72f7-4a39-8227-324c5a4adb6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686195024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3686195024
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2510501998
Short name T77
Test name
Test status
Simulation time 3042205831 ps
CPU time 2.06 seconds
Started May 07 03:21:18 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 183904 kb
Host smart-69947251-62fd-4fd6-9ae7-c4416700eda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510501998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2510501998
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1054058761
Short name T333
Test name
Test status
Simulation time 646198120 ps
CPU time 1.38 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 198484 kb
Host smart-34175648-b6da-4165-9484-c19387c2d481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054058761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1054058761
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1671545702
Short name T317
Test name
Test status
Simulation time 8279335957 ps
CPU time 4.2 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 197944 kb
Host smart-2515dd9e-f065-4c6c-bb6e-7aa457175a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671545702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1671545702
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2473714038
Short name T328
Test name
Test status
Simulation time 472577609 ps
CPU time 1.32 seconds
Started May 07 03:21:29 PM PDT 24
Finished May 07 03:21:32 PM PDT 24
Peak memory 195636 kb
Host smart-945d5c39-f147-45f5-bed3-88ecd8cb8fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473714038 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2473714038
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3811084865
Short name T331
Test name
Test status
Simulation time 463292320 ps
CPU time 1.21 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 183800 kb
Host smart-ecb503dd-3492-4245-9698-b6cec86f8306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811084865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3811084865
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4294046467
Short name T382
Test name
Test status
Simulation time 491558095 ps
CPU time 0.79 seconds
Started May 07 03:21:33 PM PDT 24
Finished May 07 03:21:34 PM PDT 24
Peak memory 183580 kb
Host smart-cb1b3bc0-e596-410c-b180-1b6cd82b06ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294046467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4294046467
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3823447795
Short name T395
Test name
Test status
Simulation time 999077634 ps
CPU time 3.13 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 183648 kb
Host smart-0b396445-cc88-4316-9704-8e0cd08565aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823447795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3823447795
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3526779854
Short name T297
Test name
Test status
Simulation time 537956827 ps
CPU time 2.76 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 198504 kb
Host smart-2171a2f6-7f1e-4337-a05b-db62b9c18885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526779854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3526779854
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2622403376
Short name T325
Test name
Test status
Simulation time 8588847699 ps
CPU time 4.76 seconds
Started May 07 03:21:34 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 197936 kb
Host smart-9fb4a066-4d4f-4f89-8c56-743bb058bf06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622403376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2622403376
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3383847115
Short name T363
Test name
Test status
Simulation time 468905841 ps
CPU time 0.96 seconds
Started May 07 03:21:38 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 196864 kb
Host smart-15fb0445-3096-41f6-907a-baf73bfa315e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383847115 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3383847115
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1688927016
Short name T394
Test name
Test status
Simulation time 518248743 ps
CPU time 1.37 seconds
Started May 07 03:21:39 PM PDT 24
Finished May 07 03:21:41 PM PDT 24
Peak memory 193164 kb
Host smart-9b2b67c7-20e4-486f-aac9-0639a5882365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688927016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1688927016
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4075796385
Short name T277
Test name
Test status
Simulation time 431901577 ps
CPU time 0.86 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:49 PM PDT 24
Peak memory 183536 kb
Host smart-7e59ab4e-3e9a-4721-bb77-ff16c1793016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075796385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4075796385
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.873481271
Short name T314
Test name
Test status
Simulation time 1224689101 ps
CPU time 1.5 seconds
Started May 07 03:21:43 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 183636 kb
Host smart-ac6db066-3306-4fea-94ed-9c488852d8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873481271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.873481271
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3041495263
Short name T287
Test name
Test status
Simulation time 474505897 ps
CPU time 2.78 seconds
Started May 07 03:21:31 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 198472 kb
Host smart-facc365d-3fac-4b70-9e24-e216b9da1681
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041495263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3041495263
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3940234060
Short name T396
Test name
Test status
Simulation time 8059556126 ps
CPU time 4.39 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:51 PM PDT 24
Peak memory 197916 kb
Host smart-6a340383-049c-4d33-bd75-23ca7d1d2136
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940234060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3940234060
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.399549493
Short name T415
Test name
Test status
Simulation time 413581279 ps
CPU time 0.93 seconds
Started May 07 03:21:37 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 195732 kb
Host smart-687249dd-189e-4e88-976d-f1ca82793aae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399549493 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.399549493
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1885528376
Short name T76
Test name
Test status
Simulation time 507839763 ps
CPU time 0.79 seconds
Started May 07 03:21:39 PM PDT 24
Finished May 07 03:21:41 PM PDT 24
Peak memory 183888 kb
Host smart-d19f433c-4bbc-4e77-afbf-c18edc086438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885528376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1885528376
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1205965078
Short name T407
Test name
Test status
Simulation time 476444542 ps
CPU time 0.88 seconds
Started May 07 03:21:38 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 183588 kb
Host smart-ac23dad4-07af-486e-b939-0fc7f0b0f93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205965078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1205965078
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3034188715
Short name T376
Test name
Test status
Simulation time 2281561511 ps
CPU time 3.15 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:49 PM PDT 24
Peak memory 194580 kb
Host smart-bc4c2493-e95c-459c-af75-3a3b03ff964f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034188715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3034188715
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2260964656
Short name T403
Test name
Test status
Simulation time 391402203 ps
CPU time 2.06 seconds
Started May 07 03:21:41 PM PDT 24
Finished May 07 03:21:44 PM PDT 24
Peak memory 198568 kb
Host smart-930a7eb6-4981-4481-888b-4c1938256f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260964656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2260964656
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3265675704
Short name T107
Test name
Test status
Simulation time 8233671475 ps
CPU time 15.22 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:53 PM PDT 24
Peak memory 197848 kb
Host smart-64c2069c-24d3-4597-8725-91052d39805e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265675704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3265675704
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.96537033
Short name T111
Test name
Test status
Simulation time 501333846 ps
CPU time 1.34 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 196260 kb
Host smart-4d79d349-ca11-4b4e-9051-39cc0a00253f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96537033 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.96537033
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4111997464
Short name T79
Test name
Test status
Simulation time 362350292 ps
CPU time 0.88 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 193104 kb
Host smart-33ae3151-bceb-42de-a755-6aadbdd1bca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111997464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4111997464
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3849224990
Short name T371
Test name
Test status
Simulation time 397816592 ps
CPU time 0.71 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:37 PM PDT 24
Peak memory 183552 kb
Host smart-dbd8624a-c942-4a93-91b5-5f2a7082a704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849224990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3849224990
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1135433291
Short name T320
Test name
Test status
Simulation time 1330755900 ps
CPU time 1.98 seconds
Started May 07 03:21:41 PM PDT 24
Finished May 07 03:21:44 PM PDT 24
Peak memory 183740 kb
Host smart-0d9a8ad9-630f-4745-85ea-64bd7318e622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135433291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1135433291
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1867460640
Short name T315
Test name
Test status
Simulation time 324683433 ps
CPU time 2.8 seconds
Started May 07 03:21:39 PM PDT 24
Finished May 07 03:21:43 PM PDT 24
Peak memory 198524 kb
Host smart-0638ed75-fe3f-413e-9b59-fa5797c84fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867460640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1867460640
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3287122556
Short name T369
Test name
Test status
Simulation time 4231595407 ps
CPU time 1.44 seconds
Started May 07 03:21:37 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 196344 kb
Host smart-80ef9eb8-b41b-42a9-ae7a-cbe882374512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287122556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3287122556
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3193337062
Short name T373
Test name
Test status
Simulation time 547608708 ps
CPU time 1.14 seconds
Started May 07 03:21:40 PM PDT 24
Finished May 07 03:21:42 PM PDT 24
Peak memory 196508 kb
Host smart-14157307-6354-4d98-8e0a-60ca0cd76e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193337062 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3193337062
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2899248917
Short name T63
Test name
Test status
Simulation time 357937842 ps
CPU time 1.16 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:39 PM PDT 24
Peak memory 193028 kb
Host smart-18bbbee7-64d8-4848-8496-866139a808a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899248917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2899248917
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.247811776
Short name T389
Test name
Test status
Simulation time 493552757 ps
CPU time 0.72 seconds
Started May 07 03:21:37 PM PDT 24
Finished May 07 03:21:39 PM PDT 24
Peak memory 183512 kb
Host smart-4dda68e6-a186-461a-b69f-45d138f34276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247811776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.247811776
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2577538841
Short name T318
Test name
Test status
Simulation time 1395382298 ps
CPU time 0.76 seconds
Started May 07 03:21:38 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 193164 kb
Host smart-22b67928-84ab-4348-8508-57d4f86b729d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577538841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2577538841
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1095084943
Short name T295
Test name
Test status
Simulation time 381282919 ps
CPU time 1.83 seconds
Started May 07 03:21:43 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 198472 kb
Host smart-f640aa59-3921-430c-b530-b30cbdfe5a17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095084943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1095084943
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1490435599
Short name T384
Test name
Test status
Simulation time 8723650131 ps
CPU time 3.26 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 197808 kb
Host smart-4442a205-55c0-4359-92c6-b769f81cc74e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490435599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1490435599
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3398330057
Short name T294
Test name
Test status
Simulation time 585213651 ps
CPU time 0.9 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 197212 kb
Host smart-16773252-c1bc-4dca-9540-d95a3c9764c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398330057 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3398330057
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1129617076
Short name T78
Test name
Test status
Simulation time 349374257 ps
CPU time 0.83 seconds
Started May 07 03:21:38 PM PDT 24
Finished May 07 03:21:40 PM PDT 24
Peak memory 183836 kb
Host smart-08ac28a2-a4ab-4e40-839c-8a9533230358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129617076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1129617076
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.93420101
Short name T362
Test name
Test status
Simulation time 482281185 ps
CPU time 0.9 seconds
Started May 07 03:21:37 PM PDT 24
Finished May 07 03:21:39 PM PDT 24
Peak memory 183536 kb
Host smart-b357abf0-fc8b-477c-a1c5-649f8eac8830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93420101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.93420101
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2690149612
Short name T338
Test name
Test status
Simulation time 1458236139 ps
CPU time 2.64 seconds
Started May 07 03:21:42 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 194380 kb
Host smart-15fc381f-93f5-4e12-9834-e9d6c6b8b81c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690149612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2690149612
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.674640521
Short name T410
Test name
Test status
Simulation time 648555659 ps
CPU time 2.26 seconds
Started May 07 03:21:38 PM PDT 24
Finished May 07 03:21:42 PM PDT 24
Peak memory 198500 kb
Host smart-9ffc7f17-8333-4dfa-8cc3-3de9dc3144de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674640521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.674640521
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3116261464
Short name T40
Test name
Test status
Simulation time 4254706196 ps
CPU time 7.37 seconds
Started May 07 03:21:37 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 197332 kb
Host smart-8af3c56a-756d-4b51-9cb7-ea1fcf5d4a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116261464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3116261464
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3853484497
Short name T352
Test name
Test status
Simulation time 449312397 ps
CPU time 1.34 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 197100 kb
Host smart-5105dc33-696b-48a6-b608-c758cc2bd882
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853484497 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3853484497
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3698291083
Short name T74
Test name
Test status
Simulation time 511672991 ps
CPU time 0.7 seconds
Started May 07 03:21:42 PM PDT 24
Finished May 07 03:21:44 PM PDT 24
Peak memory 193064 kb
Host smart-da45e13b-22bb-4eb9-94bc-c647173af530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698291083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3698291083
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.740292171
Short name T354
Test name
Test status
Simulation time 358692369 ps
CPU time 0.67 seconds
Started May 07 03:21:42 PM PDT 24
Finished May 07 03:21:44 PM PDT 24
Peak memory 183276 kb
Host smart-8715a7f8-251f-40a4-bcfd-ca05d1a3dc1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740292171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.740292171
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1212723164
Short name T296
Test name
Test status
Simulation time 2531625186 ps
CPU time 1.53 seconds
Started May 07 03:21:43 PM PDT 24
Finished May 07 03:21:45 PM PDT 24
Peak memory 194304 kb
Host smart-6ab7211c-28fb-4f82-8e40-eaa1d1573ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212723164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1212723164
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2468627040
Short name T302
Test name
Test status
Simulation time 449329765 ps
CPU time 1.47 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 198480 kb
Host smart-57ae3b09-45b1-43ae-9cd2-12922c6d6190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468627040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2468627040
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3840308703
Short name T337
Test name
Test status
Simulation time 8640049165 ps
CPU time 4.29 seconds
Started May 07 03:21:42 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 198048 kb
Host smart-d3798674-2c7e-43ad-8f25-bb61a2965bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840308703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3840308703
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1966484231
Short name T388
Test name
Test status
Simulation time 570948239 ps
CPU time 1.49 seconds
Started May 07 03:21:50 PM PDT 24
Finished May 07 03:21:52 PM PDT 24
Peak memory 194916 kb
Host smart-75927fcf-0ce5-45cf-905a-bca388f83e01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966484231 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1966484231
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.478899752
Short name T66
Test name
Test status
Simulation time 524641721 ps
CPU time 0.74 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:45 PM PDT 24
Peak memory 183664 kb
Host smart-690b4f6e-1560-460d-aabb-f5cb5425dd90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478899752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.478899752
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3059991118
Short name T332
Test name
Test status
Simulation time 446672795 ps
CPU time 0.6 seconds
Started May 07 03:21:41 PM PDT 24
Finished May 07 03:21:43 PM PDT 24
Peak memory 183588 kb
Host smart-80e823f8-9219-494d-acdc-383c3976efda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059991118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3059991118
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3699663929
Short name T326
Test name
Test status
Simulation time 1521429720 ps
CPU time 1.32 seconds
Started May 07 03:21:47 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 193480 kb
Host smart-7a32fa4e-9d0c-4ffc-a60b-126466508b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699663929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3699663929
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2253130166
Short name T339
Test name
Test status
Simulation time 568040276 ps
CPU time 1.39 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 198512 kb
Host smart-1f00099d-8f11-4a07-99bc-b727f2cca48a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253130166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2253130166
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1152446079
Short name T408
Test name
Test status
Simulation time 4382387794 ps
CPU time 2.54 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 197300 kb
Host smart-11773c4d-2ef4-42b7-945a-406c53a8ad12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152446079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1152446079
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1274822380
Short name T386
Test name
Test status
Simulation time 561366533 ps
CPU time 0.92 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 195832 kb
Host smart-064ac68a-6cf9-4775-8f77-2b87b3bec5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274822380 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1274822380
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2610776922
Short name T414
Test name
Test status
Simulation time 355413787 ps
CPU time 1.08 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:54 PM PDT 24
Peak memory 183720 kb
Host smart-6e64fdc3-c371-4953-a669-c36dc0f3c6ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610776922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2610776922
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3486419461
Short name T411
Test name
Test status
Simulation time 498365540 ps
CPU time 1.21 seconds
Started May 07 03:21:48 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 183548 kb
Host smart-fc4a9cb7-8e7e-42a9-b291-75641be2b539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486419461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3486419461
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.488036185
Short name T35
Test name
Test status
Simulation time 2716676443 ps
CPU time 5.71 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:51 PM PDT 24
Peak memory 194720 kb
Host smart-51601113-2550-49f4-be33-f67bd5eaa1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488036185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.488036185
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3588875850
Short name T366
Test name
Test status
Simulation time 759517746 ps
CPU time 1.79 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 198500 kb
Host smart-c389b377-95e5-416f-b4e1-d4507d248996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588875850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3588875850
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4127576329
Short name T108
Test name
Test status
Simulation time 8680442977 ps
CPU time 4.78 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:22:01 PM PDT 24
Peak memory 197620 kb
Host smart-933312d8-c734-43b4-8597-fabe2ed18300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127576329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4127576329
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2962466668
Short name T348
Test name
Test status
Simulation time 641959555 ps
CPU time 0.96 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:55 PM PDT 24
Peak memory 197156 kb
Host smart-02e7a922-dc72-4778-a88e-dcea83afe6d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962466668 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2962466668
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3600977075
Short name T72
Test name
Test status
Simulation time 358843382 ps
CPU time 1.21 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 192960 kb
Host smart-01b6f5a2-a7d7-468b-bf25-02b685a18166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600977075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3600977075
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2680070910
Short name T323
Test name
Test status
Simulation time 388295298 ps
CPU time 0.85 seconds
Started May 07 03:21:41 PM PDT 24
Finished May 07 03:21:43 PM PDT 24
Peak memory 183588 kb
Host smart-279adf1a-fd9d-4a37-b58d-a65a62047b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680070910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2680070910
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.2634275102
Short name T359
Test name
Test status
Simulation time 2568159204 ps
CPU time 1.58 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 194336 kb
Host smart-96b2fea7-eece-4372-80ad-7195aab7d72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634275102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.2634275102
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1674901473
Short name T307
Test name
Test status
Simulation time 823472009 ps
CPU time 1.37 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 198452 kb
Host smart-b1888e1d-bced-431e-bc68-b1ca52d82348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674901473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1674901473
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2788793516
Short name T327
Test name
Test status
Simulation time 726815846 ps
CPU time 2.02 seconds
Started May 07 03:21:18 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 183704 kb
Host smart-45625ab4-68e8-4529-9339-54ab5278f416
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788793516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2788793516
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3586211411
Short name T37
Test name
Test status
Simulation time 10806298247 ps
CPU time 15.03 seconds
Started May 07 03:21:22 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 195776 kb
Host smart-eabeb837-1228-46a4-8328-79706930ae36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586211411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3586211411
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3520780936
Short name T38
Test name
Test status
Simulation time 685953037 ps
CPU time 1.13 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183664 kb
Host smart-12fd2a64-9434-4e40-852a-f941d8c496c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520780936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3520780936
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1166647421
Short name T345
Test name
Test status
Simulation time 379787685 ps
CPU time 0.9 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 195720 kb
Host smart-36222aee-6ad5-469c-b53a-84fa49d43047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166647421 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1166647421
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2688799499
Short name T378
Test name
Test status
Simulation time 474723483 ps
CPU time 0.74 seconds
Started May 07 03:21:23 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 192920 kb
Host smart-1d9e469c-576a-4b70-8b02-e545db4e494a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688799499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2688799499
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1633609906
Short name T310
Test name
Test status
Simulation time 302844899 ps
CPU time 0.66 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:32 PM PDT 24
Peak memory 183584 kb
Host smart-4b5050ba-4f53-4532-b65c-20261e46c90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633609906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1633609906
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1408287312
Short name T391
Test name
Test status
Simulation time 278534098 ps
CPU time 0.75 seconds
Started May 07 03:21:19 PM PDT 24
Finished May 07 03:21:21 PM PDT 24
Peak memory 183488 kb
Host smart-d7b335c4-cdf8-4858-b891-3b1e17a23013
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408287312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1408287312
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2357538168
Short name T281
Test name
Test status
Simulation time 328384675 ps
CPU time 0.77 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:27 PM PDT 24
Peak memory 183592 kb
Host smart-8a2e7c4b-502a-4bab-8d38-8c1f3ce28d21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357538168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2357538168
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.106638517
Short name T304
Test name
Test status
Simulation time 1230187817 ps
CPU time 3.2 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 183732 kb
Host smart-c176b75c-fda6-4ed7-836b-013a791c2084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106638517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.106638517
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2058050825
Short name T282
Test name
Test status
Simulation time 319235931 ps
CPU time 1.37 seconds
Started May 07 03:21:22 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 198468 kb
Host smart-d09dbefb-dc6f-4273-ace0-1b8309a203dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058050825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2058050825
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3808609591
Short name T109
Test name
Test status
Simulation time 8514580841 ps
CPU time 3.27 seconds
Started May 07 03:21:18 PM PDT 24
Finished May 07 03:21:22 PM PDT 24
Peak memory 197728 kb
Host smart-82aa1e0d-2c25-4d7f-9c65-2a8f5e791e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808609591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3808609591
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3374816853
Short name T387
Test name
Test status
Simulation time 380382018 ps
CPU time 0.78 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183552 kb
Host smart-3bcbf28c-3713-4cff-9043-c9f270971409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374816853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3374816853
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3092501770
Short name T292
Test name
Test status
Simulation time 413414209 ps
CPU time 1.14 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:51 PM PDT 24
Peak memory 183572 kb
Host smart-fd5ea566-40a9-4cab-98e6-9ccd800d1b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092501770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3092501770
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.250118974
Short name T417
Test name
Test status
Simulation time 318710969 ps
CPU time 0.62 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:56 PM PDT 24
Peak memory 183628 kb
Host smart-82477d98-009b-46e4-ada6-19b368ba0ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250118974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.250118974
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.753004599
Short name T356
Test name
Test status
Simulation time 427687993 ps
CPU time 0.57 seconds
Started May 07 03:21:42 PM PDT 24
Finished May 07 03:21:43 PM PDT 24
Peak memory 183564 kb
Host smart-23556154-1589-4cdf-9f52-38fe28abec02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753004599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.753004599
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2482702941
Short name T306
Test name
Test status
Simulation time 536464337 ps
CPU time 0.7 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183596 kb
Host smart-44764019-ffe5-4d00-9d1e-53480c1cef29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482702941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2482702941
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.694508076
Short name T275
Test name
Test status
Simulation time 366183511 ps
CPU time 1.08 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:46 PM PDT 24
Peak memory 183556 kb
Host smart-8c15b029-ea0e-4010-bd7a-8c8f0606a05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694508076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.694508076
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.13090362
Short name T404
Test name
Test status
Simulation time 379600280 ps
CPU time 0.69 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183576 kb
Host smart-10218869-9294-4070-99e6-47c740ac8ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13090362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.13090362
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1024885751
Short name T284
Test name
Test status
Simulation time 462684182 ps
CPU time 0.71 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183580 kb
Host smart-2bee0982-26c0-455d-a5e7-385e06d9daf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024885751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1024885751
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3426622802
Short name T413
Test name
Test status
Simulation time 299450357 ps
CPU time 0.97 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 183588 kb
Host smart-a6678aa7-b486-4958-93ba-9ab70eea5ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426622802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3426622802
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.940733917
Short name T313
Test name
Test status
Simulation time 380793646 ps
CPU time 1.06 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183580 kb
Host smart-df322e99-85f2-4e7d-9388-8095f939e78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940733917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.940733917
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1046387734
Short name T324
Test name
Test status
Simulation time 357287797 ps
CPU time 1.24 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183660 kb
Host smart-f5eed5f9-147a-4236-b44c-8950d21579ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046387734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1046387734
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1974211463
Short name T75
Test name
Test status
Simulation time 2557680441 ps
CPU time 6.89 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 192196 kb
Host smart-c47e4570-53e5-4568-8127-833f803065cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974211463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1974211463
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3187722009
Short name T358
Test name
Test status
Simulation time 799090825 ps
CPU time 1.68 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 183672 kb
Host smart-36e153c6-65ac-4e8e-86a8-dda1ba982317
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187722009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3187722009
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4083153996
Short name T110
Test name
Test status
Simulation time 401920590 ps
CPU time 0.94 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 195640 kb
Host smart-50eb6247-a93c-46ce-b335-9ce58934ba73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083153996 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4083153996
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.207551153
Short name T299
Test name
Test status
Simulation time 549806703 ps
CPU time 0.77 seconds
Started May 07 03:21:21 PM PDT 24
Finished May 07 03:21:24 PM PDT 24
Peak memory 183908 kb
Host smart-a263d1d0-b008-42cb-af90-7af4fa79f930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207551153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.207551153
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.112760496
Short name T347
Test name
Test status
Simulation time 345389563 ps
CPU time 0.99 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183596 kb
Host smart-21df31d1-fbb3-4dfd-9d00-4a796a982f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112760496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.112760496
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1199719571
Short name T311
Test name
Test status
Simulation time 331829042 ps
CPU time 0.61 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183528 kb
Host smart-9bd45956-6f50-4655-b7ec-02f64835992b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199719571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1199719571
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1212742055
Short name T350
Test name
Test status
Simulation time 340571840 ps
CPU time 0.94 seconds
Started May 07 03:21:20 PM PDT 24
Finished May 07 03:21:23 PM PDT 24
Peak memory 183596 kb
Host smart-413741de-f312-421c-a9be-9a3bee8bb02a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212742055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1212742055
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3336922179
Short name T36
Test name
Test status
Simulation time 1266305834 ps
CPU time 3.86 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 193288 kb
Host smart-bdec7fb9-adc0-41d2-bb80-6a3682e07fdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336922179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3336922179
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3686649350
Short name T319
Test name
Test status
Simulation time 435720232 ps
CPU time 1.37 seconds
Started May 07 03:21:22 PM PDT 24
Finished May 07 03:21:25 PM PDT 24
Peak memory 198424 kb
Host smart-b11f0f81-c6f6-4238-a814-1e1f55d0b374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686649350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3686649350
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2993083760
Short name T398
Test name
Test status
Simulation time 4533418755 ps
CPU time 6.88 seconds
Started May 07 03:21:18 PM PDT 24
Finished May 07 03:21:26 PM PDT 24
Peak memory 197412 kb
Host smart-89fa51b6-bd29-40de-a693-14f6fd1171b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993083760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2993083760
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2957181697
Short name T370
Test name
Test status
Simulation time 481283602 ps
CPU time 0.6 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:47 PM PDT 24
Peak memory 183572 kb
Host smart-4f45742d-1d23-4da1-ae0b-604bafaa8fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957181697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2957181697
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3977582034
Short name T379
Test name
Test status
Simulation time 374578695 ps
CPU time 1.06 seconds
Started May 07 03:21:48 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 183548 kb
Host smart-f223d507-6b29-4215-8ac4-66ef6601129d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977582034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3977582034
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4050118780
Short name T375
Test name
Test status
Simulation time 518002727 ps
CPU time 1.15 seconds
Started May 07 03:21:45 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 183596 kb
Host smart-4f1d02cc-2dec-451b-bf3f-0443c42bd3e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050118780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4050118780
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.743470050
Short name T283
Test name
Test status
Simulation time 341156035 ps
CPU time 1.02 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:52 PM PDT 24
Peak memory 183592 kb
Host smart-1b2e8aa5-5682-4717-8a2b-6b9ae7ef6cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743470050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.743470050
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1426071310
Short name T334
Test name
Test status
Simulation time 339566777 ps
CPU time 1.2 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:49 PM PDT 24
Peak memory 183604 kb
Host smart-86e95f32-268a-41ce-b9f9-9a9295a45e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426071310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1426071310
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1862277915
Short name T298
Test name
Test status
Simulation time 303091058 ps
CPU time 0.97 seconds
Started May 07 03:21:44 PM PDT 24
Finished May 07 03:21:45 PM PDT 24
Peak memory 183584 kb
Host smart-665a9ff9-29d1-4e0c-9c71-b9f100658e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862277915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1862277915
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.105086684
Short name T290
Test name
Test status
Simulation time 452721365 ps
CPU time 1.14 seconds
Started May 07 03:21:43 PM PDT 24
Finished May 07 03:21:45 PM PDT 24
Peak memory 183576 kb
Host smart-cdabfda2-ad4a-4bad-ad36-9dd0046acb9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105086684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.105086684
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4046762757
Short name T353
Test name
Test status
Simulation time 337434287 ps
CPU time 0.98 seconds
Started May 07 03:21:43 PM PDT 24
Finished May 07 03:21:45 PM PDT 24
Peak memory 183584 kb
Host smart-bb810c00-d65f-4825-bd89-9bdca934759b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046762757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4046762757
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2532832676
Short name T360
Test name
Test status
Simulation time 390600566 ps
CPU time 0.63 seconds
Started May 07 03:21:52 PM PDT 24
Finished May 07 03:21:54 PM PDT 24
Peak memory 183536 kb
Host smart-be281e90-c7b3-4e2b-80a6-a15144b3bcf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532832676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2532832676
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.91285823
Short name T280
Test name
Test status
Simulation time 525599204 ps
CPU time 0.64 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 183584 kb
Host smart-88b7a1d4-ebc7-496a-a5da-69c7b11a2c64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91285823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.91285823
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2398175454
Short name T64
Test name
Test status
Simulation time 543220342 ps
CPU time 1.07 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:32 PM PDT 24
Peak memory 193864 kb
Host smart-333f1259-86d3-4939-a86d-faa56ad64dfe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398175454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2398175454
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2496095244
Short name T73
Test name
Test status
Simulation time 4661281560 ps
CPU time 11.58 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 192176 kb
Host smart-df8b4b59-7633-4d30-a78b-82545bcd8757
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496095244 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2496095244
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.946615653
Short name T279
Test name
Test status
Simulation time 737926155 ps
CPU time 0.74 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 183736 kb
Host smart-439bf186-8c98-43b1-90db-ba75f3d915fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946615653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.946615653
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1156844496
Short name T405
Test name
Test status
Simulation time 572938486 ps
CPU time 0.87 seconds
Started May 07 03:21:28 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 198080 kb
Host smart-d5c6ea73-21f2-4143-8188-815503080799
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156844496 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1156844496
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1704692142
Short name T402
Test name
Test status
Simulation time 342171388 ps
CPU time 0.85 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 183664 kb
Host smart-1f29daad-da3a-43e4-b3f0-087480282728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704692142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1704692142
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2951864806
Short name T367
Test name
Test status
Simulation time 353564883 ps
CPU time 0.95 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:26 PM PDT 24
Peak memory 183572 kb
Host smart-dc50bc72-f086-49ba-8676-b0346ffaab73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951864806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2951864806
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2705599740
Short name T335
Test name
Test status
Simulation time 472675103 ps
CPU time 1.19 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 183584 kb
Host smart-5e1de1e2-f8e2-4d6a-8a25-e966bae97ecb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705599740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2705599740
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4093219799
Short name T305
Test name
Test status
Simulation time 486379257 ps
CPU time 1.11 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:27 PM PDT 24
Peak memory 183568 kb
Host smart-2ba9745b-18e9-455b-adb6-48ada93c8d2c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093219799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4093219799
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.447882838
Short name T397
Test name
Test status
Simulation time 2308404619 ps
CPU time 3.89 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:32 PM PDT 24
Peak memory 183832 kb
Host smart-76ed27ff-5f18-4e70-ae57-82964c6a7787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447882838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.447882838
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2869243534
Short name T293
Test name
Test status
Simulation time 326400301 ps
CPU time 1.58 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 198300 kb
Host smart-0bdb817d-e695-4d3c-bdc2-f26f4d576535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869243534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2869243534
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4200320709
Short name T385
Test name
Test status
Simulation time 8018010617 ps
CPU time 12.46 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:41 PM PDT 24
Peak memory 197748 kb
Host smart-e257aba3-0bd2-4560-8bf2-c1220c38dc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200320709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.4200320709
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.905211415
Short name T374
Test name
Test status
Simulation time 335668383 ps
CPU time 0.97 seconds
Started May 07 03:21:48 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 183552 kb
Host smart-65033f57-f23a-4339-bdf6-c03ed3aca8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905211415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.905211415
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1068050624
Short name T383
Test name
Test status
Simulation time 439442011 ps
CPU time 0.67 seconds
Started May 07 03:21:46 PM PDT 24
Finished May 07 03:21:48 PM PDT 24
Peak memory 183584 kb
Host smart-f82b2636-009f-4caa-8920-ddec5c58efba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068050624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1068050624
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1325885206
Short name T291
Test name
Test status
Simulation time 270847145 ps
CPU time 0.86 seconds
Started May 07 03:21:57 PM PDT 24
Finished May 07 03:22:00 PM PDT 24
Peak memory 183584 kb
Host smart-a53698be-52d2-45ad-906e-0424dc0900fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325885206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1325885206
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2191600172
Short name T303
Test name
Test status
Simulation time 319306884 ps
CPU time 1.02 seconds
Started May 07 03:21:55 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 183584 kb
Host smart-43f1abd8-b024-4004-8774-a1d5cb24828c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191600172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2191600172
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.93012967
Short name T301
Test name
Test status
Simulation time 408739133 ps
CPU time 1.17 seconds
Started May 07 03:21:48 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 183592 kb
Host smart-16f4086e-c357-4df9-97da-40e921e3427d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93012967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.93012967
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3787282635
Short name T381
Test name
Test status
Simulation time 435918847 ps
CPU time 1.08 seconds
Started May 07 03:21:54 PM PDT 24
Finished May 07 03:21:58 PM PDT 24
Peak memory 183556 kb
Host smart-c56937e6-e18d-428b-ba05-5b8481221b53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787282635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3787282635
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3643474460
Short name T276
Test name
Test status
Simulation time 324672466 ps
CPU time 1.01 seconds
Started May 07 03:21:47 PM PDT 24
Finished May 07 03:21:50 PM PDT 24
Peak memory 183580 kb
Host smart-915fff87-5797-4d11-8d64-ce8fcf26e410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643474460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3643474460
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3450700025
Short name T351
Test name
Test status
Simulation time 274302803 ps
CPU time 0.92 seconds
Started May 07 03:21:56 PM PDT 24
Finished May 07 03:21:59 PM PDT 24
Peak memory 183584 kb
Host smart-6a59b81e-ed6a-4067-b21c-292f089250f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450700025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3450700025
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1994335093
Short name T342
Test name
Test status
Simulation time 468025098 ps
CPU time 1.21 seconds
Started May 07 03:21:49 PM PDT 24
Finished May 07 03:21:52 PM PDT 24
Peak memory 183556 kb
Host smart-9853dccc-6840-4f43-ab21-04ec22a9168c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994335093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1994335093
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.41573312
Short name T278
Test name
Test status
Simulation time 500402473 ps
CPU time 0.77 seconds
Started May 07 03:21:53 PM PDT 24
Finished May 07 03:21:57 PM PDT 24
Peak memory 183624 kb
Host smart-c38ecb8b-0b77-4c21-a192-80adb63c4ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41573312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.41573312
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1764541036
Short name T377
Test name
Test status
Simulation time 500358226 ps
CPU time 0.79 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 195988 kb
Host smart-eafbb229-ee8e-485a-951c-87a6e622f217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764541036 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1764541036
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2952490282
Short name T68
Test name
Test status
Simulation time 522789460 ps
CPU time 0.74 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:26 PM PDT 24
Peak memory 183644 kb
Host smart-1fcb9a30-6150-46e7-ba1d-8c8c0d707e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952490282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2952490282
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.195832241
Short name T344
Test name
Test status
Simulation time 369346870 ps
CPU time 0.82 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 183588 kb
Host smart-f464e694-24dc-453e-890e-550a4ecae3ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195832241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.195832241
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1212628053
Short name T416
Test name
Test status
Simulation time 1189020023 ps
CPU time 1.77 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:27 PM PDT 24
Peak memory 193236 kb
Host smart-3062e589-d07b-4ec5-a7ac-33a6ef782b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212628053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1212628053
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2766339497
Short name T340
Test name
Test status
Simulation time 776911324 ps
CPU time 2.8 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 198540 kb
Host smart-70c55d0d-206b-4554-865a-481da66aa693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766339497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2766339497
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2438756929
Short name T329
Test name
Test status
Simulation time 7676064822 ps
CPU time 11.14 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 197980 kb
Host smart-e859dec5-e9ee-46ec-bded-585099ab6e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438756929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2438756929
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3264160882
Short name T330
Test name
Test status
Simulation time 589594357 ps
CPU time 1.13 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:27 PM PDT 24
Peak memory 196320 kb
Host smart-767d6751-a3f7-4df8-a032-5795f7d1d3f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264160882 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3264160882
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.28196583
Short name T412
Test name
Test status
Simulation time 420751851 ps
CPU time 1.28 seconds
Started May 07 03:21:28 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 192852 kb
Host smart-010ed258-1f35-48cb-9c36-4ed7816e9452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28196583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.28196583
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3951843402
Short name T406
Test name
Test status
Simulation time 310396269 ps
CPU time 0.63 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 183572 kb
Host smart-83af4174-6d88-4d62-a956-0ed4c9ce970b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951843402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3951843402
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3371018487
Short name T34
Test name
Test status
Simulation time 3214851054 ps
CPU time 5.84 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 194540 kb
Host smart-b0d7eae2-f96b-42e4-8c72-76a3087728a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371018487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3371018487
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1101974803
Short name T392
Test name
Test status
Simulation time 385433111 ps
CPU time 1.78 seconds
Started May 07 03:21:26 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 198456 kb
Host smart-85de10b8-7469-42c0-82e1-3524d7b90707
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101974803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1101974803
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.4173003687
Short name T321
Test name
Test status
Simulation time 4485281933 ps
CPU time 2 seconds
Started May 07 03:21:28 PM PDT 24
Finished May 07 03:21:31 PM PDT 24
Peak memory 197612 kb
Host smart-71b1fbfd-3c84-4795-8a68-e6068c43ba4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173003687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.4173003687
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1913356459
Short name T289
Test name
Test status
Simulation time 442577873 ps
CPU time 1.2 seconds
Started May 07 03:21:33 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 195420 kb
Host smart-0a6c45e3-782b-446d-95b8-e4b216f39d8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913356459 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1913356459
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2539167868
Short name T368
Test name
Test status
Simulation time 589663909 ps
CPU time 0.63 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:29 PM PDT 24
Peak memory 183344 kb
Host smart-a5064113-6c5a-4913-9b17-d2aa6f0a0468
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539167868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2539167868
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.349818552
Short name T380
Test name
Test status
Simulation time 453512239 ps
CPU time 1.18 seconds
Started May 07 03:21:25 PM PDT 24
Finished May 07 03:21:28 PM PDT 24
Peak memory 183568 kb
Host smart-4871194a-9135-4932-a5b9-f3c47bfe9491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349818552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.349818552
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.448876682
Short name T322
Test name
Test status
Simulation time 2375887349 ps
CPU time 1.59 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 194620 kb
Host smart-9587ccf3-0f5b-4061-a343-dc05ee66811c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448876682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.448876682
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.768556532
Short name T312
Test name
Test status
Simulation time 686561654 ps
CPU time 3.3 seconds
Started May 07 03:21:27 PM PDT 24
Finished May 07 03:21:32 PM PDT 24
Peak memory 198472 kb
Host smart-335d1b25-f639-4b68-83d1-bbd8fea9c251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768556532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.768556532
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2790271983
Short name T285
Test name
Test status
Simulation time 4445115992 ps
CPU time 4.4 seconds
Started May 07 03:21:24 PM PDT 24
Finished May 07 03:21:30 PM PDT 24
Peak memory 197664 kb
Host smart-494422f6-c54e-4250-a755-2f4f69032158
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790271983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2790271983
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.164488545
Short name T308
Test name
Test status
Simulation time 419133001 ps
CPU time 0.8 seconds
Started May 07 03:21:31 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 195708 kb
Host smart-c4d881ba-709c-4052-a4e0-36d6e9037236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164488545 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.164488545
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1132377047
Short name T346
Test name
Test status
Simulation time 325447319 ps
CPU time 0.99 seconds
Started May 07 03:21:33 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 183628 kb
Host smart-f9cf99b3-3324-4352-bca7-698afda57f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132377047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1132377047
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.212192297
Short name T349
Test name
Test status
Simulation time 1281785548 ps
CPU time 3.05 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 183820 kb
Host smart-76d64601-b427-4177-ac13-67ac40f718ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212192297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.212192297
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.419580899
Short name T401
Test name
Test status
Simulation time 545341343 ps
CPU time 2.51 seconds
Started May 07 03:21:35 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 197972 kb
Host smart-182e263b-b591-4b96-935b-84c8befcd79d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419580899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.419580899
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1397125125
Short name T341
Test name
Test status
Simulation time 4232002375 ps
CPU time 7.79 seconds
Started May 07 03:21:33 PM PDT 24
Finished May 07 03:21:41 PM PDT 24
Peak memory 197448 kb
Host smart-5315f93e-bf1f-409f-b794-a9c93fd417f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397125125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1397125125
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2620357979
Short name T357
Test name
Test status
Simulation time 471937617 ps
CPU time 1.39 seconds
Started May 07 03:21:36 PM PDT 24
Finished May 07 03:21:38 PM PDT 24
Peak memory 196164 kb
Host smart-21c52059-3bb5-4b8c-8257-06ab33a2a199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620357979 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2620357979
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3716441488
Short name T67
Test name
Test status
Simulation time 402030629 ps
CPU time 1.15 seconds
Started May 07 03:21:30 PM PDT 24
Finished May 07 03:21:33 PM PDT 24
Peak memory 183664 kb
Host smart-5aa94ee1-6abb-4034-a6b3-fd872b37a66f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716441488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3716441488
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2077565354
Short name T286
Test name
Test status
Simulation time 395014947 ps
CPU time 0.68 seconds
Started May 07 03:21:29 PM PDT 24
Finished May 07 03:21:31 PM PDT 24
Peak memory 183556 kb
Host smart-9fc7d346-65eb-4e84-88db-81443e95a61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077565354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2077565354
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.87640750
Short name T81
Test name
Test status
Simulation time 2832785426 ps
CPU time 1.92 seconds
Started May 07 03:21:32 PM PDT 24
Finished May 07 03:21:35 PM PDT 24
Peak memory 194028 kb
Host smart-09d46313-973a-4756-bf4d-2685565bcac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87640750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_t
imer_same_csr_outstanding.87640750
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1109778130
Short name T400
Test name
Test status
Simulation time 512660837 ps
CPU time 2.22 seconds
Started May 07 03:21:31 PM PDT 24
Finished May 07 03:21:34 PM PDT 24
Peak memory 198484 kb
Host smart-b8bdacc6-fc12-4fa8-ba99-26267590e11a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109778130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1109778130
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.93136236
Short name T41
Test name
Test status
Simulation time 4983691530 ps
CPU time 1.39 seconds
Started May 07 03:21:35 PM PDT 24
Finished May 07 03:21:37 PM PDT 24
Peak memory 196012 kb
Host smart-2dd9b2ed-2d53-4699-aa07-0ef5d113294f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93136236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_i
ntg_err.93136236
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2159924764
Short name T206
Test name
Test status
Simulation time 424656803 ps
CPU time 1.2 seconds
Started May 07 03:02:13 PM PDT 24
Finished May 07 03:02:15 PM PDT 24
Peak memory 183540 kb
Host smart-77121a59-3993-4650-82da-bba630bb1761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159924764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2159924764
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1802789320
Short name T57
Test name
Test status
Simulation time 47120687113 ps
CPU time 18.47 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:35 PM PDT 24
Peak memory 183580 kb
Host smart-a52ed179-e8c0-474c-8ab9-5e4726635398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802789320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1802789320
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3364432978
Short name T175
Test name
Test status
Simulation time 537731152 ps
CPU time 0.81 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:16 PM PDT 24
Peak memory 183580 kb
Host smart-a034a7ab-5a18-481a-8867-9d8b381968f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364432978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3364432978
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4207283874
Short name T242
Test name
Test status
Simulation time 10095126728 ps
CPU time 15.85 seconds
Started May 07 03:02:16 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 194276 kb
Host smart-7531806c-c31e-49be-8d37-f6891f49e285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207283874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4207283874
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.768297594
Short name T271
Test name
Test status
Simulation time 374492670 ps
CPU time 1.11 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:25 PM PDT 24
Peak memory 183504 kb
Host smart-eb1f3b7f-da3f-43e6-9c1e-d3440be16853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768297594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.768297594
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3183917285
Short name T14
Test name
Test status
Simulation time 8417305848 ps
CPU time 2.02 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:26 PM PDT 24
Peak memory 215228 kb
Host smart-467eddab-fe30-463e-97d4-e24e593a69fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183917285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3183917285
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3362144346
Short name T190
Test name
Test status
Simulation time 600851638 ps
CPU time 0.82 seconds
Started May 07 03:02:14 PM PDT 24
Finished May 07 03:02:17 PM PDT 24
Peak memory 183548 kb
Host smart-135fd73f-3993-4575-8f12-034287412b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362144346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3362144346
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2019463127
Short name T184
Test name
Test status
Simulation time 256975862315 ps
CPU time 95.18 seconds
Started May 07 03:02:24 PM PDT 24
Finished May 07 03:04:00 PM PDT 24
Peak memory 195276 kb
Host smart-3d561f90-8378-4de1-90b0-e6966b271b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019463127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2019463127
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.381856234
Short name T235
Test name
Test status
Simulation time 582029638 ps
CPU time 1.43 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183548 kb
Host smart-5d1b112e-b471-461a-8250-6c2089fd3804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381856234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.381856234
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1062485603
Short name T166
Test name
Test status
Simulation time 47303224939 ps
CPU time 18.05 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:46 PM PDT 24
Peak memory 183624 kb
Host smart-72fd9b98-8ace-4912-8b03-e2f6a342598a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062485603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1062485603
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3898464131
Short name T83
Test name
Test status
Simulation time 376819836 ps
CPU time 0.69 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 182684 kb
Host smart-54ad4ecf-f0e9-4b0b-ad17-462ef45b757f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898464131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3898464131
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2320098345
Short name T182
Test name
Test status
Simulation time 153272557815 ps
CPU time 131.76 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:04:42 PM PDT 24
Peak memory 183628 kb
Host smart-bc11dcc4-05ca-490d-9dfb-b082ec51b81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320098345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2320098345
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2004939043
Short name T263
Test name
Test status
Simulation time 595208125 ps
CPU time 0.8 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 183480 kb
Host smart-365e7820-f60d-4f49-b32c-45f122e334d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004939043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2004939043
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1403571481
Short name T218
Test name
Test status
Simulation time 19643342971 ps
CPU time 29.94 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:58 PM PDT 24
Peak memory 191808 kb
Host smart-cc1e3bcc-781c-49cc-adff-a62632ddc955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403571481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1403571481
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.641742144
Short name T173
Test name
Test status
Simulation time 412169884 ps
CPU time 0.97 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183552 kb
Host smart-c03125c6-6062-4d83-8f03-d3cb565b371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641742144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.641742144
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.168235410
Short name T211
Test name
Test status
Simulation time 431644213397 ps
CPU time 378.42 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:08:48 PM PDT 24
Peak memory 194384 kb
Host smart-cf001db5-ba40-4bd3-95dc-8d378fb9a13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168235410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.168235410
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2998144679
Short name T92
Test name
Test status
Simulation time 41822679290 ps
CPU time 428.96 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:09:38 PM PDT 24
Peak memory 198564 kb
Host smart-5706d9ae-f536-441b-a9de-123e59943577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998144679 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2998144679
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2411725223
Short name T267
Test name
Test status
Simulation time 387014874 ps
CPU time 0.69 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183496 kb
Host smart-f297467c-86fc-4fab-afb1-cda1925b2638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411725223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2411725223
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.586038758
Short name T177
Test name
Test status
Simulation time 41054009537 ps
CPU time 69.93 seconds
Started May 07 03:02:34 PM PDT 24
Finished May 07 03:03:46 PM PDT 24
Peak memory 183656 kb
Host smart-65f23fb8-f834-41bd-856f-de2aa84ee6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586038758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.586038758
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.706253692
Short name T145
Test name
Test status
Simulation time 492559080 ps
CPU time 0.71 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:32 PM PDT 24
Peak memory 183452 kb
Host smart-08e069e6-54ce-4380-8831-874f3fbfd435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706253692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.706253692
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.604821796
Short name T158
Test name
Test status
Simulation time 263844774709 ps
CPU time 210.88 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:06:01 PM PDT 24
Peak memory 194136 kb
Host smart-5a646dc3-a9dc-45d9-9243-006539d0b162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604821796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.604821796
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.526223370
Short name T183
Test name
Test status
Simulation time 383749403 ps
CPU time 1.03 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:02:30 PM PDT 24
Peak memory 183548 kb
Host smart-2b214ff6-6104-49dc-9870-a124cf4e8a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526223370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.526223370
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3292288384
Short name T29
Test name
Test status
Simulation time 35772101724 ps
CPU time 58.75 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:03:27 PM PDT 24
Peak memory 183828 kb
Host smart-94623dc6-751d-4c04-8568-a36f0a933cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292288384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3292288384
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3790514121
Short name T82
Test name
Test status
Simulation time 542971451 ps
CPU time 0.78 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183572 kb
Host smart-a796af1c-0acb-4b7f-887e-ae11e687a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790514121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3790514121
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3433950013
Short name T176
Test name
Test status
Simulation time 202686342816 ps
CPU time 41.63 seconds
Started May 07 03:02:25 PM PDT 24
Finished May 07 03:03:09 PM PDT 24
Peak memory 195180 kb
Host smart-f35ea461-5cd7-46a1-b21b-6247f4dcc0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433950013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3433950013
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3752711486
Short name T51
Test name
Test status
Simulation time 512754250 ps
CPU time 0.96 seconds
Started May 07 03:02:25 PM PDT 24
Finished May 07 03:02:27 PM PDT 24
Peak memory 183588 kb
Host smart-924a77e7-086a-493e-9e16-3f79f9e9b53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752711486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3752711486
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3444105154
Short name T205
Test name
Test status
Simulation time 51114853548 ps
CPU time 67.39 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:03:39 PM PDT 24
Peak memory 190952 kb
Host smart-9e380a80-e2e4-40bd-8dce-8463abe6613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444105154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3444105154
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.597208696
Short name T260
Test name
Test status
Simulation time 565327972 ps
CPU time 1.35 seconds
Started May 07 03:02:30 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 183576 kb
Host smart-0627ec66-eba7-449a-b890-e784781d2ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597208696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.597208696
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3716426808
Short name T222
Test name
Test status
Simulation time 164786012698 ps
CPU time 72.91 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:03:42 PM PDT 24
Peak memory 183624 kb
Host smart-0b462b29-c4e4-43da-b5d9-31f044b3faae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716426808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3716426808
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.4109589761
Short name T230
Test name
Test status
Simulation time 14583826264 ps
CPU time 156.84 seconds
Started May 07 03:02:25 PM PDT 24
Finished May 07 03:05:03 PM PDT 24
Peak memory 198480 kb
Host smart-187d8bcf-b41b-4b45-9852-00e25d653d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109589761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.4109589761
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2657636760
Short name T194
Test name
Test status
Simulation time 357956435 ps
CPU time 0.85 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:29 PM PDT 24
Peak memory 183552 kb
Host smart-e528681e-5468-4c50-8f69-49ca23b8ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657636760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2657636760
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.524283311
Short name T103
Test name
Test status
Simulation time 45241349837 ps
CPU time 61.43 seconds
Started May 07 03:02:24 PM PDT 24
Finished May 07 03:03:27 PM PDT 24
Peak memory 183644 kb
Host smart-97142c98-6ca1-4644-8b48-0059f86d33c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524283311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.524283311
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2448791433
Short name T84
Test name
Test status
Simulation time 426565535 ps
CPU time 0.7 seconds
Started May 07 03:02:30 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 183456 kb
Host smart-55d0d390-eacc-4ddf-90f0-1669620d3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448791433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2448791433
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.475191302
Short name T101
Test name
Test status
Simulation time 44050353468 ps
CPU time 64.95 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:03:37 PM PDT 24
Peak memory 183572 kb
Host smart-8bc0910d-9ac1-47a1-b588-45d48b702d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475191302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.475191302
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2091534024
Short name T48
Test name
Test status
Simulation time 499602747 ps
CPU time 0.9 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:35 PM PDT 24
Peak memory 183572 kb
Host smart-ca7ef5f1-1e4e-4979-8629-59292ae8bff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091534024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2091534024
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3121868847
Short name T125
Test name
Test status
Simulation time 38464793208 ps
CPU time 14.4 seconds
Started May 07 03:02:35 PM PDT 24
Finished May 07 03:02:51 PM PDT 24
Peak memory 191832 kb
Host smart-5f58b8a9-9a55-4ed9-a091-910a5cd0bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121868847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3121868847
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.917004363
Short name T143
Test name
Test status
Simulation time 359224027 ps
CPU time 1.12 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:35 PM PDT 24
Peak memory 183556 kb
Host smart-0df1dfe6-0b96-40d5-853e-4aafe3f62646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917004363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.917004363
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1199402705
Short name T198
Test name
Test status
Simulation time 60257485674 ps
CPU time 96.51 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:04:17 PM PDT 24
Peak memory 194040 kb
Host smart-c64e46a7-7a07-46b5-9000-2f484ad15b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199402705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1199402705
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.312126884
Short name T23
Test name
Test status
Simulation time 635247616 ps
CPU time 1.05 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:35 PM PDT 24
Peak memory 183500 kb
Host smart-5908ce47-0674-4718-844d-e69d9580966c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312126884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.312126884
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1747831958
Short name T9
Test name
Test status
Simulation time 51811935851 ps
CPU time 44.03 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:03:24 PM PDT 24
Peak memory 191776 kb
Host smart-85161ee1-76bb-49f3-a8f8-3d3c532ff938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747831958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1747831958
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.90297963
Short name T167
Test name
Test status
Simulation time 547291787 ps
CPU time 0.93 seconds
Started May 07 03:02:31 PM PDT 24
Finished May 07 03:02:34 PM PDT 24
Peak memory 183536 kb
Host smart-12e099a2-5672-4bc9-a01a-d370ae42f1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90297963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.90297963
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.133894917
Short name T132
Test name
Test status
Simulation time 192680053887 ps
CPU time 293.1 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:07:28 PM PDT 24
Peak memory 183688 kb
Host smart-e354b810-9001-401e-9321-ebe5981045ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133894917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.133894917
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2232734582
Short name T95
Test name
Test status
Simulation time 14212546322 ps
CPU time 105 seconds
Started May 07 03:02:34 PM PDT 24
Finished May 07 03:04:21 PM PDT 24
Peak memory 198532 kb
Host smart-80874196-61c1-4d80-9cb5-674576d398c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232734582 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2232734582
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2248024605
Short name T86
Test name
Test status
Simulation time 580562751 ps
CPU time 1.49 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183420 kb
Host smart-91c30e8f-4697-4289-8b75-dcd15b2f86f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248024605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2248024605
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1242885131
Short name T151
Test name
Test status
Simulation time 10197344462 ps
CPU time 14.49 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:02:50 PM PDT 24
Peak memory 183632 kb
Host smart-bbbf9586-2252-4af8-9e4a-5a6f0ad0a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242885131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1242885131
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.8713767
Short name T58
Test name
Test status
Simulation time 604580515 ps
CPU time 1.57 seconds
Started May 07 03:02:35 PM PDT 24
Finished May 07 03:02:38 PM PDT 24
Peak memory 183572 kb
Host smart-9e5b12cd-dcb6-4ff2-9c8a-f3457c6de6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8713767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.8713767
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2373309397
Short name T61
Test name
Test status
Simulation time 149022634995 ps
CPU time 59.42 seconds
Started May 07 03:02:35 PM PDT 24
Finished May 07 03:03:36 PM PDT 24
Peak memory 183640 kb
Host smart-175c2036-dd98-476f-bb5e-3801f752f4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373309397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2373309397
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.637978282
Short name T250
Test name
Test status
Simulation time 21030092952 ps
CPU time 154.44 seconds
Started May 07 03:02:31 PM PDT 24
Finished May 07 03:05:07 PM PDT 24
Peak memory 198568 kb
Host smart-170036de-0818-42ac-b832-c68e4c234f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637978282 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.637978282
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1838168597
Short name T200
Test name
Test status
Simulation time 355595841 ps
CPU time 1.05 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:35 PM PDT 24
Peak memory 183532 kb
Host smart-4fc0c615-e55a-447f-9bc4-fae3543f5264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838168597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1838168597
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1109528367
Short name T47
Test name
Test status
Simulation time 12576056873 ps
CPU time 18.53 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183432 kb
Host smart-cd2f7cec-0aad-46d7-87dc-3742e7c509bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109528367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1109528367
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.3602349628
Short name T208
Test name
Test status
Simulation time 474854018 ps
CPU time 0.72 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:02:36 PM PDT 24
Peak memory 183564 kb
Host smart-fe538b89-7687-4d4c-ac0b-fa75adf78dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602349628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.3602349628
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3767791098
Short name T97
Test name
Test status
Simulation time 118036296141 ps
CPU time 52.48 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:03:34 PM PDT 24
Peak memory 183320 kb
Host smart-bb823dc0-b275-440b-b3b9-a8fb8e9b6215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767791098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3767791098
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3801830233
Short name T12
Test name
Test status
Simulation time 92635678944 ps
CPU time 352.14 seconds
Started May 07 03:02:30 PM PDT 24
Finished May 07 03:08:25 PM PDT 24
Peak memory 198540 kb
Host smart-e7522df2-7da8-4909-96e8-8fe38fe7c2f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801830233 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3801830233
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1511126
Short name T123
Test name
Test status
Simulation time 514686025 ps
CPU time 1.37 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:02:22 PM PDT 24
Peak memory 183548 kb
Host smart-f715b56e-dbbe-4df1-9afe-d2260cafb4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1511126
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.682266051
Short name T129
Test name
Test status
Simulation time 22668454527 ps
CPU time 18.42 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:02:39 PM PDT 24
Peak memory 191824 kb
Host smart-8f364c9d-e75e-4a2c-bc03-163ed4f5b7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682266051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.682266051
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3918321912
Short name T20
Test name
Test status
Simulation time 4545699903 ps
CPU time 2.26 seconds
Started May 07 03:02:18 PM PDT 24
Finished May 07 03:02:21 PM PDT 24
Peak memory 215520 kb
Host smart-5466865d-4257-48be-b127-fe3e8ddd77fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918321912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3918321912
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1208533740
Short name T233
Test name
Test status
Simulation time 606314122 ps
CPU time 1.42 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:02:23 PM PDT 24
Peak memory 183544 kb
Host smart-60b0d3ee-7c75-49e7-ae63-cf0158692a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208533740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1208533740
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.400270215
Short name T170
Test name
Test status
Simulation time 30601298607 ps
CPU time 334.16 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:07:55 PM PDT 24
Peak memory 198524 kb
Host smart-a1e24892-0e98-4fbf-ba31-4b1d9bf23cda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400270215 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.400270215
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3189377916
Short name T187
Test name
Test status
Simulation time 501250587 ps
CPU time 0.74 seconds
Started May 07 03:02:31 PM PDT 24
Finished May 07 03:02:34 PM PDT 24
Peak memory 183564 kb
Host smart-96f7a817-6f04-4c2c-960d-d3b83a015852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189377916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3189377916
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2583225836
Short name T2
Test name
Test status
Simulation time 47422769347 ps
CPU time 68.46 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:03:44 PM PDT 24
Peak memory 183620 kb
Host smart-009ce7a9-b893-46ba-a327-e78c53266d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583225836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2583225836
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.350063903
Short name T234
Test name
Test status
Simulation time 402359070 ps
CPU time 1.18 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183304 kb
Host smart-496d6e0a-ad0e-4f73-925a-d420326f0037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350063903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.350063903
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2680970533
Short name T60
Test name
Test status
Simulation time 20023225085 ps
CPU time 7.97 seconds
Started May 07 03:02:34 PM PDT 24
Finished May 07 03:02:44 PM PDT 24
Peak memory 193936 kb
Host smart-2feb6646-0a9d-40d8-b0a3-07163c4c4855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680970533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2680970533
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2224394264
Short name T159
Test name
Test status
Simulation time 19741301567 ps
CPU time 158.09 seconds
Started May 07 03:02:36 PM PDT 24
Finished May 07 03:05:15 PM PDT 24
Peak memory 198592 kb
Host smart-a5086239-27bd-42b8-932e-a3cfc36227eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224394264 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2224394264
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.1533503426
Short name T239
Test name
Test status
Simulation time 388767507 ps
CPU time 1.06 seconds
Started May 07 03:02:35 PM PDT 24
Finished May 07 03:02:37 PM PDT 24
Peak memory 183556 kb
Host smart-1ee4e63c-fc15-4bb9-a482-aafb3b16d2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533503426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.1533503426
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4078030263
Short name T117
Test name
Test status
Simulation time 25640131391 ps
CPU time 18.68 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:03:00 PM PDT 24
Peak memory 183432 kb
Host smart-1e5956b2-ba7e-4296-b961-0cc5e68ff6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078030263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4078030263
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2998623892
Short name T85
Test name
Test status
Simulation time 567540808 ps
CPU time 0.88 seconds
Started May 07 03:02:31 PM PDT 24
Finished May 07 03:02:34 PM PDT 24
Peak memory 183556 kb
Host smart-d7631e04-a7b2-4b7f-a1d5-d04f50203738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998623892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2998623892
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2337311670
Short name T134
Test name
Test status
Simulation time 237147090966 ps
CPU time 371.76 seconds
Started May 07 03:02:35 PM PDT 24
Finished May 07 03:08:48 PM PDT 24
Peak memory 183600 kb
Host smart-6d334013-13b1-4fcd-b69a-0eaf43547f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337311670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2337311670
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1025046874
Short name T227
Test name
Test status
Simulation time 28125668525 ps
CPU time 204.76 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:06:06 PM PDT 24
Peak memory 198368 kb
Host smart-eff8fe8a-59c4-4e60-bf2a-33483fd669f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025046874 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1025046874
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.69299023
Short name T127
Test name
Test status
Simulation time 580890746 ps
CPU time 1.01 seconds
Started May 07 03:02:36 PM PDT 24
Finished May 07 03:02:38 PM PDT 24
Peak memory 183568 kb
Host smart-9a87a352-2c20-4701-a9c9-38d94d62b1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69299023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.69299023
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1158005621
Short name T126
Test name
Test status
Simulation time 44434823585 ps
CPU time 46.43 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:03:21 PM PDT 24
Peak memory 183448 kb
Host smart-263eb615-db23-4be3-b25b-7cd124155344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158005621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1158005621
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1334518293
Short name T179
Test name
Test status
Simulation time 511414143 ps
CPU time 0.77 seconds
Started May 07 03:02:36 PM PDT 24
Finished May 07 03:02:37 PM PDT 24
Peak memory 183572 kb
Host smart-a66c60a9-681b-43b1-b93f-99b73ea1aecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334518293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1334518293
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.24751812
Short name T149
Test name
Test status
Simulation time 212416736571 ps
CPU time 328.22 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:08:02 PM PDT 24
Peak memory 194200 kb
Host smart-cf2e41de-4d8b-4cec-a6cf-b26afe9d9556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_al
l.24751812
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.631280943
Short name T93
Test name
Test status
Simulation time 964433399267 ps
CPU time 815.69 seconds
Started May 07 03:02:33 PM PDT 24
Finished May 07 03:16:11 PM PDT 24
Peak memory 201712 kb
Host smart-39e2cbee-dad0-4bc3-b8a9-289c67d87e57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631280943 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.631280943
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.187821330
Short name T116
Test name
Test status
Simulation time 564601818 ps
CPU time 1.42 seconds
Started May 07 03:02:37 PM PDT 24
Finished May 07 03:02:40 PM PDT 24
Peak memory 183536 kb
Host smart-3857635f-3246-4200-8bb5-601e763d6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187821330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.187821330
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.863053167
Short name T188
Test name
Test status
Simulation time 5868649584 ps
CPU time 3.11 seconds
Started May 07 03:02:32 PM PDT 24
Finished May 07 03:02:37 PM PDT 24
Peak memory 183648 kb
Host smart-6020d38b-c2e2-4e91-bb38-d07049a3764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863053167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.863053167
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2506761913
Short name T219
Test name
Test status
Simulation time 405091958 ps
CPU time 1.03 seconds
Started May 07 03:02:30 PM PDT 24
Finished May 07 03:02:34 PM PDT 24
Peak memory 183572 kb
Host smart-347c1aaf-1ec8-4def-9d3e-bccaa7536fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506761913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2506761913
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.814630779
Short name T139
Test name
Test status
Simulation time 153728038652 ps
CPU time 259.72 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:07:01 PM PDT 24
Peak memory 195388 kb
Host smart-cca02929-5d58-49e4-8553-2cc57df8768a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814630779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.814630779
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1455452293
Short name T42
Test name
Test status
Simulation time 262070995724 ps
CPU time 561.66 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:12:01 PM PDT 24
Peak memory 198988 kb
Host smart-815451a0-c350-41a3-8c70-14e66d46e43c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455452293 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1455452293
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.40885371
Short name T223
Test name
Test status
Simulation time 480436847 ps
CPU time 1.39 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183536 kb
Host smart-b5e039dc-caa6-4c95-8105-760bc66d9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40885371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.40885371
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.459687854
Short name T232
Test name
Test status
Simulation time 36864599764 ps
CPU time 7.59 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:48 PM PDT 24
Peak memory 183636 kb
Host smart-5116b737-0222-40c1-b240-5be3edf51c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459687854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.459687854
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.4087510182
Short name T272
Test name
Test status
Simulation time 465957844 ps
CPU time 1.35 seconds
Started May 07 03:02:46 PM PDT 24
Finished May 07 03:02:49 PM PDT 24
Peak memory 183516 kb
Host smart-83e8caa4-b739-423b-970a-616e4c98443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087510182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.4087510182
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.45375750
Short name T191
Test name
Test status
Simulation time 290446663342 ps
CPU time 453.37 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:10:14 PM PDT 24
Peak memory 183648 kb
Host smart-83e546e0-a6a2-4657-815b-059fc28d8c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45375750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_al
l.45375750
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2302231852
Short name T44
Test name
Test status
Simulation time 22516016441 ps
CPU time 192.72 seconds
Started May 07 03:02:41 PM PDT 24
Finished May 07 03:05:55 PM PDT 24
Peak memory 198232 kb
Host smart-0a5147e3-0162-48d5-9813-29c7fbbb105b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302231852 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2302231852
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3747967417
Short name T165
Test name
Test status
Simulation time 371271430 ps
CPU time 0.7 seconds
Started May 07 03:02:41 PM PDT 24
Finished May 07 03:02:43 PM PDT 24
Peak memory 183360 kb
Host smart-f934ebad-6970-4c5d-a9a0-a40fa0eebce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747967417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3747967417
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1626037998
Short name T178
Test name
Test status
Simulation time 22265590021 ps
CPU time 17.07 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 191796 kb
Host smart-3c0f6af5-c94f-431c-9418-20331f706f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626037998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1626037998
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4149077804
Short name T150
Test name
Test status
Simulation time 484805048 ps
CPU time 0.73 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:41 PM PDT 24
Peak memory 183580 kb
Host smart-f4074e30-a822-4dc0-be91-19e1a4909009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149077804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4149077804
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.856315464
Short name T195
Test name
Test status
Simulation time 168180464199 ps
CPU time 353.82 seconds
Started May 07 03:02:41 PM PDT 24
Finished May 07 03:08:36 PM PDT 24
Peak memory 198600 kb
Host smart-7c9a204e-28ed-470d-9506-4a9878b457fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856315464 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.856315464
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2282563148
Short name T245
Test name
Test status
Simulation time 516827733 ps
CPU time 1.23 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:41 PM PDT 24
Peak memory 183568 kb
Host smart-d5844b96-84c1-40ee-ba74-aceea3de48e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282563148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2282563148
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3093124429
Short name T26
Test name
Test status
Simulation time 16944528526 ps
CPU time 22.9 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:03:02 PM PDT 24
Peak memory 183616 kb
Host smart-cde45f55-e416-4456-85e6-06a17a8f7212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093124429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3093124429
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.513541308
Short name T192
Test name
Test status
Simulation time 608445279 ps
CPU time 0.61 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183580 kb
Host smart-82a1359d-8f83-4c09-a0a3-bc4766451ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513541308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.513541308
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3293780498
Short name T138
Test name
Test status
Simulation time 47406087705 ps
CPU time 19.15 seconds
Started May 07 03:02:37 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 183624 kb
Host smart-1b12e02b-8a06-4a89-90e6-e843411b483c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293780498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3293780498
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1651164676
Short name T43
Test name
Test status
Simulation time 62788533135 ps
CPU time 690.73 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:14:12 PM PDT 24
Peak memory 199520 kb
Host smart-d9bb8331-7ab7-41ff-97e2-64f27f6d18c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651164676 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1651164676
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2724559794
Short name T53
Test name
Test status
Simulation time 362272058 ps
CPU time 0.85 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:40 PM PDT 24
Peak memory 183560 kb
Host smart-abc1ce2d-26aa-4bae-af44-84efc38ffcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724559794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2724559794
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2236384751
Short name T133
Test name
Test status
Simulation time 39030364995 ps
CPU time 15.49 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:55 PM PDT 24
Peak memory 191832 kb
Host smart-b219b870-14ae-4a65-912a-28e2a9f52f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236384751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2236384751
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1910827042
Short name T258
Test name
Test status
Simulation time 530630192 ps
CPU time 0.74 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183564 kb
Host smart-de15d89a-3b2a-4f5e-a974-6cdd5fa77987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910827042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1910827042
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1461513822
Short name T59
Test name
Test status
Simulation time 34641407060 ps
CPU time 217.29 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:06:18 PM PDT 24
Peak memory 198584 kb
Host smart-fa3568ed-d56c-40f6-924f-c4a0bce2c794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461513822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1461513822
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4111676594
Short name T261
Test name
Test status
Simulation time 641942961 ps
CPU time 0.64 seconds
Started May 07 03:02:41 PM PDT 24
Finished May 07 03:02:43 PM PDT 24
Peak memory 183568 kb
Host smart-02b9ba47-11a1-42b6-b0cb-a8201729a401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111676594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4111676594
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3947572979
Short name T169
Test name
Test status
Simulation time 20231470918 ps
CPU time 3.28 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:02:45 PM PDT 24
Peak memory 191836 kb
Host smart-e7497ea2-1a08-4fcd-be98-b0cc8f744721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947572979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3947572979
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3716338846
Short name T142
Test name
Test status
Simulation time 546171895 ps
CPU time 1.27 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183552 kb
Host smart-3a1a40aa-e0fb-46ed-bd81-699a3c3eea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716338846 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3716338846
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.121597300
Short name T247
Test name
Test status
Simulation time 267637497552 ps
CPU time 92.14 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:04:13 PM PDT 24
Peak memory 191816 kb
Host smart-a663cdd1-0a8e-44d6-8eda-50d4dbe1f124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121597300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.121597300
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2698274232
Short name T228
Test name
Test status
Simulation time 63911424554 ps
CPU time 321.82 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:08:03 PM PDT 24
Peak memory 198484 kb
Host smart-454662a4-53e1-4ac6-97ec-d76391983827
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698274232 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2698274232
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2048210027
Short name T257
Test name
Test status
Simulation time 575598377 ps
CPU time 1.49 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:42 PM PDT 24
Peak memory 183500 kb
Host smart-d259ff71-a68f-4609-b22e-e7ac4714009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048210027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2048210027
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.398385730
Short name T193
Test name
Test status
Simulation time 10166938664 ps
CPU time 16.72 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:02:58 PM PDT 24
Peak memory 183640 kb
Host smart-9d3bce78-0bcb-4b08-8ff5-8809fcde985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398385730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.398385730
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.684472907
Short name T156
Test name
Test status
Simulation time 445321373 ps
CPU time 1.21 seconds
Started May 07 03:02:45 PM PDT 24
Finished May 07 03:02:47 PM PDT 24
Peak memory 183512 kb
Host smart-b503dfff-a0f9-41eb-85f8-5afd122e9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684472907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.684472907
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.894651188
Short name T209
Test name
Test status
Simulation time 212574460111 ps
CPU time 83.51 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:04:03 PM PDT 24
Peak memory 194140 kb
Host smart-bd2b07a0-4bc1-4b71-8b8e-2bd6caab0999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894651188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.894651188
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.275874505
Short name T262
Test name
Test status
Simulation time 27537024710 ps
CPU time 229.99 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:06:32 PM PDT 24
Peak memory 198540 kb
Host smart-6da4334b-d180-468f-8985-1b6d365afc21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275874505 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.275874505
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2206402612
Short name T144
Test name
Test status
Simulation time 511793987 ps
CPU time 1.29 seconds
Started May 07 03:02:19 PM PDT 24
Finished May 07 03:02:21 PM PDT 24
Peak memory 183512 kb
Host smart-13537a93-37cf-431d-921a-1b4b3cdfa968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206402612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2206402612
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.830252266
Short name T163
Test name
Test status
Simulation time 27949222709 ps
CPU time 11.72 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:02:36 PM PDT 24
Peak memory 183616 kb
Host smart-f4fbc2a0-0488-4fdf-ba2a-7702a82dcacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830252266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.830252266
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2252781192
Short name T16
Test name
Test status
Simulation time 4177485897 ps
CPU time 2.39 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:02:26 PM PDT 24
Peak memory 214884 kb
Host smart-e6e02219-5be7-4e60-a8b1-ecf6257f8ab1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252781192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2252781192
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1711808406
Short name T22
Test name
Test status
Simulation time 418552850 ps
CPU time 1.18 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:02:25 PM PDT 24
Peak memory 183572 kb
Host smart-b81a0953-0937-4776-bfb2-df80301efd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711808406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1711808406
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1701486789
Short name T17
Test name
Test status
Simulation time 182689212246 ps
CPU time 77 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:03:39 PM PDT 24
Peak memory 183628 kb
Host smart-a25c3a3b-53c9-44c6-98df-fd9b7d1d4b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701486789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1701486789
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1134902599
Short name T181
Test name
Test status
Simulation time 22034974087 ps
CPU time 119.82 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:04:22 PM PDT 24
Peak memory 198632 kb
Host smart-ec3644e8-eb49-4252-8177-0ec77478f5cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134902599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1134902599
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.262687127
Short name T268
Test name
Test status
Simulation time 614504113 ps
CPU time 0.74 seconds
Started May 07 03:02:38 PM PDT 24
Finished May 07 03:02:40 PM PDT 24
Peak memory 183532 kb
Host smart-90279bf3-c6d2-444f-9560-babfd622a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262687127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.262687127
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.1553752367
Short name T252
Test name
Test status
Simulation time 37305780879 ps
CPU time 14.58 seconds
Started May 07 03:02:41 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 183136 kb
Host smart-cd125b68-260e-46be-bf2b-5d24fd58247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553752367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.1553752367
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3961763354
Short name T137
Test name
Test status
Simulation time 519035278 ps
CPU time 1.41 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:02:43 PM PDT 24
Peak memory 183564 kb
Host smart-a588a449-2c73-43c7-8b9b-b6989a9c3801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961763354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3961763354
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1579562902
Short name T155
Test name
Test status
Simulation time 82479507428 ps
CPU time 44.8 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:03:25 PM PDT 24
Peak memory 183608 kb
Host smart-1637f5db-e639-4904-97f9-edf84e3dfd7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579562902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1579562902
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.243438634
Short name T56
Test name
Test status
Simulation time 66202139978 ps
CPU time 588.17 seconds
Started May 07 03:02:39 PM PDT 24
Finished May 07 03:12:29 PM PDT 24
Peak memory 198544 kb
Host smart-349a9da4-9612-4d3f-9785-b5f310a674bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243438634 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.243438634
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2217819338
Short name T215
Test name
Test status
Simulation time 480638205 ps
CPU time 0.73 seconds
Started May 07 03:02:46 PM PDT 24
Finished May 07 03:02:47 PM PDT 24
Peak memory 183572 kb
Host smart-29df1b92-c9c5-4a24-a23a-db1cc17d1304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217819338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2217819338
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2788042111
Short name T243
Test name
Test status
Simulation time 14795268929 ps
CPU time 20.95 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:03:05 PM PDT 24
Peak memory 183596 kb
Host smart-1efa9bd4-4fbc-4357-a06c-0a25a463f5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788042111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2788042111
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2054469604
Short name T264
Test name
Test status
Simulation time 439721546 ps
CPU time 1.17 seconds
Started May 07 03:02:40 PM PDT 24
Finished May 07 03:02:43 PM PDT 24
Peak memory 183556 kb
Host smart-6ccbc895-7674-4191-b2ed-5c73a2677bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054469604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2054469604
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2023582512
Short name T254
Test name
Test status
Simulation time 101408617760 ps
CPU time 152.6 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:05:17 PM PDT 24
Peak memory 193892 kb
Host smart-5832921a-ae6b-48be-bbda-721c5db42a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023582512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2023582512
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.632724875
Short name T91
Test name
Test status
Simulation time 290342479177 ps
CPU time 355.15 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:08:40 PM PDT 24
Peak memory 198552 kb
Host smart-0d514914-c8c1-4c77-b475-efa21ed63ee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632724875 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.632724875
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.721237502
Short name T154
Test name
Test status
Simulation time 576804895 ps
CPU time 0.94 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:02:45 PM PDT 24
Peak memory 183544 kb
Host smart-b6c5f5a6-24b7-43f5-b1de-7a1929f96c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721237502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.721237502
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2850073689
Short name T135
Test name
Test status
Simulation time 19213788637 ps
CPU time 29.81 seconds
Started May 07 03:02:48 PM PDT 24
Finished May 07 03:03:19 PM PDT 24
Peak memory 183568 kb
Host smart-5916df94-1b10-47a1-9328-6832e09f3466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850073689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2850073689
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.931965613
Short name T146
Test name
Test status
Simulation time 540662577 ps
CPU time 1.36 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183580 kb
Host smart-d1357937-d66f-4ac3-976e-16a56d218871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931965613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.931965613
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3130882041
Short name T148
Test name
Test status
Simulation time 256098534549 ps
CPU time 191.08 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:06:04 PM PDT 24
Peak memory 195252 kb
Host smart-50c81744-341e-4f34-ac9a-bce8b57f64d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130882041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3130882041
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.152645932
Short name T269
Test name
Test status
Simulation time 60298442430 ps
CPU time 670.7 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:14:02 PM PDT 24
Peak memory 198988 kb
Host smart-89d6a454-5f2c-4b14-9284-cbe3d7e61133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152645932 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.152645932
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1664107853
Short name T124
Test name
Test status
Simulation time 715223181 ps
CPU time 0.6 seconds
Started May 07 03:02:45 PM PDT 24
Finished May 07 03:02:46 PM PDT 24
Peak memory 183576 kb
Host smart-e34aad9a-9da5-4b81-8015-c3fdce8ef8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664107853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1664107853
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4093220088
Short name T98
Test name
Test status
Simulation time 3102856921 ps
CPU time 1.66 seconds
Started May 07 03:02:44 PM PDT 24
Finished May 07 03:02:47 PM PDT 24
Peak memory 183580 kb
Host smart-d0036bd5-5d8d-498a-9950-0716b4d37d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093220088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4093220088
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2165573551
Short name T5
Test name
Test status
Simulation time 580531825 ps
CPU time 0.67 seconds
Started May 07 03:02:45 PM PDT 24
Finished May 07 03:02:47 PM PDT 24
Peak memory 183572 kb
Host smart-4578c8ba-8fd7-4cd6-a1d3-4edaeec4c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165573551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2165573551
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4055131753
Short name T55
Test name
Test status
Simulation time 113873119511 ps
CPU time 189.04 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:05:54 PM PDT 24
Peak memory 195236 kb
Host smart-3ba62856-5f91-40ea-8a71-a2a8148019b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055131753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4055131753
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4221145674
Short name T130
Test name
Test status
Simulation time 36145543044 ps
CPU time 200.63 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:06:12 PM PDT 24
Peak memory 198512 kb
Host smart-68b588be-04f6-4ecf-8791-57d0960788cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221145674 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4221145674
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4053151423
Short name T3
Test name
Test status
Simulation time 504497613 ps
CPU time 0.79 seconds
Started May 07 03:02:46 PM PDT 24
Finished May 07 03:02:47 PM PDT 24
Peak memory 183564 kb
Host smart-ad0ee4c7-ebcd-4eba-b262-b434473f6be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053151423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4053151423
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3185625493
Short name T162
Test name
Test status
Simulation time 12269795792 ps
CPU time 11.04 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:02:55 PM PDT 24
Peak memory 183600 kb
Host smart-71dcf139-1f82-4521-bd88-6d14cbfa7e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185625493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3185625493
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4172400510
Short name T266
Test name
Test status
Simulation time 483513275 ps
CPU time 0.72 seconds
Started May 07 03:02:42 PM PDT 24
Finished May 07 03:02:44 PM PDT 24
Peak memory 183580 kb
Host smart-86002c91-9780-4086-a943-adcfb889c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172400510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4172400510
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2638948699
Short name T236
Test name
Test status
Simulation time 134313904086 ps
CPU time 35.61 seconds
Started May 07 03:02:45 PM PDT 24
Finished May 07 03:03:22 PM PDT 24
Peak memory 183704 kb
Host smart-188e1d47-6cb1-4519-b460-b7fb08673ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638948699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2638948699
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2301544747
Short name T89
Test name
Test status
Simulation time 178586081801 ps
CPU time 378.91 seconds
Started May 07 03:02:49 PM PDT 24
Finished May 07 03:09:09 PM PDT 24
Peak memory 214312 kb
Host smart-f26556f0-5ac2-4a3d-970b-92fa7383f5b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301544747 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2301544747
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4129644678
Short name T259
Test name
Test status
Simulation time 412241953 ps
CPU time 1.17 seconds
Started May 07 03:02:44 PM PDT 24
Finished May 07 03:02:46 PM PDT 24
Peak memory 183556 kb
Host smart-5d3cb4bd-3e51-4fd0-b40b-76ff2d79acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129644678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4129644678
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3730159236
Short name T6
Test name
Test status
Simulation time 31508291135 ps
CPU time 44.71 seconds
Started May 07 03:02:44 PM PDT 24
Finished May 07 03:03:30 PM PDT 24
Peak memory 191820 kb
Host smart-c378a0eb-c85e-4779-96b8-2847428226fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730159236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3730159236
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2754346377
Short name T253
Test name
Test status
Simulation time 510412389 ps
CPU time 0.71 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:02:52 PM PDT 24
Peak memory 183544 kb
Host smart-973dd2c7-cf4f-499e-804d-272846be6fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754346377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2754346377
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3221694172
Short name T256
Test name
Test status
Simulation time 49132094039 ps
CPU time 264.48 seconds
Started May 07 03:02:45 PM PDT 24
Finished May 07 03:07:10 PM PDT 24
Peak memory 198596 kb
Host smart-e6067b8a-5f67-4e2f-b542-1ff1dc1ceecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221694172 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3221694172
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1729281441
Short name T197
Test name
Test status
Simulation time 426616234 ps
CPU time 0.72 seconds
Started May 07 03:02:44 PM PDT 24
Finished May 07 03:02:46 PM PDT 24
Peak memory 183560 kb
Host smart-2cffc89c-50c7-44b0-8a1b-3d36a8df5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729281441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1729281441
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.213762444
Short name T248
Test name
Test status
Simulation time 18446784745 ps
CPU time 24.96 seconds
Started May 07 03:02:44 PM PDT 24
Finished May 07 03:03:10 PM PDT 24
Peak memory 191852 kb
Host smart-bd86ab11-33af-41bf-a7b0-e3d2c72687fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213762444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.213762444
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2482812783
Short name T114
Test name
Test status
Simulation time 417292053 ps
CPU time 0.6 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183580 kb
Host smart-811d36bb-f87e-4638-8796-5ad2a6cb2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482812783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2482812783
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3578919490
Short name T203
Test name
Test status
Simulation time 144248763202 ps
CPU time 15.68 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:03:08 PM PDT 24
Peak memory 191784 kb
Host smart-51cc26f1-da5e-4c36-81bd-e9db242d5f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578919490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3578919490
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4028137583
Short name T90
Test name
Test status
Simulation time 214403915946 ps
CPU time 682.88 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:14:15 PM PDT 24
Peak memory 209020 kb
Host smart-c05a5623-d912-4d04-a2a0-97884ddde54e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028137583 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4028137583
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4281066989
Short name T216
Test name
Test status
Simulation time 387541217 ps
CPU time 1.12 seconds
Started May 07 03:02:43 PM PDT 24
Finished May 07 03:02:45 PM PDT 24
Peak memory 183532 kb
Host smart-9bdcc3b5-5752-4c83-b58f-48b93c7cea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281066989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4281066989
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.4122972285
Short name T185
Test name
Test status
Simulation time 35182154950 ps
CPU time 28.07 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:03:20 PM PDT 24
Peak memory 191804 kb
Host smart-866f2c54-c0b2-4f0c-b067-d6c48cf36d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122972285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.4122972285
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4132958780
Short name T161
Test name
Test status
Simulation time 460432472 ps
CPU time 1.25 seconds
Started May 07 03:02:48 PM PDT 24
Finished May 07 03:02:50 PM PDT 24
Peak memory 183460 kb
Host smart-4068f2a2-50cb-4d42-a507-81508dc9ba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132958780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4132958780
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1606637129
Short name T100
Test name
Test status
Simulation time 112113203198 ps
CPU time 74.51 seconds
Started May 07 03:02:46 PM PDT 24
Finished May 07 03:04:01 PM PDT 24
Peak memory 183640 kb
Host smart-cb979356-c053-4621-a032-d26dee5c5e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606637129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1606637129
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3826601109
Short name T131
Test name
Test status
Simulation time 553688914 ps
CPU time 1.38 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:55 PM PDT 24
Peak memory 183524 kb
Host smart-d70b08ca-2c23-4ae6-aab9-6f5003ebb800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826601109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3826601109
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.533211235
Short name T21
Test name
Test status
Simulation time 31343920450 ps
CPU time 13.22 seconds
Started May 07 03:02:48 PM PDT 24
Finished May 07 03:03:02 PM PDT 24
Peak memory 183656 kb
Host smart-359ee325-235c-4647-8c32-96a2f1cc95f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533211235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.533211235
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.897834492
Short name T54
Test name
Test status
Simulation time 578072125 ps
CPU time 1.46 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183512 kb
Host smart-b72a547c-c9f2-4c1e-9486-a23b5b61ac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897834492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.897834492
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1543637468
Short name T157
Test name
Test status
Simulation time 302506321087 ps
CPU time 505.88 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:11:19 PM PDT 24
Peak memory 195488 kb
Host smart-babc0107-2f1d-4e35-bd9a-20da599645b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543637468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1543637468
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1075030589
Short name T251
Test name
Test status
Simulation time 25150340301 ps
CPU time 212.63 seconds
Started May 07 03:02:49 PM PDT 24
Finished May 07 03:06:22 PM PDT 24
Peak memory 198596 kb
Host smart-d59a5523-3708-4f23-accf-a3a142dbe800
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075030589 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1075030589
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3131044594
Short name T201
Test name
Test status
Simulation time 388458661 ps
CPU time 0.65 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183564 kb
Host smart-4dbfc8b3-5b1e-436f-ab90-9984f85b48c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131044594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3131044594
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.230897738
Short name T115
Test name
Test status
Simulation time 8985613019 ps
CPU time 13.72 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:03:07 PM PDT 24
Peak memory 183624 kb
Host smart-100d9f16-ad34-4ac7-8073-ef09258eb405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230897738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.230897738
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3267616627
Short name T136
Test name
Test status
Simulation time 472806446 ps
CPU time 0.59 seconds
Started May 07 03:02:47 PM PDT 24
Finished May 07 03:02:48 PM PDT 24
Peak memory 183544 kb
Host smart-626b0515-da56-403f-a25a-2403183dc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267616627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3267616627
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.894792221
Short name T24
Test name
Test status
Simulation time 625186189727 ps
CPU time 260.19 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:07:12 PM PDT 24
Peak memory 198556 kb
Host smart-7917672d-f4f3-40ba-8002-70881767f89a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894792221 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.894792221
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1445722445
Short name T199
Test name
Test status
Simulation time 541455481 ps
CPU time 1.34 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:25 PM PDT 24
Peak memory 183536 kb
Host smart-5d0955f6-18e5-4267-85e5-c48e3a514193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445722445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1445722445
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2595731600
Short name T189
Test name
Test status
Simulation time 26387171629 ps
CPU time 8.53 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 191840 kb
Host smart-fef021d6-7e3b-42f1-947e-8b203bfec63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595731600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2595731600
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3699733301
Short name T19
Test name
Test status
Simulation time 8720917708 ps
CPU time 1.51 seconds
Started May 07 03:02:24 PM PDT 24
Finished May 07 03:02:27 PM PDT 24
Peak memory 215624 kb
Host smart-b17c64a9-f724-477e-8541-731cd4b30153
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699733301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3699733301
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1980813036
Short name T31
Test name
Test status
Simulation time 526740816 ps
CPU time 0.73 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:02:23 PM PDT 24
Peak memory 183552 kb
Host smart-b008ac97-3fb0-4203-b646-fc8c7bbf6a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980813036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1980813036
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2248619831
Short name T18
Test name
Test status
Simulation time 220469875817 ps
CPU time 164.72 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:05:06 PM PDT 24
Peak memory 183628 kb
Host smart-c0cfc757-2bc3-4425-8d71-bdcb8cfc7468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248619831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2248619831
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2709094311
Short name T88
Test name
Test status
Simulation time 75015779843 ps
CPU time 299.63 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:07:21 PM PDT 24
Peak memory 198568 kb
Host smart-90e91b33-3691-4f71-a5f2-feba273d08bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709094311 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2709094311
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2829118582
Short name T49
Test name
Test status
Simulation time 569427673 ps
CPU time 0.85 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183568 kb
Host smart-e68d3dad-a8e7-40da-b0db-67bb81b15402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829118582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2829118582
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2388646661
Short name T105
Test name
Test status
Simulation time 35011436544 ps
CPU time 14.24 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:03:05 PM PDT 24
Peak memory 183596 kb
Host smart-a62d3744-22e9-4666-bbdf-2ca329cd5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388646661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2388646661
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3777140782
Short name T28
Test name
Test status
Simulation time 416471791 ps
CPU time 0.85 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183572 kb
Host smart-b78045dc-fa0c-4d37-a87f-885fd67b9860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777140782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3777140782
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1701733875
Short name T204
Test name
Test status
Simulation time 34728614834 ps
CPU time 97.08 seconds
Started May 07 03:02:48 PM PDT 24
Finished May 07 03:04:25 PM PDT 24
Peak memory 198532 kb
Host smart-7ba58a1e-f56b-479c-915d-7f225ac92b97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701733875 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1701733875
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2746598184
Short name T229
Test name
Test status
Simulation time 456566959 ps
CPU time 0.7 seconds
Started May 07 03:02:48 PM PDT 24
Finished May 07 03:02:50 PM PDT 24
Peak memory 183548 kb
Host smart-9fd700a0-5be2-466e-bf2a-cc05039885ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746598184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2746598184
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2108741995
Short name T160
Test name
Test status
Simulation time 50927818438 ps
CPU time 36.65 seconds
Started May 07 03:02:53 PM PDT 24
Finished May 07 03:03:31 PM PDT 24
Peak memory 191780 kb
Host smart-fee72277-02db-42c6-8f48-0789b320c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108741995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2108741995
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2344622917
Short name T4
Test name
Test status
Simulation time 431229242 ps
CPU time 1.21 seconds
Started May 07 03:02:53 PM PDT 24
Finished May 07 03:02:55 PM PDT 24
Peak memory 183520 kb
Host smart-e5c7c247-af1b-47d4-89c1-e679d441c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344622917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2344622917
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.522193423
Short name T221
Test name
Test status
Simulation time 209007137752 ps
CPU time 33.18 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:03:27 PM PDT 24
Peak memory 183584 kb
Host smart-0ede9cde-95f0-476d-bebf-bcfcc8a563b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522193423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.522193423
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2269993325
Short name T225
Test name
Test status
Simulation time 516846719 ps
CPU time 1.16 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183552 kb
Host smart-ecc642de-07ee-4729-946e-de208bc375d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269993325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2269993325
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.608071757
Short name T186
Test name
Test status
Simulation time 13006129935 ps
CPU time 1.87 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183644 kb
Host smart-c6adbcdc-3c89-4bc4-bbf6-5966682f1bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608071757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.608071757
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1289335097
Short name T30
Test name
Test status
Simulation time 380417834 ps
CPU time 0.81 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183540 kb
Host smart-52898e98-1f8c-4e45-88e4-df4677d741d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289335097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1289335097
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2944494110
Short name T210
Test name
Test status
Simulation time 97676226999 ps
CPU time 145.18 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:05:17 PM PDT 24
Peak memory 194512 kb
Host smart-5c72f5cd-b47c-44c0-af41-0836661b630a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944494110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2944494110
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.272793607
Short name T13
Test name
Test status
Simulation time 52583942352 ps
CPU time 412.06 seconds
Started May 07 03:02:49 PM PDT 24
Finished May 07 03:09:42 PM PDT 24
Peak memory 198560 kb
Host smart-2c1496f2-4849-44bc-8101-66d9a5491a5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272793607 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.272793607
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4108696251
Short name T27
Test name
Test status
Simulation time 460365259 ps
CPU time 0.69 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183568 kb
Host smart-afd85e6e-a182-41e6-8378-e486481f63c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108696251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4108696251
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2687310680
Short name T180
Test name
Test status
Simulation time 26667416857 ps
CPU time 36.62 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:03:28 PM PDT 24
Peak memory 183624 kb
Host smart-645e790a-6ba4-430d-9b93-f26470ba125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687310680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2687310680
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.350612716
Short name T8
Test name
Test status
Simulation time 425074169 ps
CPU time 1.16 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:02:55 PM PDT 24
Peak memory 183564 kb
Host smart-7ee07352-2541-4d0d-bf84-c2582b3a1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350612716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.350612716
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1906875443
Short name T102
Test name
Test status
Simulation time 196242029397 ps
CPU time 70.55 seconds
Started May 07 03:02:52 PM PDT 24
Finished May 07 03:04:04 PM PDT 24
Peak memory 183792 kb
Host smart-33a8ef5a-69e4-4d28-8ace-717bd22df249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906875443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1906875443
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3666948521
Short name T52
Test name
Test status
Simulation time 160170767469 ps
CPU time 645.05 seconds
Started May 07 03:02:49 PM PDT 24
Finished May 07 03:13:36 PM PDT 24
Peak memory 200400 kb
Host smart-17c65222-433f-4679-b419-0a4e807ef76b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666948521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3666948521
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1366509457
Short name T168
Test name
Test status
Simulation time 408528640 ps
CPU time 1.16 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183540 kb
Host smart-fea111cf-f346-41f3-b235-52ec6a4c0a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366509457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1366509457
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3929453912
Short name T99
Test name
Test status
Simulation time 17483844447 ps
CPU time 14.58 seconds
Started May 07 03:02:53 PM PDT 24
Finished May 07 03:03:08 PM PDT 24
Peak memory 191632 kb
Host smart-5e793e92-75c1-4e19-ae21-d931311a3529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929453912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3929453912
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3481838546
Short name T174
Test name
Test status
Simulation time 599600559 ps
CPU time 1.03 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 183508 kb
Host smart-47276981-e391-49c9-82a5-305584f0544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481838546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3481838546
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2043824233
Short name T231
Test name
Test status
Simulation time 110937838291 ps
CPU time 159.1 seconds
Started May 07 03:02:49 PM PDT 24
Finished May 07 03:05:30 PM PDT 24
Peak memory 195156 kb
Host smart-ebc06bb7-4ab3-4c42-b4ac-d2ff90e2db5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043824233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2043824233
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1855330241
Short name T246
Test name
Test status
Simulation time 529892891912 ps
CPU time 809.56 seconds
Started May 07 03:02:50 PM PDT 24
Finished May 07 03:16:21 PM PDT 24
Peak memory 202840 kb
Host smart-4bc85c83-61bc-4f15-9b72-e8dc7ff6bcb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855330241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1855330241
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2452452599
Short name T213
Test name
Test status
Simulation time 579274295 ps
CPU time 1.34 seconds
Started May 07 03:02:56 PM PDT 24
Finished May 07 03:02:59 PM PDT 24
Peak memory 183540 kb
Host smart-c3ab2486-4953-490a-801f-32d7c5c26753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452452599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2452452599
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3487081512
Short name T241
Test name
Test status
Simulation time 44664184813 ps
CPU time 20.44 seconds
Started May 07 03:02:55 PM PDT 24
Finished May 07 03:03:17 PM PDT 24
Peak memory 191880 kb
Host smart-a3ab75e7-ccc5-4788-9cfa-22875ade0705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487081512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3487081512
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.633432732
Short name T238
Test name
Test status
Simulation time 489208998 ps
CPU time 1.28 seconds
Started May 07 03:02:51 PM PDT 24
Finished May 07 03:02:54 PM PDT 24
Peak memory 183568 kb
Host smart-2420a0b0-24c0-498f-9969-f608a30f641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633432732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.633432732
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3875723255
Short name T212
Test name
Test status
Simulation time 87653479481 ps
CPU time 63.86 seconds
Started May 07 03:03:02 PM PDT 24
Finished May 07 03:04:07 PM PDT 24
Peak memory 193644 kb
Host smart-46c60be4-7aa6-4599-9288-e4288aaee098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875723255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3875723255
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3770918200
Short name T62
Test name
Test status
Simulation time 59571403206 ps
CPU time 352.71 seconds
Started May 07 03:02:57 PM PDT 24
Finished May 07 03:08:51 PM PDT 24
Peak memory 198512 kb
Host smart-be645b34-ca1c-45f9-a028-7cf11f96e5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770918200 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3770918200
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1217610361
Short name T121
Test name
Test status
Simulation time 532089961 ps
CPU time 0.61 seconds
Started May 07 03:02:56 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 183560 kb
Host smart-1dd27f2c-29be-4595-b78b-1340626ecd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217610361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1217610361
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3950486917
Short name T217
Test name
Test status
Simulation time 23345572807 ps
CPU time 9.42 seconds
Started May 07 03:02:57 PM PDT 24
Finished May 07 03:03:07 PM PDT 24
Peak memory 191840 kb
Host smart-766e3c35-2b1a-4b62-83f4-d0ba9eaf4313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950486917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3950486917
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.84983139
Short name T214
Test name
Test status
Simulation time 413708297 ps
CPU time 0.82 seconds
Started May 07 03:02:54 PM PDT 24
Finished May 07 03:02:56 PM PDT 24
Peak memory 183492 kb
Host smart-f25e7d5f-c901-44fe-81f8-0e9af3624ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84983139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.84983139
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.141808903
Short name T224
Test name
Test status
Simulation time 90138065401 ps
CPU time 34.54 seconds
Started May 07 03:03:02 PM PDT 24
Finished May 07 03:03:37 PM PDT 24
Peak memory 183632 kb
Host smart-efc7c9cf-5bd2-4474-bfd8-0d3454da2a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141808903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.141808903
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.990660528
Short name T237
Test name
Test status
Simulation time 93839159539 ps
CPU time 240.14 seconds
Started May 07 03:02:55 PM PDT 24
Finished May 07 03:06:56 PM PDT 24
Peak memory 198536 kb
Host smart-7e2470db-caf5-44a0-9c41-0b0e4bdb02f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990660528 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.990660528
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3360756905
Short name T202
Test name
Test status
Simulation time 435141864 ps
CPU time 1.21 seconds
Started May 07 03:02:59 PM PDT 24
Finished May 07 03:03:01 PM PDT 24
Peak memory 183552 kb
Host smart-b2df0df6-812d-4a61-88ae-656a87102bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360756905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3360756905
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1993388327
Short name T11
Test name
Test status
Simulation time 13081086050 ps
CPU time 3.75 seconds
Started May 07 03:02:55 PM PDT 24
Finished May 07 03:03:00 PM PDT 24
Peak memory 183604 kb
Host smart-f5b50574-2238-4c53-8927-34782b07d82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993388327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1993388327
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2283768720
Short name T25
Test name
Test status
Simulation time 482355372 ps
CPU time 0.76 seconds
Started May 07 03:02:56 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 183512 kb
Host smart-0fe37282-a9fb-4b98-bec2-bbc567715f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283768720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2283768720
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2452573774
Short name T220
Test name
Test status
Simulation time 112890155102 ps
CPU time 194.59 seconds
Started May 07 03:02:58 PM PDT 24
Finished May 07 03:06:13 PM PDT 24
Peak memory 183628 kb
Host smart-3ff31fba-60fa-4840-9b69-9c645a7cee06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452573774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2452573774
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4120418629
Short name T87
Test name
Test status
Simulation time 296157671493 ps
CPU time 408.08 seconds
Started May 07 03:02:56 PM PDT 24
Finished May 07 03:09:45 PM PDT 24
Peak memory 198540 kb
Host smart-32a820fe-c6c8-4c15-82aa-38ad01c06421
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120418629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4120418629
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2325109866
Short name T274
Test name
Test status
Simulation time 573708510 ps
CPU time 0.86 seconds
Started May 07 03:02:55 PM PDT 24
Finished May 07 03:02:57 PM PDT 24
Peak memory 183564 kb
Host smart-17ba6e83-ebea-4025-8e41-8c086fd5eb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325109866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2325109866
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3501699252
Short name T50
Test name
Test status
Simulation time 30278748235 ps
CPU time 11.05 seconds
Started May 07 03:03:01 PM PDT 24
Finished May 07 03:03:13 PM PDT 24
Peak memory 183184 kb
Host smart-e7559cea-b752-4494-a6a0-3a79014cf7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501699252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3501699252
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.634035016
Short name T122
Test name
Test status
Simulation time 437668064 ps
CPU time 0.75 seconds
Started May 07 03:03:02 PM PDT 24
Finished May 07 03:03:03 PM PDT 24
Peak memory 183532 kb
Host smart-3ae761dd-3818-409d-8471-c7ee6d30f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634035016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.634035016
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2501415108
Short name T255
Test name
Test status
Simulation time 360955738278 ps
CPU time 130.07 seconds
Started May 07 03:02:56 PM PDT 24
Finished May 07 03:05:07 PM PDT 24
Peak memory 193952 kb
Host smart-2a2df18f-b228-4986-b6dc-29650aa72992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501415108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2501415108
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1712546697
Short name T172
Test name
Test status
Simulation time 454122930 ps
CPU time 0.73 seconds
Started May 07 03:03:03 PM PDT 24
Finished May 07 03:03:05 PM PDT 24
Peak memory 183564 kb
Host smart-e7fdee64-f516-4be3-afea-69bde789cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712546697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1712546697
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1580367349
Short name T118
Test name
Test status
Simulation time 58869211885 ps
CPU time 24.01 seconds
Started May 07 03:03:04 PM PDT 24
Finished May 07 03:03:29 PM PDT 24
Peak memory 191836 kb
Host smart-1b5b2d62-c7fe-45a0-a57d-85b6a39c4c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580367349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1580367349
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4115204814
Short name T112
Test name
Test status
Simulation time 599891982 ps
CPU time 0.98 seconds
Started May 07 03:03:01 PM PDT 24
Finished May 07 03:03:03 PM PDT 24
Peak memory 183236 kb
Host smart-c8fa30d4-6778-4eba-af15-5719193dd0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115204814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4115204814
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1961261508
Short name T171
Test name
Test status
Simulation time 124218909959 ps
CPU time 51.04 seconds
Started May 07 03:03:03 PM PDT 24
Finished May 07 03:03:55 PM PDT 24
Peak memory 183628 kb
Host smart-b6fd1a0f-4135-49c3-9c19-c92c5ff3b015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961261508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1961261508
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.54389538
Short name T164
Test name
Test status
Simulation time 366791132 ps
CPU time 1 seconds
Started May 07 03:02:19 PM PDT 24
Finished May 07 03:02:21 PM PDT 24
Peak memory 183556 kb
Host smart-f111f1f9-c064-4fbe-a748-5adb55723639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54389538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.54389538
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.568515314
Short name T46
Test name
Test status
Simulation time 48760374896 ps
CPU time 7.19 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:02:30 PM PDT 24
Peak memory 183632 kb
Host smart-55a03e90-5ba3-4483-b1b3-c11aca91a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568515314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.568515314
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3754442266
Short name T240
Test name
Test status
Simulation time 435769563 ps
CPU time 0.71 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:02:25 PM PDT 24
Peak memory 183572 kb
Host smart-af59ba5e-3e32-47d4-891f-6a328956b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754442266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3754442266
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3158574194
Short name T141
Test name
Test status
Simulation time 409362743104 ps
CPU time 646.06 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:13:10 PM PDT 24
Peak memory 194108 kb
Host smart-71adf1ad-f644-410d-8878-b1ea9f697741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158574194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3158574194
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1652503751
Short name T244
Test name
Test status
Simulation time 656081470543 ps
CPU time 1290.26 seconds
Started May 07 03:02:21 PM PDT 24
Finished May 07 03:23:52 PM PDT 24
Peak memory 207372 kb
Host smart-1cce2b55-5c41-44fd-8a2e-4ae5fddef9a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652503751 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1652503751
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4038712286
Short name T270
Test name
Test status
Simulation time 532654779 ps
CPU time 1.3 seconds
Started May 07 03:02:24 PM PDT 24
Finished May 07 03:02:27 PM PDT 24
Peak memory 183580 kb
Host smart-df8b67b6-05bd-4c5a-9552-018506f83281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038712286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4038712286
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1942198345
Short name T226
Test name
Test status
Simulation time 14218501594 ps
CPU time 5.92 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:30 PM PDT 24
Peak memory 191684 kb
Host smart-c554ead1-1a89-42bf-b21f-65c37d2d0fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942198345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1942198345
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3106844527
Short name T265
Test name
Test status
Simulation time 372754998 ps
CPU time 0.66 seconds
Started May 07 03:02:23 PM PDT 24
Finished May 07 03:02:25 PM PDT 24
Peak memory 183452 kb
Host smart-8c95ca9a-198c-448c-9f66-8037e661acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106844527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3106844527
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1643297002
Short name T147
Test name
Test status
Simulation time 88116520309 ps
CPU time 30.01 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:53 PM PDT 24
Peak memory 195500 kb
Host smart-3a9ad4da-90b3-4a60-92a5-401de5cfb9af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643297002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1643297002
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.356327185
Short name T207
Test name
Test status
Simulation time 20625885647 ps
CPU time 216.61 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:05:58 PM PDT 24
Peak memory 198552 kb
Host smart-d2530112-7ab5-4e9a-8dfe-42a205303be2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356327185 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.356327185
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1629567137
Short name T196
Test name
Test status
Simulation time 333878684 ps
CPU time 1.06 seconds
Started May 07 03:02:34 PM PDT 24
Finished May 07 03:02:37 PM PDT 24
Peak memory 183568 kb
Host smart-df8b432d-304e-4fa2-a034-47b2c4f197d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629567137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1629567137
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2509770931
Short name T128
Test name
Test status
Simulation time 11596796209 ps
CPU time 19.44 seconds
Started May 07 03:02:20 PM PDT 24
Finished May 07 03:02:41 PM PDT 24
Peak memory 183624 kb
Host smart-2eba4f0a-34b2-4647-8e1d-884833bea93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509770931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2509770931
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3121879190
Short name T113
Test name
Test status
Simulation time 455143418 ps
CPU time 0.72 seconds
Started May 07 03:02:22 PM PDT 24
Finished May 07 03:02:24 PM PDT 24
Peak memory 183544 kb
Host smart-2f293f2d-7de6-4ae0-bcdc-c3ed0810bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121879190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3121879190
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3180104165
Short name T249
Test name
Test status
Simulation time 107935295366 ps
CPU time 82.64 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:03:52 PM PDT 24
Peak memory 193656 kb
Host smart-922818b2-92f1-4d5a-a83e-fe8e33b0712e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180104165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3180104165
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.3148901147
Short name T96
Test name
Test status
Simulation time 47438745591 ps
CPU time 373.67 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:08:43 PM PDT 24
Peak memory 198520 kb
Host smart-094f6f9b-e2f4-407c-b414-96ca95e6da14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148901147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.3148901147
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2160433119
Short name T273
Test name
Test status
Simulation time 561483654 ps
CPU time 0.79 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183560 kb
Host smart-18d29b06-efce-4bb8-b838-f5af6145371b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160433119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2160433119
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.210525575
Short name T106
Test name
Test status
Simulation time 61164343222 ps
CPU time 5.31 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:33 PM PDT 24
Peak memory 183632 kb
Host smart-98850def-d326-4d32-a285-019d8341c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210525575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.210525575
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.2438349917
Short name T119
Test name
Test status
Simulation time 406465043 ps
CPU time 0.66 seconds
Started May 07 03:02:28 PM PDT 24
Finished May 07 03:02:31 PM PDT 24
Peak memory 183536 kb
Host smart-493a3cde-7aaa-4cbc-bf07-97161e9dd37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438349917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.2438349917
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1827193605
Short name T140
Test name
Test status
Simulation time 236089723952 ps
CPU time 90.23 seconds
Started May 07 03:02:27 PM PDT 24
Finished May 07 03:03:59 PM PDT 24
Peak memory 193700 kb
Host smart-00d1a6c4-002c-4428-b797-d95ced9a81a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827193605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1827193605
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2049512671
Short name T33
Test name
Test status
Simulation time 414217678 ps
CPU time 0.85 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:29 PM PDT 24
Peak memory 183560 kb
Host smart-7858553d-97a7-468e-9da2-e8f0047d4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049512671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2049512671
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3940441251
Short name T153
Test name
Test status
Simulation time 20092522421 ps
CPU time 29.1 seconds
Started May 07 03:02:29 PM PDT 24
Finished May 07 03:03:00 PM PDT 24
Peak memory 191832 kb
Host smart-178316d0-254c-4c68-87bb-5b73d385badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940441251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3940441251
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.985815105
Short name T120
Test name
Test status
Simulation time 555069526 ps
CPU time 0.81 seconds
Started May 07 03:02:26 PM PDT 24
Finished May 07 03:02:29 PM PDT 24
Peak memory 183528 kb
Host smart-6b97d905-e267-416e-bce9-26ddccee094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985815105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.985815105
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.3463708745
Short name T152
Test name
Test status
Simulation time 112650130884 ps
CPU time 174.65 seconds
Started May 07 03:02:34 PM PDT 24
Finished May 07 03:05:31 PM PDT 24
Peak memory 194224 kb
Host smart-4791367f-a4d1-4c1e-a4c5-050e3307342d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463708745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.3463708745
Directory /workspace/9.aon_timer_stress_all/latest
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