Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	338056	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4093232	1		T1	19		T2	16		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1089371	1		T1	1		T2	1		T3	1
values[0x0]	1565342	1		T1	9		T2	9		T3	13
values[0x1]	1776575	1		T1	12		T2	12		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151731	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4279557	1		T1	19		T2	18		T3	16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16084	1		T5	1		T8	656		T17	1
valid_sources[0x01]	17895	1		T8	799		T16	7		T20	694
valid_sources[0x02]	17667	1		T8	328		T9	4		T10	22
valid_sources[0x03]	18310	1		T3	1		T8	711		T15	4
valid_sources[0x04]	18471	1		T8	946		T17	3		T20	696
valid_sources[0x05]	16792	1		T7	2		T8	894		T15	1
valid_sources[0x06]	17070	1		T8	341		T15	3		T20	673
valid_sources[0x07]	17318	1		T8	1346		T15	1		T20	676
valid_sources[0x08]	18363	1		T8	691		T17	3		T35	1
valid_sources[0x09]	17591	1		T8	1118		T15	2		T20	660
valid_sources[0x0a]	17158	1		T8	630		T15	5		T17	2
valid_sources[0x0b]	17779	1		T8	432		T15	2		T17	1
valid_sources[0x0c]	18054	1		T8	678		T35	1		T20	679
valid_sources[0x0d]	17416	1		T3	1		T8	540		T17	2
valid_sources[0x0e]	18656	1		T5	4		T7	1		T8	772
valid_sources[0x0f]	16416	1		T8	448		T15	2		T17	1
valid_sources[0x10]	18237	1		T8	304		T15	6		T20	644
valid_sources[0x11]	16131	1		T8	514		T15	2		T17	1
valid_sources[0x12]	17094	1		T8	874		T15	6		T17	1
valid_sources[0x13]	17184	1		T1	1		T8	715		T15	1
valid_sources[0x14]	17830	1		T8	976		T12	22		T17	2
valid_sources[0x15]	17843	1		T8	722		T15	3		T17	1
valid_sources[0x16]	16204	1		T8	232		T15	1		T17	2
valid_sources[0x17]	18090	1		T8	508		T15	2		T20	774
valid_sources[0x18]	16825	1		T8	806		T15	2		T35	5
valid_sources[0x19]	18523	1		T5	1		T8	369		T16	4
valid_sources[0x1a]	16770	1		T8	740		T15	5		T17	2
valid_sources[0x1b]	18734	1		T8	947		T35	4		T20	660
valid_sources[0x1c]	17276	1		T3	1		T8	410		T15	3
valid_sources[0x1d]	18709	1		T3	1		T8	1040		T15	1
valid_sources[0x1e]	17516	1		T8	790		T15	2		T17	1
valid_sources[0x1f]	19350	1		T8	1522		T15	3		T16	43
valid_sources[0x20]	17614	1		T8	354		T11	1		T15	2
valid_sources[0x21]	17146	1		T8	693		T20	687		T21	8
valid_sources[0x22]	18999	1		T8	878		T17	4		T35	2
valid_sources[0x23]	17425	1		T8	743		T15	1		T17	1
valid_sources[0x24]	18035	1		T8	1064		T15	1		T20	768
valid_sources[0x25]	16890	1		T8	560		T16	19		T35	3
valid_sources[0x26]	16373	1		T3	1		T8	341		T15	4
valid_sources[0x27]	17879	1		T8	654		T15	3		T17	1
valid_sources[0x28]	17555	1		T8	900		T17	1		T35	2
valid_sources[0x29]	17257	1		T8	442		T11	1		T17	2
valid_sources[0x2a]	17041	1		T8	1121		T15	1		T17	3
valid_sources[0x2b]	16748	1		T8	310		T15	1		T17	2
valid_sources[0x2c]	17837	1		T6	7		T8	364		T15	2
valid_sources[0x2d]	18231	1		T8	362		T15	2		T17	3
valid_sources[0x2e]	17015	1		T8	563		T15	4		T17	2
valid_sources[0x2f]	15924	1		T8	939		T15	1		T17	1
valid_sources[0x30]	15843	1		T8	595		T15	9		T17	1
valid_sources[0x31]	17937	1		T5	1		T8	894		T15	2
valid_sources[0x32]	17673	1		T8	1002		T15	1		T20	720
valid_sources[0x33]	17863	1		T8	995		T16	14		T17	3
valid_sources[0x34]	16456	1		T8	524		T15	2		T17	2
valid_sources[0x35]	17157	1		T7	1		T8	384		T15	2
valid_sources[0x36]	17844	1		T8	953		T15	1		T17	1
valid_sources[0x37]	18245	1		T8	869		T17	1		T20	664
valid_sources[0x38]	17307	1		T8	896		T11	1		T16	4
valid_sources[0x39]	18318	1		T8	908		T15	2		T17	2
valid_sources[0x3a]	17196	1		T1	2		T8	392		T15	3
valid_sources[0x3b]	17776	1		T7	1		T8	1102		T15	2
valid_sources[0x3c]	17409	1		T8	360		T15	2		T35	1
valid_sources[0x3d]	17453	1		T8	423		T17	2		T20	656
valid_sources[0x3e]	17150	1		T8	505		T15	10		T17	1
valid_sources[0x3f]	17089	1		T3	1		T8	681		T15	2
valid_sources[0x40]	16066	1		T3	1		T8	538		T15	1
valid_sources[0x41]	16648	1		T8	616		T15	2		T17	1
valid_sources[0x42]	18065	1		T8	688		T35	1		T20	679
valid_sources[0x43]	17710	1		T3	1		T8	521		T15	2
valid_sources[0x44]	17432	1		T8	451		T20	681		T21	118
valid_sources[0x45]	15673	1		T8	813		T15	1		T35	1
valid_sources[0x46]	17670	1		T8	979		T20	702		T21	59
valid_sources[0x47]	16492	1		T8	347		T15	1		T17	3
valid_sources[0x48]	18442	1		T8	797		T15	1		T20	682
valid_sources[0x49]	17475	1		T8	759		T14	22		T15	3
valid_sources[0x4a]	18357	1		T8	1173		T17	2		T20	623
valid_sources[0x4b]	17697	1		T8	780		T17	2		T35	3
valid_sources[0x4c]	17324	1		T7	1		T8	754		T17	2
valid_sources[0x4d]	17947	1		T8	833		T15	2		T17	2
valid_sources[0x4e]	17159	1		T8	469		T15	2		T17	2
valid_sources[0x4f]	16547	1		T1	2		T8	835		T15	3
valid_sources[0x50]	18366	1		T8	1155		T11	1		T15	3
valid_sources[0x51]	17878	1		T8	1447		T17	1		T20	666
valid_sources[0x52]	17909	1		T8	579		T17	1		T35	3
valid_sources[0x53]	17223	1		T8	635		T15	1		T35	4
valid_sources[0x54]	17236	1		T8	606		T15	2		T35	2
valid_sources[0x55]	15048	1		T5	1		T8	263		T17	2
valid_sources[0x56]	16459	1		T8	626		T15	1		T17	1
valid_sources[0x57]	17670	1		T8	911		T17	3		T97	2
valid_sources[0x58]	19413	1		T5	1		T8	465		T17	1
valid_sources[0x59]	18271	1		T8	1231		T17	2		T35	4
valid_sources[0x5a]	16013	1		T8	261		T11	1		T17	1
valid_sources[0x5b]	17709	1		T8	931		T11	1		T15	4
valid_sources[0x5c]	18482	1		T8	1054		T15	2		T20	672
valid_sources[0x5d]	17104	1		T3	1		T8	443		T17	3
valid_sources[0x5e]	17293	1		T8	468		T15	2		T17	1
valid_sources[0x5f]	17026	1		T1	2		T5	1		T8	1090
valid_sources[0x60]	18776	1		T8	593		T15	1		T17	2
valid_sources[0x61]	17198	1		T8	600		T15	1		T17	1
valid_sources[0x62]	16445	1		T8	690		T16	8		T17	1
valid_sources[0x63]	16840	1		T8	784		T15	5		T17	3
valid_sources[0x64]	17815	1		T3	1		T8	981		T15	1
valid_sources[0x65]	15902	1		T5	1		T6	2		T8	218
valid_sources[0x66]	17094	1		T8	689		T17	3		T20	681
valid_sources[0x67]	16244	1		T3	2		T8	645		T15	1
valid_sources[0x68]	15847	1		T8	808		T17	3		T20	736
valid_sources[0x69]	18365	1		T1	1		T8	667		T11	2
valid_sources[0x6a]	18097	1		T8	837		T20	755		T21	100
valid_sources[0x6b]	17993	1		T8	749		T11	1		T15	5
valid_sources[0x6c]	16348	1		T8	847		T17	4		T20	665
valid_sources[0x6d]	16873	1		T8	643		T15	2		T17	4
valid_sources[0x6e]	16620	1		T8	322		T15	1		T17	1
valid_sources[0x6f]	17652	1		T8	757		T17	1		T20	641
valid_sources[0x70]	15715	1		T8	990		T15	3		T17	4
valid_sources[0x71]	17067	1		T3	2		T8	206		T15	1
valid_sources[0x72]	18006	1		T5	1		T8	708		T9	15
valid_sources[0x73]	19480	1		T8	799		T15	3		T17	2
valid_sources[0x74]	16809	1		T2	22		T8	915		T15	1
valid_sources[0x75]	17480	1		T8	754		T9	3		T17	3
valid_sources[0x76]	17069	1		T8	930		T17	6		T35	2
valid_sources[0x77]	17740	1		T8	422		T16	15		T20	650
valid_sources[0x78]	17041	1		T7	1		T8	567		T15	1
valid_sources[0x79]	16238	1		T8	358		T17	1		T20	679
valid_sources[0x7a]	16293	1		T1	1		T8	1008		T15	1
valid_sources[0x7b]	16961	1		T8	558		T11	1		T15	2
valid_sources[0x7c]	16054	1		T8	394		T15	3		T20	685
valid_sources[0x7d]	17496	1		T8	729		T16	9		T17	2
valid_sources[0x7e]	16786	1		T8	831		T15	1		T17	1
valid_sources[0x7f]	18146	1		T8	515		T15	3		T17	1
valid_sources[0x80]	17446	1		T8	527		T15	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1020934

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

1536254

1

T1

9

T2

6

T3

8

values[0x1]

all_enables

biggest_size

1536044

1

T1

9

T2

9

T3

6