Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	742579505	4884555	0	0
wdog_bark_thold_rd_A	742579505	114440	0	0
wdog_bite_thold_rd_A	742579505	98892	0	0
wdog_ctrl_rd_A	742579505	99304	0	0
wdog_regwen_rd_A	742579505	114152	0	0
wkup_ctrl_rd_A	742579505	99709	0	0
wkup_thold_hi_rd_A	742579505	113923	0	0
wkup_thold_lo_rd_A	742579505	99440	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	4884555	0	0
T8	547993	206717	0	0
T9	4305	0	0	0
T10	34370	0	0	0
T11	13138	0	0	0
T12	22849	0	0	0
T13	4053	0	0	0
T14	17475	0	0	0
T15	456658	0	0	0
T16	697508	0	0	0
T17	577749	0	0	0
T20	0	185172	0	0
T21	0	31068	0	0
T27	0	144838	0	0
T30	0	159895	0	0
T33	0	115609	0	0
T34	0	75191	0	0
T44	0	170001	0	0
T45	0	151968	0	0
T46	0	95153	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	114440	0	0
T44	760430	17546	0	0
T45	423161	0	0	0
T48	0	4630	0	0
T49	0	6917	0	0
T80	0	8039	0	0
T82	0	9139	0	0
T84	0	5478	0	0
T85	0	13996	0	0
T86	0	18463	0	0
T87	0	12839	0	0
T88	0	8623	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	98892	0	0
T44	760430	15645	0	0
T45	423161	0	0	0
T48	0	4272	0	0
T49	0	6072	0	0
T80	0	6564	0	0
T82	0	7601	0	0
T84	0	4506	0	0
T85	0	12463	0	0
T86	0	15938	0	0
T87	0	10767	0	0
T88	0	7676	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	99304	0	0
T44	760430	14989	0	0
T45	423161	0	0	0
T48	0	4033	0	0
T49	0	5925	0	0
T80	0	6765	0	0
T82	0	7936	0	0
T84	0	4454	0	0
T85	0	12762	0	0
T86	0	15582	0	0
T87	0	11486	0	0
T88	0	7853	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	114152	0	0
T44	760430	17938	0	0
T45	423161	0	0	0
T48	0	5006	0	0
T49	0	6819	0	0
T80	0	7813	0	0
T82	0	8730	0	0
T84	0	5158	0	0
T85	0	13942	0	0
T86	0	17715	0	0
T87	0	12940	0	0
T88	0	9163	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	99709	0	0
T44	760430	15776	0	0
T45	423161	0	0	0
T48	0	4145	0	0
T49	0	5885	0	0
T80	0	6699	0	0
T82	0	7517	0	0
T84	0	4758	0	0
T85	0	12226	0	0
T86	0	15730	0	0
T87	0	11087	0	0
T88	0	7979	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	113923	0	0
T44	760430	17380	0	0
T45	423161	0	0	0
T48	0	5066	0	0
T49	0	6771	0	0
T80	0	7771	0	0
T82	0	9437	0	0
T84	0	5229	0	0
T85	0	14522	0	0
T86	0	17758	0	0
T87	0	12778	0	0
T88	0	8565	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	742579505	99440	0	0
T44	760430	15264	0	0
T45	423161	0	0	0
T48	0	4091	0	0
T49	0	5635	0	0
T80	0	6886	0	0
T82	0	7764	0	0
T84	0	4518	0	0
T85	0	12616	0	0
T86	0	15934	0	0
T87	0	11502	0	0
T88	0	7749	0	0
T89	23942	0	0	0
T90	3556	0	0	0
T91	54881	0	0	0
T92	15276	0	0	0
T93	52650	0	0	0
T94	630724	0	0	0
T95	24914	0	0	0
T96	7118	0	0	0