Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	402316	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4896160	1		T1	86374		T2	11		T3	202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1302574	1		T1	22664		T2	1		T3	29
values[0x0]	1870994	1		T1	32740		T2	13		T3	128
values[0x1]	2124908	1		T1	37160		T2	6		T3	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	179361	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5119115	1		T1	89897		T2	12		T3	221

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19388	1		T1	286		T3	1		T10	1
valid_sources[0x01]	20431	1		T1	532		T3	1		T10	1
valid_sources[0x02]	20787	1		T1	449		T10	1		T13	113
valid_sources[0x03]	19321	1		T1	552		T10	1		T12	3
valid_sources[0x04]	22571	1		T1	628		T10	3		T13	125
valid_sources[0x05]	20614	1		T1	377		T2	1		T10	3
valid_sources[0x06]	21110	1		T1	267		T3	1		T6	1
valid_sources[0x07]	20178	1		T1	355		T2	1		T9	1
valid_sources[0x08]	20536	1		T1	561		T7	1		T12	2
valid_sources[0x09]	20393	1		T1	319		T3	2		T10	3
valid_sources[0x0a]	20621	1		T1	278		T3	4		T10	1
valid_sources[0x0b]	19950	1		T1	312		T3	2		T13	103
valid_sources[0x0c]	21414	1		T1	292		T8	1		T13	104
valid_sources[0x0d]	20055	1		T1	409		T10	3		T13	102
valid_sources[0x0e]	19913	1		T1	364		T3	12		T7	3
valid_sources[0x0f]	20640	1		T1	324		T10	2		T12	2
valid_sources[0x10]	20826	1		T1	355		T3	1		T10	1
valid_sources[0x11]	21386	1		T1	409		T3	2		T6	1
valid_sources[0x12]	22342	1		T1	364		T10	2		T12	1
valid_sources[0x13]	19927	1		T1	419		T3	1		T8	1
valid_sources[0x14]	21536	1		T1	478		T3	2		T10	1
valid_sources[0x15]	21044	1		T1	277		T10	1		T12	3
valid_sources[0x16]	20567	1		T1	255		T10	1		T12	2
valid_sources[0x17]	21458	1		T1	242		T10	2		T12	1
valid_sources[0x18]	20085	1		T1	371		T2	1		T3	1
valid_sources[0x19]	20530	1		T1	271		T3	2		T10	2
valid_sources[0x1a]	20189	1		T1	318		T3	8		T13	117
valid_sources[0x1b]	20937	1		T1	231		T2	1		T3	2
valid_sources[0x1c]	19664	1		T1	191		T3	2		T12	2
valid_sources[0x1d]	21825	1		T1	528		T2	1		T12	2
valid_sources[0x1e]	20712	1		T1	352		T12	2		T13	117
valid_sources[0x1f]	20933	1		T1	195		T10	2		T13	128
valid_sources[0x20]	20812	1		T1	418		T3	4		T10	5
valid_sources[0x21]	21032	1		T1	350		T3	1		T10	1
valid_sources[0x22]	19654	1		T1	269		T10	2		T12	2
valid_sources[0x23]	20284	1		T1	465		T3	1		T12	1
valid_sources[0x24]	20451	1		T1	381		T2	1		T13	110
valid_sources[0x25]	21309	1		T1	350		T10	4		T12	2
valid_sources[0x26]	20767	1		T1	295		T3	1		T10	1
valid_sources[0x27]	21015	1		T1	447		T12	2		T13	105
valid_sources[0x28]	19996	1		T1	265		T9	1		T10	2
valid_sources[0x29]	20405	1		T1	485		T10	2		T12	2
valid_sources[0x2a]	20412	1		T1	327		T13	98		T17	734
valid_sources[0x2b]	20971	1		T1	442		T3	1		T10	1
valid_sources[0x2c]	20119	1		T1	300		T2	1		T12	1
valid_sources[0x2d]	20365	1		T1	238		T9	1		T12	1
valid_sources[0x2e]	21344	1		T1	438		T8	1		T10	3
valid_sources[0x2f]	22283	1		T1	395		T12	2		T13	110
valid_sources[0x30]	20930	1		T1	394		T2	1		T12	1
valid_sources[0x31]	20400	1		T1	356		T3	2		T12	2
valid_sources[0x32]	20798	1		T1	404		T3	3		T12	1
valid_sources[0x33]	21039	1		T1	513		T2	1		T10	1
valid_sources[0x34]	20483	1		T1	386		T12	3		T13	103
valid_sources[0x35]	18974	1		T1	342		T3	1		T4	1
valid_sources[0x36]	19920	1		T1	219		T3	3		T6	1
valid_sources[0x37]	20926	1		T1	454		T3	2		T12	2
valid_sources[0x38]	20484	1		T1	263		T10	1		T12	1
valid_sources[0x39]	21336	1		T1	525		T3	4		T12	2
valid_sources[0x3a]	21482	1		T1	447		T13	101		T17	687
valid_sources[0x3b]	20787	1		T1	332		T8	1		T10	4
valid_sources[0x3c]	20242	1		T1	314		T3	1		T10	1
valid_sources[0x3d]	22119	1		T1	270		T9	1		T10	2
valid_sources[0x3e]	20029	1		T1	271		T3	1		T10	5
valid_sources[0x3f]	20581	1		T1	242		T6	1		T10	2
valid_sources[0x40]	19912	1		T1	359		T6	1		T12	1
valid_sources[0x41]	20928	1		T1	273		T10	3		T12	1
valid_sources[0x42]	20707	1		T1	265		T8	2		T9	1
valid_sources[0x43]	20090	1		T1	539		T3	3		T6	1
valid_sources[0x44]	20348	1		T1	565		T3	3		T10	1
valid_sources[0x45]	20284	1		T1	351		T3	5		T10	1
valid_sources[0x46]	20977	1		T1	451		T10	1		T13	101
valid_sources[0x47]	21860	1		T1	371		T8	2		T12	1
valid_sources[0x48]	20836	1		T1	332		T3	10		T12	2
valid_sources[0x49]	20706	1		T1	400		T3	3		T6	1
valid_sources[0x4a]	21637	1		T1	305		T10	1		T12	1
valid_sources[0x4b]	21406	1		T1	367		T9	1		T10	5
valid_sources[0x4c]	20667	1		T1	388		T3	1		T13	119
valid_sources[0x4d]	20036	1		T1	283		T3	3		T12	1
valid_sources[0x4e]	21767	1		T1	306		T9	1		T10	3
valid_sources[0x4f]	21533	1		T1	462		T12	1		T13	98
valid_sources[0x50]	20101	1		T1	206		T3	3		T13	105
valid_sources[0x51]	21693	1		T1	388		T3	7		T10	4
valid_sources[0x52]	19650	1		T1	240		T4	1		T12	3
valid_sources[0x53]	21237	1		T1	377		T10	3		T12	3
valid_sources[0x54]	20190	1		T1	350		T3	1		T10	1
valid_sources[0x55]	20962	1		T1	300		T12	1		T13	91
valid_sources[0x56]	21043	1		T1	514		T10	3		T12	1
valid_sources[0x57]	21746	1		T1	528		T10	1		T12	2
valid_sources[0x58]	21024	1		T1	440		T3	1		T10	3
valid_sources[0x59]	19606	1		T1	378		T10	1		T12	3
valid_sources[0x5a]	21154	1		T1	498		T10	4		T12	2
valid_sources[0x5b]	21538	1		T1	395		T3	1		T10	1
valid_sources[0x5c]	20430	1		T1	327		T3	3		T10	1
valid_sources[0x5d]	20275	1		T1	274		T3	1		T13	115
valid_sources[0x5e]	20172	1		T1	331		T3	3		T12	2
valid_sources[0x5f]	19931	1		T1	313		T3	4		T10	2
valid_sources[0x60]	21078	1		T1	318		T13	121		T17	704
valid_sources[0x61]	21657	1		T1	517		T10	1		T13	114
valid_sources[0x62]	20340	1		T1	442		T3	4		T12	2
valid_sources[0x63]	20180	1		T1	326		T10	3		T13	102
valid_sources[0x64]	20836	1		T1	420		T10	1		T13	122
valid_sources[0x65]	20456	1		T1	435		T3	8		T12	2
valid_sources[0x66]	20173	1		T1	439		T10	2		T12	3
valid_sources[0x67]	21425	1		T1	258		T2	1		T10	2
valid_sources[0x68]	19530	1		T1	337		T6	1		T9	1
valid_sources[0x69]	20739	1		T1	361		T3	1		T4	4
valid_sources[0x6a]	21660	1		T1	371		T10	3		T12	1
valid_sources[0x6b]	21279	1		T1	445		T3	1		T10	2
valid_sources[0x6c]	19199	1		T1	155		T10	1		T12	1
valid_sources[0x6d]	21057	1		T1	442		T10	2		T12	1
valid_sources[0x6e]	20508	1		T1	316		T3	5		T10	3
valid_sources[0x6f]	19855	1		T1	260		T12	3		T13	106
valid_sources[0x70]	20776	1		T1	421		T3	1		T4	2
valid_sources[0x71]	21306	1		T1	270		T3	1		T10	4
valid_sources[0x72]	20881	1		T1	408		T10	1		T12	2
valid_sources[0x73]	21257	1		T1	437		T3	2		T10	1
valid_sources[0x74]	20389	1		T1	262		T3	3		T10	3
valid_sources[0x75]	21011	1		T1	607		T10	6		T13	116
valid_sources[0x76]	21161	1		T1	428		T7	3		T10	1
valid_sources[0x77]	20150	1		T1	233		T3	3		T6	1
valid_sources[0x78]	20214	1		T1	345		T12	3		T13	92
valid_sources[0x79]	20676	1		T1	463		T3	2		T10	1
valid_sources[0x7a]	20627	1		T1	317		T8	1		T10	2
valid_sources[0x7b]	21184	1		T1	353		T10	2		T12	2
valid_sources[0x7c]	19934	1		T1	299		T2	1		T9	2
valid_sources[0x7d]	20575	1		T1	311		T10	2		T12	2
valid_sources[0x7e]	19924	1		T1	424		T10	1		T12	2
valid_sources[0x7f]	20787	1		T1	402		T3	1		T10	2
valid_sources[0x80]	21011	1		T1	365		T10	1		T12	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1221085

1

T1

21481

T3

13

T8

1

values[0x0]

all_enables

biggest_size

1837163

1

T1

32200

T2

9

T3

88

values[0x1]

all_enables

biggest_size

1837912

1

T1

32693

T2

2

T3

101