Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	759015915	5825909	0	0
wdog_bark_thold_rd_A	759015915	100365	0	0
wdog_bite_thold_rd_A	759015915	88346	0	0
wdog_ctrl_rd_A	759015915	88943	0	0
wdog_regwen_rd_A	759015915	101999	0	0
wkup_ctrl_rd_A	759015915	89225	0	0
wkup_thold_hi_rd_A	759015915	100072	0	0
wkup_thold_lo_rd_A	759015915	86640	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	5825909	0	0
T1	420036	91367	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T13	0	31466	0	0
T17	0	187826	0	0
T32	0	132051	0	0
T33	0	110868	0	0
T34	0	113171	0	0
T35	0	50061	0	0
T36	0	191133	0	0
T37	0	195754	0	0
T38	0	57012	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	100365	0	0
T1	420036	9558	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	9902	0	0
T47	0	9850	0	0
T85	0	3724	0	0
T89	0	6641	0	0
T90	0	3498	0	0
T91	0	4256	0	0
T92	0	8740	0	0
T93	0	8792	0	0
T94	0	9687	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	88346	0	0
T1	420036	8424	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	8345	0	0
T47	0	8365	0	0
T85	0	3433	0	0
T89	0	5678	0	0
T90	0	3067	0	0
T91	0	3473	0	0
T92	0	7730	0	0
T93	0	7850	0	0
T94	0	8545	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	88943	0	0
T1	420036	8603	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	8403	0	0
T47	0	8680	0	0
T85	0	3450	0	0
T89	0	5979	0	0
T90	0	3177	0	0
T91	0	3388	0	0
T92	0	7639	0	0
T93	0	7607	0	0
T94	0	8400	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	101999	0	0
T1	420036	10414	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	10030	0	0
T47	0	9851	0	0
T85	0	3892	0	0
T89	0	6847	0	0
T90	0	3590	0	0
T91	0	4056	0	0
T92	0	8975	0	0
T93	0	8394	0	0
T94	0	9749	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	89225	0	0
T1	420036	8374	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	8805	0	0
T47	0	8621	0	0
T85	0	3381	0	0
T89	0	5773	0	0
T90	0	3070	0	0
T91	0	3700	0	0
T92	0	7775	0	0
T93	0	7662	0	0
T94	0	8829	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	100072	0	0
T1	420036	9878	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	9621	0	0
T47	0	9839	0	0
T85	0	3857	0	0
T89	0	6484	0	0
T90	0	3480	0	0
T91	0	3924	0	0
T92	0	8875	0	0
T93	0	8794	0	0
T94	0	9442	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	759015915	86640	0	0
T1	420036	8592	0	0
T2	383017	0	0	0
T3	567614	0	0	0
T4	851748	0	0	0
T5	12113	0	0	0
T6	33740	0	0	0
T7	25409	0	0	0
T8	27598	0	0	0
T9	20720	0	0	0
T11	103639	0	0	0
T36	0	8120	0	0
T47	0	8513	0	0
T85	0	3463	0	0
T89	0	5501	0	0
T90	0	3034	0	0
T91	0	3634	0	0
T92	0	7736	0	0
T93	0	7726	0	0
T94	0	7788	0	0