Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	336277	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4124148	1		T1	13		T2	189		T3	119713

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1095458	1		T1	1		T2	47		T3	31468
values[0x0]	1576240	1		T1	9		T2	127		T3	45563
values[0x1]	1788727	1		T1	9		T2	127		T3	51703

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149511	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4310914	1		T1	14		T2	207		T3	124859

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17549	1		T3	491		T7	247		T10	529
valid_sources[0x01]	17485	1		T3	511		T7	104		T10	589
valid_sources[0x02]	18272	1		T2	2		T3	527		T6	1
valid_sources[0x03]	18374	1		T2	1		T3	495		T7	130
valid_sources[0x04]	18800	1		T2	1		T3	483		T6	1
valid_sources[0x05]	17127	1		T2	1		T3	510		T7	137
valid_sources[0x06]	17757	1		T2	1		T3	469		T6	1
valid_sources[0x07]	16917	1		T2	1		T3	512		T6	1
valid_sources[0x08]	16487	1		T3	552		T7	291		T10	609
valid_sources[0x09]	17361	1		T2	5		T3	467		T6	2
valid_sources[0x0a]	17814	1		T2	1		T3	510		T6	1
valid_sources[0x0b]	17160	1		T2	1		T3	483		T7	234
valid_sources[0x0c]	15885	1		T3	556		T7	184		T10	674
valid_sources[0x0d]	18692	1		T2	2		T3	484		T6	3
valid_sources[0x0e]	16589	1		T3	490		T4	1		T7	61
valid_sources[0x0f]	17410	1		T3	508		T6	1		T7	140
valid_sources[0x10]	17801	1		T2	1		T3	487		T6	1
valid_sources[0x11]	17151	1		T2	1		T3	496		T7	162
valid_sources[0x12]	17367	1		T2	3		T3	494		T7	374
valid_sources[0x13]	16495	1		T3	511		T7	250		T10	669
valid_sources[0x14]	17602	1		T2	1		T3	495		T7	81
valid_sources[0x15]	18551	1		T2	2		T3	499		T7	113
valid_sources[0x16]	15548	1		T2	3		T3	464		T6	1
valid_sources[0x17]	17646	1		T2	1		T3	513		T7	80
valid_sources[0x18]	17812	1		T2	1		T3	515		T6	3
valid_sources[0x19]	16205	1		T2	2		T3	469		T6	1
valid_sources[0x1a]	17395	1		T2	5		T3	516		T5	1
valid_sources[0x1b]	17705	1		T3	499		T6	2		T7	149
valid_sources[0x1c]	16356	1		T2	2		T3	494		T6	3
valid_sources[0x1d]	17091	1		T2	3		T3	525		T6	1
valid_sources[0x1e]	18495	1		T3	522		T6	3		T7	347
valid_sources[0x1f]	18301	1		T2	1		T3	512		T6	1
valid_sources[0x20]	17849	1		T2	1		T3	482		T6	2
valid_sources[0x21]	19230	1		T1	1		T2	1		T3	510
valid_sources[0x22]	16404	1		T2	3		T3	480		T7	205
valid_sources[0x23]	18010	1		T2	1		T3	511		T6	2
valid_sources[0x24]	17964	1		T2	2		T3	508		T6	1
valid_sources[0x25]	18917	1		T3	510		T7	140		T10	667
valid_sources[0x26]	17788	1		T2	2		T3	501		T7	80
valid_sources[0x27]	16221	1		T2	2		T3	539		T6	1
valid_sources[0x28]	17342	1		T3	504		T7	232		T10	714
valid_sources[0x29]	16546	1		T3	476		T6	1		T7	101
valid_sources[0x2a]	18509	1		T2	1		T3	542		T7	182
valid_sources[0x2b]	17744	1		T2	1		T3	474		T7	144
valid_sources[0x2c]	16168	1		T2	1		T3	467		T6	1
valid_sources[0x2d]	15845	1		T2	2		T3	513		T6	2
valid_sources[0x2e]	17301	1		T2	3		T3	500		T6	1
valid_sources[0x2f]	18399	1		T2	2		T3	553		T7	198
valid_sources[0x30]	16667	1		T3	547		T6	1		T7	516
valid_sources[0x31]	19039	1		T2	2		T3	477		T6	3
valid_sources[0x32]	19341	1		T2	1		T3	532		T6	2
valid_sources[0x33]	16693	1		T3	503		T6	1		T7	117
valid_sources[0x34]	16102	1		T2	1		T3	434		T7	129
valid_sources[0x35]	16377	1		T2	1		T3	479		T6	2
valid_sources[0x36]	16698	1		T2	1		T3	444		T6	2
valid_sources[0x37]	19073	1		T3	494		T5	8		T6	2
valid_sources[0x38]	18227	1		T2	1		T3	508		T7	402
valid_sources[0x39]	16217	1		T2	2		T3	524		T6	1
valid_sources[0x3a]	17659	1		T2	1		T3	530		T6	3
valid_sources[0x3b]	17949	1		T2	1		T3	510		T6	2
valid_sources[0x3c]	17137	1		T3	484		T6	1		T7	46
valid_sources[0x3d]	17911	1		T2	1		T3	513		T4	1
valid_sources[0x3e]	17873	1		T3	496		T4	1		T6	1
valid_sources[0x3f]	17270	1		T3	519		T6	1		T7	40
valid_sources[0x40]	16978	1		T2	1		T3	522		T7	224
valid_sources[0x41]	19012	1		T3	501		T6	1		T7	87
valid_sources[0x42]	18760	1		T3	530		T4	2		T6	2
valid_sources[0x43]	18599	1		T2	3		T3	551		T6	2
valid_sources[0x44]	16560	1		T3	517		T7	42		T10	639
valid_sources[0x45]	16373	1		T3	489		T7	236		T10	568
valid_sources[0x46]	17681	1		T2	1		T3	541		T4	2
valid_sources[0x47]	18707	1		T2	2		T3	552		T7	236
valid_sources[0x48]	17041	1		T2	2		T3	515		T6	1
valid_sources[0x49]	17036	1		T3	517		T6	1		T7	305
valid_sources[0x4a]	15693	1		T2	1		T3	498		T6	2
valid_sources[0x4b]	17287	1		T3	550		T5	1		T6	3
valid_sources[0x4c]	17362	1		T3	493		T6	2		T7	549
valid_sources[0x4d]	16209	1		T3	494		T6	1		T7	65
valid_sources[0x4e]	17847	1		T2	3		T3	504		T6	1
valid_sources[0x4f]	16790	1		T2	1		T3	510		T5	1
valid_sources[0x50]	17942	1		T2	2		T3	501		T6	2
valid_sources[0x51]	16782	1		T2	1		T3	481		T6	3
valid_sources[0x52]	18111	1		T3	515		T4	1		T7	73
valid_sources[0x53]	16767	1		T2	2		T3	503		T6	2
valid_sources[0x54]	16856	1		T3	488		T7	298		T10	530
valid_sources[0x55]	17953	1		T2	1		T3	479		T7	302
valid_sources[0x56]	18094	1		T3	513		T7	182		T10	516
valid_sources[0x57]	18147	1		T2	1		T3	523		T7	23
valid_sources[0x58]	17352	1		T3	509		T6	2		T7	450
valid_sources[0x59]	17274	1		T3	472		T6	1		T7	4
valid_sources[0x5a]	18634	1		T2	2		T3	519		T7	26
valid_sources[0x5b]	17780	1		T3	502		T4	3		T6	2
valid_sources[0x5c]	20207	1		T2	6		T3	480		T6	2
valid_sources[0x5d]	16659	1		T2	1		T3	491		T6	1
valid_sources[0x5e]	17497	1		T2	2		T3	504		T6	2
valid_sources[0x5f]	17788	1		T2	4		T3	520		T6	1
valid_sources[0x60]	17983	1		T2	1		T3	515		T6	2
valid_sources[0x61]	15463	1		T3	483		T6	3		T7	30
valid_sources[0x62]	17189	1		T2	2		T3	542		T7	135
valid_sources[0x63]	19209	1		T3	547		T6	2		T7	175
valid_sources[0x64]	17091	1		T2	2		T3	508		T6	1
valid_sources[0x65]	18113	1		T2	2		T3	489		T7	72
valid_sources[0x66]	18442	1		T2	5		T3	536		T7	23
valid_sources[0x67]	16620	1		T2	5		T3	473		T6	1
valid_sources[0x68]	17633	1		T2	1		T3	445		T6	2
valid_sources[0x69]	15929	1		T3	516		T7	106		T10	718
valid_sources[0x6a]	16592	1		T3	503		T6	3		T7	293
valid_sources[0x6b]	17120	1		T2	2		T3	537		T6	1
valid_sources[0x6c]	16902	1		T3	495		T6	2		T7	17
valid_sources[0x6d]	16846	1		T2	4		T3	466		T6	2
valid_sources[0x6e]	18261	1		T2	1		T3	493		T6	1
valid_sources[0x6f]	16686	1		T3	492		T6	1		T7	206
valid_sources[0x70]	18995	1		T3	519		T6	1		T7	274
valid_sources[0x71]	16864	1		T2	1		T3	480		T6	2
valid_sources[0x72]	16014	1		T2	2		T3	439		T4	1
valid_sources[0x73]	17142	1		T2	3		T3	516		T4	1
valid_sources[0x74]	17717	1		T2	2		T3	505		T7	245
valid_sources[0x75]	18067	1		T3	497		T6	3		T7	262
valid_sources[0x76]	17085	1		T2	1		T3	513		T6	1
valid_sources[0x77]	17486	1		T2	1		T3	495		T6	1
valid_sources[0x78]	17088	1		T2	1		T3	474		T5	1
valid_sources[0x79]	19169	1		T3	543		T6	1		T7	101
valid_sources[0x7a]	17461	1		T3	466		T6	1		T7	186
valid_sources[0x7b]	16877	1		T2	2		T3	517		T6	5
valid_sources[0x7c]	17361	1		T2	1		T3	497		T7	148
valid_sources[0x7d]	17279	1		T3	469		T6	2		T7	110
valid_sources[0x7e]	17156	1		T2	1		T3	490		T6	2
valid_sources[0x7f]	17484	1		T2	1		T3	510		T7	58
valid_sources[0x80]	16807	1		T2	1		T3	514		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027967

1

T2

23

T3

29775

T4

1

values[0x0]

all_enables

biggest_size

1547645

1

T1

7

T2

79

T3

44820

values[0x1]

all_enables

biggest_size

1548536

1

T1

6

T2

87

T3

45118