Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	618271910	4867842	0	0
wdog_bark_thold_rd_A	618271910	123035	0	0
wdog_bite_thold_rd_A	618271910	106922	0	0
wdog_ctrl_rd_A	618271910	105062	0	0
wdog_regwen_rd_A	618271910	121272	0	0
wkup_ctrl_rd_A	618271910	106148	0	0
wkup_thold_hi_rd_A	618271910	122531	0	0
wkup_thold_lo_rd_A	618271910	106950	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	4867842	0	0
T3	673033	134373	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	46689	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	175569	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T20	0	102645	0	0
T35	0	232081	0	0
T36	0	218258	0	0
T37	0	57809	0	0
T38	0	62052	0	0
T39	0	67318	0	0
T40	0	111389	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	123035	0	0
T3	673033	13781	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	5469	0	0
T39	0	7632	0	0
T49	0	4671	0	0
T73	0	2831	0	0
T74	0	5311	0	0
T75	0	13502	0	0
T76	0	6372	0	0
T77	0	21737	0	0
T78	0	5605	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	106922	0	0
T3	673033	11991	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	4851	0	0
T39	0	6505	0	0
T49	0	3979	0	0
T73	0	2373	0	0
T74	0	4588	0	0
T75	0	11834	0	0
T76	0	5234	0	0
T77	0	18865	0	0
T78	0	4911	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	105062	0	0
T3	673033	11757	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	5115	0	0
T39	0	6243	0	0
T49	0	3710	0	0
T73	0	2532	0	0
T74	0	4884	0	0
T75	0	11353	0	0
T76	0	5486	0	0
T77	0	18256	0	0
T78	0	4606	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	121272	0	0
T3	673033	13415	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	5534	0	0
T39	0	7281	0	0
T49	0	4396	0	0
T73	0	2815	0	0
T74	0	5296	0	0
T75	0	13454	0	0
T76	0	6148	0	0
T77	0	21824	0	0
T78	0	5412	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	106148	0	0
T3	673033	12026	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	5199	0	0
T39	0	6220	0	0
T49	0	3903	0	0
T73	0	2582	0	0
T74	0	4851	0	0
T75	0	11488	0	0
T76	0	5383	0	0
T77	0	18664	0	0
T78	0	4733	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	122531	0	0
T3	673033	13672	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	5544	0	0
T39	0	7710	0	0
T49	0	4591	0	0
T73	0	2815	0	0
T74	0	5543	0	0
T75	0	13100	0	0
T76	0	6403	0	0
T77	0	21999	0	0
T78	0	5557	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618271910	106950	0	0
T3	673033	11817	0	0
T4	34276	0	0	0
T5	615236	0	0	0
T6	120741	0	0	0
T7	193573	0	0	0
T8	42337	0	0	0
T9	27136	0	0	0
T10	504109	0	0	0
T11	14318	0	0	0
T12	575057	0	0	0
T37	0	4771	0	0
T39	0	6555	0	0
T49	0	3847	0	0
T73	0	2306	0	0
T74	0	4856	0	0
T75	0	11750	0	0
T76	0	5607	0	0
T77	0	19463	0	0
T78	0	4922	0	0