Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	324510	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	3913978	1		T1	14		T2	13		T3	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1043133	1		T1	1		T2	1		T3	1
values[0x0]	1498514	1		T1	11		T2	8		T3	12
values[0x1]	1696841	1		T1	8		T2	11		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145799	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4092689	1		T1	14		T2	13		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15289	1		T4	241		T5	2		T6	7
valid_sources[0x01]	16618	1		T4	791		T7	831		T10	1
valid_sources[0x02]	16415	1		T1	1		T4	339		T5	2
valid_sources[0x03]	16538	1		T4	244		T7	1521		T10	9
valid_sources[0x04]	15157	1		T4	313		T5	3		T7	480
valid_sources[0x05]	16547	1		T4	303		T5	3		T7	1736
valid_sources[0x06]	15430	1		T4	444		T7	649		T11	5
valid_sources[0x07]	16665	1		T4	275		T5	1		T7	1133
valid_sources[0x08]	15702	1		T4	328		T5	4		T7	1600
valid_sources[0x09]	17393	1		T4	871		T5	1		T7	1858
valid_sources[0x0a]	16585	1		T4	483		T5	1		T7	1274
valid_sources[0x0b]	17678	1		T4	528		T5	1		T6	12
valid_sources[0x0c]	15161	1		T4	672		T5	1		T6	3
valid_sources[0x0d]	16362	1		T4	292		T6	1		T7	1241
valid_sources[0x0e]	17324	1		T4	756		T7	1100		T12	201
valid_sources[0x0f]	15665	1		T4	86		T5	1		T7	846
valid_sources[0x10]	17450	1		T4	531		T5	2		T7	1055
valid_sources[0x11]	16322	1		T4	741		T5	1		T7	986
valid_sources[0x12]	16321	1		T4	464		T5	2		T7	1544
valid_sources[0x13]	18803	1		T4	428		T7	2753		T10	1
valid_sources[0x14]	17404	1		T4	1040		T5	4		T7	1293
valid_sources[0x15]	16667	1		T4	786		T7	1145		T10	3
valid_sources[0x16]	16686	1		T4	814		T7	1505		T12	166
valid_sources[0x17]	17224	1		T4	558		T7	1178		T8	1
valid_sources[0x18]	15376	1		T4	720		T5	1		T7	998
valid_sources[0x19]	15507	1		T4	199		T5	1		T7	898
valid_sources[0x1a]	16699	1		T4	223		T5	1		T7	1270
valid_sources[0x1b]	16118	1		T4	89		T5	2		T7	1013
valid_sources[0x1c]	16039	1		T4	325		T5	4		T7	723
valid_sources[0x1d]	17894	1		T4	335		T5	2		T6	1
valid_sources[0x1e]	15570	1		T4	751		T5	1		T7	515
valid_sources[0x1f]	16122	1		T4	756		T5	2		T7	698
valid_sources[0x20]	17013	1		T4	545		T6	7		T7	1162
valid_sources[0x21]	15758	1		T4	732		T5	2		T7	1227
valid_sources[0x22]	16402	1		T4	225		T5	1		T7	1717
valid_sources[0x23]	16603	1		T4	588		T5	3		T7	1349
valid_sources[0x24]	16809	1		T1	1		T4	816		T5	2
valid_sources[0x25]	15603	1		T4	371		T7	1443		T9	1
valid_sources[0x26]	15867	1		T4	439		T5	2		T7	1283
valid_sources[0x27]	16899	1		T4	1004		T5	1		T6	1
valid_sources[0x28]	17109	1		T4	605		T7	748		T10	3
valid_sources[0x29]	14750	1		T4	62		T7	392		T8	2
valid_sources[0x2a]	19111	1		T4	295		T5	1		T7	2457
valid_sources[0x2b]	16708	1		T4	607		T5	1		T6	5
valid_sources[0x2c]	17231	1		T4	545		T5	2		T7	965
valid_sources[0x2d]	16436	1		T4	391		T5	1		T7	975
valid_sources[0x2e]	16398	1		T4	170		T5	1		T7	357
valid_sources[0x2f]	16069	1		T2	20		T4	496		T5	1
valid_sources[0x30]	16711	1		T4	596		T5	4		T6	9
valid_sources[0x31]	17807	1		T4	754		T5	1		T7	2035
valid_sources[0x32]	16302	1		T4	523		T5	1		T7	1065
valid_sources[0x33]	16559	1		T4	287		T5	2		T7	1494
valid_sources[0x34]	16202	1		T4	293		T7	1207		T10	1
valid_sources[0x35]	14241	1		T4	349		T5	1		T7	610
valid_sources[0x36]	16765	1		T4	484		T5	1		T7	1014
valid_sources[0x37]	16067	1		T4	217		T5	1		T7	937
valid_sources[0x38]	16744	1		T4	465		T7	1242		T12	162
valid_sources[0x39]	17696	1		T4	699		T7	1373		T8	1
valid_sources[0x3a]	16866	1		T4	661		T5	1		T7	1657
valid_sources[0x3b]	16707	1		T4	412		T5	1		T7	1187
valid_sources[0x3c]	16223	1		T4	589		T5	4		T7	992
valid_sources[0x3d]	16394	1		T4	165		T5	2		T6	19
valid_sources[0x3e]	16592	1		T4	417		T5	2		T7	1211
valid_sources[0x3f]	15768	1		T4	132		T7	522		T11	2
valid_sources[0x40]	16322	1		T4	241		T5	2		T7	1492
valid_sources[0x41]	16446	1		T4	692		T5	1		T7	1441
valid_sources[0x42]	16276	1		T4	371		T5	1		T7	1506
valid_sources[0x43]	18366	1		T4	913		T5	2		T7	1219
valid_sources[0x44]	17312	1		T4	479		T7	2752		T12	146
valid_sources[0x45]	15839	1		T4	511		T5	1		T6	1
valid_sources[0x46]	15928	1		T4	728		T5	3		T7	1008
valid_sources[0x47]	15804	1		T4	891		T5	1		T7	838
valid_sources[0x48]	15392	1		T4	85		T5	1		T7	343
valid_sources[0x49]	18113	1		T4	783		T5	1		T7	1145
valid_sources[0x4a]	16438	1		T4	556		T5	1		T6	4
valid_sources[0x4b]	16558	1		T4	568		T5	1		T7	997
valid_sources[0x4c]	16694	1		T4	736		T5	1		T7	1522
valid_sources[0x4d]	15647	1		T4	394		T7	1149		T10	2
valid_sources[0x4e]	16887	1		T4	716		T5	1		T7	2346
valid_sources[0x4f]	15996	1		T4	1396		T7	197		T10	5
valid_sources[0x50]	17481	1		T4	60		T5	1		T7	1111
valid_sources[0x51]	16005	1		T4	279		T5	1		T7	668
valid_sources[0x52]	16105	1		T4	651		T7	1246		T12	187
valid_sources[0x53]	16533	1		T4	1063		T7	778		T9	6
valid_sources[0x54]	17350	1		T4	513		T5	1		T7	1123
valid_sources[0x55]	16730	1		T4	787		T5	1		T7	1433
valid_sources[0x56]	15878	1		T4	463		T5	3		T7	813
valid_sources[0x57]	16068	1		T4	469		T5	1		T7	1350
valid_sources[0x58]	16843	1		T4	544		T5	1		T7	1328
valid_sources[0x59]	15652	1		T4	247		T5	4		T7	1125
valid_sources[0x5a]	16788	1		T1	3		T4	531		T5	2
valid_sources[0x5b]	15991	1		T4	472		T5	2		T6	3
valid_sources[0x5c]	15897	1		T4	594		T7	1031		T9	13
valid_sources[0x5d]	18364	1		T4	367		T5	2		T7	2545
valid_sources[0x5e]	17065	1		T4	1081		T5	1		T7	1107
valid_sources[0x5f]	16657	1		T4	673		T5	1		T7	752
valid_sources[0x60]	15744	1		T4	605		T5	3		T7	958
valid_sources[0x61]	17904	1		T4	496		T7	1826		T11	2
valid_sources[0x62]	14829	1		T4	46		T7	723		T9	23
valid_sources[0x63]	16370	1		T4	1052		T7	1053		T12	169
valid_sources[0x64]	17112	1		T4	315		T5	1		T7	2014
valid_sources[0x65]	17348	1		T4	366		T7	2113		T11	2
valid_sources[0x66]	16526	1		T4	558		T7	1288		T10	2
valid_sources[0x67]	16629	1		T4	364		T5	2		T6	4
valid_sources[0x68]	15997	1		T4	359		T7	948		T11	1
valid_sources[0x69]	14986	1		T4	505		T5	1		T7	365
valid_sources[0x6a]	16495	1		T4	345		T5	2		T6	1
valid_sources[0x6b]	17335	1		T4	498		T5	1		T6	28
valid_sources[0x6c]	18244	1		T4	178		T5	1		T6	4
valid_sources[0x6d]	16056	1		T4	293		T5	1		T7	984
valid_sources[0x6e]	16770	1		T4	475		T6	46		T7	1713
valid_sources[0x6f]	15646	1		T4	397		T7	981		T10	1
valid_sources[0x70]	15634	1		T4	550		T7	594		T10	1
valid_sources[0x71]	17445	1		T4	58		T5	3		T7	2284
valid_sources[0x72]	18158	1		T4	554		T5	2		T7	906
valid_sources[0x73]	16494	1		T4	316		T5	1		T6	7
valid_sources[0x74]	16029	1		T4	684		T7	1358		T11	1
valid_sources[0x75]	15789	1		T4	409		T5	2		T7	1325
valid_sources[0x76]	16244	1		T4	431		T7	1091		T12	171
valid_sources[0x77]	16267	1		T4	520		T5	3		T6	7
valid_sources[0x78]	15974	1		T4	175		T5	1		T7	1298
valid_sources[0x79]	16361	1		T4	588		T5	1		T7	1212
valid_sources[0x7a]	17019	1		T4	342		T5	3		T7	1558
valid_sources[0x7b]	17786	1		T4	738		T5	3		T6	4
valid_sources[0x7c]	15864	1		T4	238		T5	2		T6	3
valid_sources[0x7d]	16312	1		T4	690		T7	1175		T12	216
valid_sources[0x7e]	15494	1		T4	328		T6	6		T7	1570
valid_sources[0x7f]	16592	1		T4	189		T7	1334		T11	11
valid_sources[0x80]	18489	1		T4	630		T7	1104		T12	169

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

976973

1

T1

1

T4

28183

T5

11

values[0x0]

all_enables

biggest_size

1470654

1

T1

9

T2

5

T3

8

values[0x1]

all_enables

biggest_size

1466351

1

T1

4

T2

8

T3

3