Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	621017169	4641144	0	0
wdog_bark_thold_rd_A	621017169	100630	0	0
wdog_bite_thold_rd_A	621017169	87639	0	0
wdog_ctrl_rd_A	621017169	87381	0	0
wdog_regwen_rd_A	621017169	100768	0	0
wkup_ctrl_rd_A	621017169	88793	0	0
wkup_thold_hi_rd_A	621017169	100685	0	0
wkup_thold_lo_rd_A	621017169	86145	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	4641144	0	0
T4	556965	128761	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	374547	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	49832	0	0
T30	12398	0	0	0
T38	0	138386	0	0
T39	0	115770	0	0
T40	0	19471	0	0
T41	0	222559	0	0
T42	0	84593	0	0
T43	0	212955	0	0
T44	0	48563	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	100630	0	0
T4	556965	13266	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1781	0	0
T54	0	6293	0	0
T78	0	7827	0	0
T82	0	9973	0	0
T83	0	10084	0	0
T84	0	1362	0	0
T85	0	4733	0	0
T86	0	4341	0	0
T87	0	12431	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	87639	0	0
T4	556965	11788	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1554	0	0
T54	0	5155	0	0
T78	0	6699	0	0
T82	0	8609	0	0
T83	0	8782	0	0
T84	0	1040	0	0
T85	0	3948	0	0
T86	0	3550	0	0
T87	0	11095	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	87381	0	0
T4	556965	11469	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1485	0	0
T54	0	4881	0	0
T78	0	7112	0	0
T82	0	9229	0	0
T83	0	8499	0	0
T84	0	1045	0	0
T85	0	3896	0	0
T86	0	3606	0	0
T87	0	11074	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	100768	0	0
T4	556965	12910	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1944	0	0
T54	0	6008	0	0
T78	0	7683	0	0
T82	0	9565	0	0
T83	0	10098	0	0
T84	0	1180	0	0
T85	0	4446	0	0
T86	0	4280	0	0
T87	0	12441	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	88793	0	0
T4	556965	11408	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1516	0	0
T54	0	5416	0	0
T78	0	6811	0	0
T82	0	8902	0	0
T83	0	9209	0	0
T84	0	1086	0	0
T85	0	4075	0	0
T86	0	3500	0	0
T87	0	11218	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	100685	0	0
T4	556965	13773	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1758	0	0
T54	0	5738	0	0
T78	0	8107	0	0
T82	0	9777	0	0
T83	0	10168	0	0
T84	0	1171	0	0
T85	0	4251	0	0
T86	0	3843	0	0
T87	0	12294	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	621017169	86145	0	0
T4	556965	11416	0	0
T5	231483	0	0	0
T6	491063	0	0	0
T7	159606	0	0	0
T8	506903	0	0	0
T9	330547	0	0	0
T10	521706	0	0	0
T11	234923	0	0	0
T12	142647	0	0	0
T30	12398	0	0	0
T40	0	1480	0	0
T54	0	5171	0	0
T78	0	6512	0	0
T82	0	8621	0	0
T83	0	8651	0	0
T84	0	998	0	0
T85	0	3590	0	0
T86	0	3377	0	0
T87	0	10989	0	0