Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_sync_sleep_mode.u_sync_1
tb.dut.u_sync_sleep_mode.u_sync_2
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1
tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1
tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1
tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1
tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1
tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2
tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.u_sync_1
tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.u_sync_2
tb.dut.u_aon_intr_flop
tb.dut.u_intr_sync.g_sync.u_sync.u_sync_1
tb.dut.u_intr_sync.g_sync.u_sync.u_sync_2



Module Instance : tb.dut.u_sync_sleep_mode.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_sleep_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_sync_sleep_mode.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_sleep_mode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_hi_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_thold_lo_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_hi_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_count_lo_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_ctrl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bark_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_bite_thold_cdc.u_arb.gen_passthru.u_dst_to_src_ack.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wdog_count_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_src_to_dst_req.prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.req_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.req_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_wkup_cause_cdc.u_arb.gen_wr_req.u_dst_update_sync.gen_nrz_hs_protocol.ack_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_nrz_hs_protocol.ack_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_flops.u_prim_flop_2sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_aon_intr_flop

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.56 96.15 66.67 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_intr_sync.g_sync.u_sync.u_sync_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_intr_sync.g_sync.u_sync.u_sync_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_sync.u_sync


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_generic.u_impl_generic 100.00 100.00 100.00

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%