Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	339558	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4182735	1		T1	13		T2	14		T3	53421

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1112949	1		T1	1		T2	1		T3	14177
values[0x0]	1600170	1		T1	9		T2	12		T3	20537
values[0x1]	1809174	1		T1	9		T2	6		T3	22829

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150907	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4371386	1		T1	13		T2	15		T3	55758

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18521	1		T3	211		T5	2		T9	2
valid_sources[0x01]	16562	1		T3	244		T5	2		T9	4
valid_sources[0x02]	15914	1		T3	233		T9	3		T11	551
valid_sources[0x03]	16959	1		T3	193		T5	2		T9	3
valid_sources[0x04]	17642	1		T3	209		T5	1		T11	610
valid_sources[0x05]	16276	1		T3	215		T5	2		T9	4
valid_sources[0x06]	18191	1		T1	3		T3	242		T5	2
valid_sources[0x07]	17002	1		T3	234		T5	1		T9	2
valid_sources[0x08]	17456	1		T3	207		T5	1		T11	374
valid_sources[0x09]	17532	1		T3	241		T5	1		T11	489
valid_sources[0x0a]	17475	1		T3	211		T5	2		T11	514
valid_sources[0x0b]	18039	1		T2	1		T3	222		T8	1
valid_sources[0x0c]	16904	1		T1	1		T3	252		T5	2
valid_sources[0x0d]	18844	1		T3	262		T9	1		T11	491
valid_sources[0x0e]	16424	1		T3	205		T11	500		T12	278
valid_sources[0x0f]	16570	1		T2	1		T3	219		T5	2
valid_sources[0x10]	18517	1		T3	218		T11	545		T12	280
valid_sources[0x11]	17718	1		T3	254		T9	4		T11	464
valid_sources[0x12]	17080	1		T3	238		T5	1		T6	1
valid_sources[0x13]	16032	1		T3	236		T5	1		T9	1
valid_sources[0x14]	17768	1		T3	211		T11	451		T12	287
valid_sources[0x15]	18658	1		T3	232		T5	1		T11	482
valid_sources[0x16]	18586	1		T3	228		T5	2		T8	1
valid_sources[0x17]	18758	1		T3	214		T5	2		T9	2
valid_sources[0x18]	18188	1		T3	192		T4	1		T5	2
valid_sources[0x19]	18098	1		T3	236		T5	1		T11	470
valid_sources[0x1a]	18330	1		T3	247		T5	1		T9	3
valid_sources[0x1b]	17035	1		T3	227		T5	4		T9	4
valid_sources[0x1c]	17488	1		T3	217		T5	1		T11	364
valid_sources[0x1d]	17875	1		T3	209		T9	2		T11	504
valid_sources[0x1e]	17195	1		T3	222		T5	1		T8	3
valid_sources[0x1f]	16617	1		T3	249		T5	3		T11	505
valid_sources[0x20]	16925	1		T3	219		T5	2		T6	1
valid_sources[0x21]	17108	1		T3	227		T5	3		T11	372
valid_sources[0x22]	18491	1		T3	233		T11	462		T12	256
valid_sources[0x23]	17791	1		T3	215		T9	1		T11	483
valid_sources[0x24]	18207	1		T3	182		T5	1		T11	417
valid_sources[0x25]	17396	1		T3	239		T5	1		T11	468
valid_sources[0x26]	18987	1		T2	1		T3	215		T5	2
valid_sources[0x27]	18782	1		T3	205		T4	6		T5	1
valid_sources[0x28]	18438	1		T3	233		T5	3		T9	1
valid_sources[0x29]	17620	1		T3	191		T5	1		T11	577
valid_sources[0x2a]	16778	1		T3	205		T9	2		T11	354
valid_sources[0x2b]	17516	1		T3	239		T5	3		T11	538
valid_sources[0x2c]	19189	1		T3	233		T5	1		T8	3
valid_sources[0x2d]	17215	1		T3	221		T5	3		T11	282
valid_sources[0x2e]	20400	1		T3	228		T5	1		T11	458
valid_sources[0x2f]	15803	1		T3	215		T11	432		T12	223
valid_sources[0x30]	17509	1		T2	1		T3	184		T5	1
valid_sources[0x31]	16912	1		T3	199		T5	1		T10	1
valid_sources[0x32]	17950	1		T3	203		T9	2		T11	341
valid_sources[0x33]	15358	1		T3	241		T5	2		T9	8
valid_sources[0x34]	16915	1		T3	211		T5	3		T11	577
valid_sources[0x35]	17341	1		T3	218		T5	2		T9	1
valid_sources[0x36]	17655	1		T3	213		T11	564		T12	257
valid_sources[0x37]	18285	1		T3	239		T5	1		T11	423
valid_sources[0x38]	16665	1		T3	230		T5	4		T9	3
valid_sources[0x39]	17752	1		T3	237		T5	4		T11	374
valid_sources[0x3a]	16385	1		T3	229		T5	2		T11	407
valid_sources[0x3b]	17159	1		T3	216		T11	427		T12	295
valid_sources[0x3c]	17572	1		T3	209		T5	2		T11	373
valid_sources[0x3d]	19623	1		T3	221		T11	559		T12	246
valid_sources[0x3e]	17984	1		T3	223		T11	466		T12	270
valid_sources[0x3f]	17231	1		T3	246		T5	1		T11	461
valid_sources[0x40]	19616	1		T3	209		T5	2		T9	1
valid_sources[0x41]	17837	1		T3	217		T9	2		T11	543
valid_sources[0x42]	17861	1		T3	269		T9	2		T11	474
valid_sources[0x43]	18962	1		T3	238		T5	2		T11	562
valid_sources[0x44]	17791	1		T3	220		T9	3		T11	513
valid_sources[0x45]	16901	1		T2	3		T3	240		T9	4
valid_sources[0x46]	17030	1		T3	238		T4	1		T5	1
valid_sources[0x47]	16752	1		T3	255		T5	2		T11	374
valid_sources[0x48]	20302	1		T2	2		T3	246		T5	3
valid_sources[0x49]	18218	1		T3	209		T4	2		T11	529
valid_sources[0x4a]	18736	1		T3	201		T5	3		T11	563
valid_sources[0x4b]	18867	1		T3	232		T5	1		T11	529
valid_sources[0x4c]	19079	1		T3	209		T9	1		T11	560
valid_sources[0x4d]	15335	1		T3	221		T5	3		T9	2
valid_sources[0x4e]	18383	1		T3	217		T5	3		T11	450
valid_sources[0x4f]	16285	1		T3	244		T11	489		T12	256
valid_sources[0x50]	17866	1		T3	240		T5	4		T11	391
valid_sources[0x51]	16534	1		T3	233		T9	3		T10	1
valid_sources[0x52]	17003	1		T3	248		T5	1		T11	369
valid_sources[0x53]	17258	1		T1	1		T3	222		T5	1
valid_sources[0x54]	17784	1		T3	219		T5	1		T9	1
valid_sources[0x55]	17952	1		T3	259		T11	415		T12	288
valid_sources[0x56]	17446	1		T3	236		T5	3		T11	540
valid_sources[0x57]	18105	1		T3	243		T5	1		T9	2
valid_sources[0x58]	16042	1		T3	252		T5	1		T11	432
valid_sources[0x59]	17908	1		T3	229		T6	1		T11	658
valid_sources[0x5a]	18354	1		T3	260		T5	1		T10	1
valid_sources[0x5b]	17537	1		T3	252		T11	512		T12	244
valid_sources[0x5c]	16396	1		T3	228		T5	1		T6	1
valid_sources[0x5d]	17988	1		T3	209		T9	1		T11	431
valid_sources[0x5e]	17729	1		T3	198		T5	4		T11	400
valid_sources[0x5f]	16473	1		T3	218		T5	1		T9	2
valid_sources[0x60]	16962	1		T3	212		T5	1		T9	2
valid_sources[0x61]	17517	1		T1	1		T3	234		T5	1
valid_sources[0x62]	19121	1		T1	1		T3	231		T9	1
valid_sources[0x63]	18317	1		T3	244		T5	2		T11	564
valid_sources[0x64]	17765	1		T3	222		T5	1		T9	1
valid_sources[0x65]	18903	1		T3	203		T8	1		T11	499
valid_sources[0x66]	18191	1		T2	1		T3	210		T5	3
valid_sources[0x67]	18351	1		T3	230		T5	1		T9	2
valid_sources[0x68]	19743	1		T3	226		T5	2		T11	468
valid_sources[0x69]	16645	1		T3	199		T5	1		T10	1
valid_sources[0x6a]	18354	1		T3	253		T5	2		T9	1
valid_sources[0x6b]	18584	1		T3	197		T11	564		T12	253
valid_sources[0x6c]	17669	1		T3	238		T11	352		T12	253
valid_sources[0x6d]	16075	1		T3	229		T5	1		T9	2
valid_sources[0x6e]	16651	1		T3	203		T5	2		T9	5
valid_sources[0x6f]	18612	1		T3	213		T5	4		T11	499
valid_sources[0x70]	16095	1		T3	220		T5	1		T9	4
valid_sources[0x71]	18663	1		T3	227		T5	1		T9	2
valid_sources[0x72]	17870	1		T3	190		T9	4		T11	728
valid_sources[0x73]	17028	1		T3	246		T9	14		T11	434
valid_sources[0x74]	18150	1		T3	211		T5	3		T11	473
valid_sources[0x75]	17961	1		T3	215		T5	1		T11	552
valid_sources[0x76]	17439	1		T3	212		T9	2		T11	522
valid_sources[0x77]	18557	1		T3	230		T5	4		T11	419
valid_sources[0x78]	17994	1		T3	238		T5	1		T9	1
valid_sources[0x79]	15840	1		T3	228		T5	2		T9	2
valid_sources[0x7a]	19319	1		T3	228		T5	1		T9	4
valid_sources[0x7b]	18161	1		T1	1		T3	272		T6	2
valid_sources[0x7c]	14958	1		T1	1		T3	215		T10	2
valid_sources[0x7d]	17623	1		T3	215		T9	2		T11	474
valid_sources[0x7e]	18685	1		T3	264		T5	1		T9	1
valid_sources[0x7f]	17697	1		T3	208		T5	1		T11	561
valid_sources[0x80]	17934	1		T3	230		T5	1		T11	552

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1044402

1

T1

1

T2

1

T3

13331

values[0x0]

all_enables

biggest_size

1571741

1

T1

6

T2

11

T3

20239

values[0x1]

all_enables

biggest_size

1566592

1

T1

6

T2

2

T3

19851