Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	649729378	4919396	0	0
wdog_bark_thold_rd_A	649729378	57767	0	0
wdog_bite_thold_rd_A	649729378	49777	0	0
wdog_ctrl_rd_A	649729378	51145	0	0
wdog_regwen_rd_A	649729378	58079	0	0
wkup_ctrl_rd_A	649729378	51298	0	0
wkup_thold_hi_rd_A	649729378	57450	0	0
wkup_thold_lo_rd_A	649729378	50379	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	4919396	0	0
T3	157688	63965	0	0
T4	10907	0	0	0
T5	672304	0	0	0
T6	14675	0	0	0
T7	581982	0	0	0
T8	201205	0	0	0
T9	420197	0	0	0
T10	20512	0	0	0
T11	504889	138178	0	0
T12	0	75311	0	0
T28	25150	0	0	0
T30	0	32008	0	0
T34	0	191193	0	0
T39	0	31805	0	0
T40	0	64066	0	0
T41	0	242616	0	0
T42	0	50955	0	0
T43	0	116408	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	57767	0	0
T39	141346	3156	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	6552	0	0
T103	0	3393	0	0
T104	0	5347	0	0
T105	0	9864	0	0
T106	0	11465	0	0
T107	0	3791	0	0
T108	0	10488	0	0
T109	0	2339	0	0
T110	0	30	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	49777	0	0
T39	141346	2677	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	5436	0	0
T103	0	2766	0	0
T104	0	4807	0	0
T105	0	8420	0	0
T106	0	10063	0	0
T107	0	3567	0	0
T108	0	8960	0	0
T109	0	1834	0	0
T110	0	37	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	51145	0	0
T39	141346	2677	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	6060	0	0
T103	0	3052	0	0
T104	0	4931	0	0
T105	0	8628	0	0
T106	0	9966	0	0
T107	0	3379	0	0
T108	0	9104	0	0
T109	0	1897	0	0
T110	0	43	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	58079	0	0
T39	141346	3143	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	6496	0	0
T103	0	3584	0	0
T104	0	5219	0	0
T105	0	9774	0	0
T106	0	11844	0	0
T107	0	3941	0	0
T108	0	10463	0	0
T109	0	2105	0	0
T110	0	45	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	51298	0	0
T39	141346	2678	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	5847	0	0
T103	0	3066	0	0
T104	0	4603	0	0
T105	0	8656	0	0
T106	0	10442	0	0
T107	0	3369	0	0
T108	0	9260	0	0
T109	0	1782	0	0
T110	0	49	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	57450	0	0
T39	141346	3101	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	6225	0	0
T103	0	3223	0	0
T104	0	5560	0	0
T105	0	10026	0	0
T106	0	11298	0	0
T107	0	4018	0	0
T108	0	10459	0	0
T109	0	2285	0	0
T110	0	60	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	649729378	50379	0	0
T39	141346	2527	0	0
T47	30653	0	0	0
T48	56102	0	0	0
T49	32369	0	0	0
T50	150008	0	0	0
T97	33279	0	0	0
T102	0	5574	0	0
T103	0	2960	0	0
T104	0	4653	0	0
T105	0	8867	0	0
T106	0	9552	0	0
T107	0	3708	0	0
T108	0	9361	0	0
T109	0	1810	0	0
T110	0	80	0	0
T111	12717	0	0	0
T112	10833	0	0	0
T113	576244	0	0	0
T114	25396	0	0	0