Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	372322	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4543225	1		T1	249		T2	15		T3	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1207995	1		T1	44		T2	1		T3	1
values[0x0]	1737325	1		T1	147		T2	13		T3	7
values[0x1]	1970227	1		T1	169		T2	8		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	166345	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4749202	1		T1	277		T2	15		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18831	1		T6	305		T12	242		T13	1
valid_sources[0x01]	18901	1		T6	314		T12	258		T13	2
valid_sources[0x02]	19018	1		T1	2		T6	301		T12	261
valid_sources[0x03]	19584	1		T6	251		T8	1		T12	286
valid_sources[0x04]	19468	1		T2	2		T5	2		T6	275
valid_sources[0x05]	18364	1		T6	295		T12	266		T13	1
valid_sources[0x06]	20477	1		T6	269		T12	273		T14	613
valid_sources[0x07]	20075	1		T6	272		T12	236		T14	673
valid_sources[0x08]	20116	1		T1	2		T6	292		T12	262
valid_sources[0x09]	18107	1		T6	257		T12	212		T13	1
valid_sources[0x0a]	21545	1		T5	2		T6	224		T12	257
valid_sources[0x0b]	19370	1		T6	274		T7	2		T9	1
valid_sources[0x0c]	19799	1		T1	3		T6	276		T12	274
valid_sources[0x0d]	19382	1		T6	250		T12	285		T13	1
valid_sources[0x0e]	19340	1		T1	4		T6	230		T12	264
valid_sources[0x0f]	17868	1		T6	251		T12	226		T14	614
valid_sources[0x10]	19242	1		T4	1		T6	222		T12	225
valid_sources[0x11]	17699	1		T3	19		T6	290		T12	265
valid_sources[0x12]	17893	1		T6	241		T12	280		T13	3
valid_sources[0x13]	18774	1		T4	1		T6	244		T9	1
valid_sources[0x14]	21770	1		T6	267		T10	3		T12	267
valid_sources[0x15]	19779	1		T6	274		T12	247		T13	4
valid_sources[0x16]	19761	1		T4	1		T6	302		T12	255
valid_sources[0x17]	19900	1		T4	1		T6	269		T12	227
valid_sources[0x18]	20263	1		T6	241		T12	234		T13	3
valid_sources[0x19]	20135	1		T1	1		T6	288		T12	272
valid_sources[0x1a]	17478	1		T6	276		T12	249		T13	1
valid_sources[0x1b]	18421	1		T6	260		T12	212		T13	1
valid_sources[0x1c]	18791	1		T1	8		T6	301		T12	219
valid_sources[0x1d]	17276	1		T6	239		T12	280		T14	695
valid_sources[0x1e]	18808	1		T6	252		T12	236		T14	655
valid_sources[0x1f]	17778	1		T2	1		T6	275		T12	252
valid_sources[0x20]	19625	1		T1	5		T6	283		T12	273
valid_sources[0x21]	21715	1		T6	299		T12	242		T13	2
valid_sources[0x22]	19506	1		T6	266		T12	276		T13	2
valid_sources[0x23]	19646	1		T6	260		T9	1		T12	289
valid_sources[0x24]	20738	1		T1	1		T6	280		T12	273
valid_sources[0x25]	17943	1		T1	8		T6	236		T12	246
valid_sources[0x26]	18142	1		T6	266		T12	279		T13	1
valid_sources[0x27]	21496	1		T6	356		T10	2		T12	271
valid_sources[0x28]	19202	1		T6	248		T10	2		T12	277
valid_sources[0x29]	19750	1		T6	256		T12	257		T13	1
valid_sources[0x2a]	22599	1		T1	2		T6	268		T8	2
valid_sources[0x2b]	19409	1		T6	274		T12	236		T13	3
valid_sources[0x2c]	19773	1		T4	1		T6	256		T12	287
valid_sources[0x2d]	20852	1		T6	287		T12	300		T14	627
valid_sources[0x2e]	18354	1		T6	285		T12	278		T13	1
valid_sources[0x2f]	18772	1		T6	271		T12	277		T13	2
valid_sources[0x30]	19305	1		T6	271		T12	246		T13	1
valid_sources[0x31]	19327	1		T1	2		T5	4		T6	309
valid_sources[0x32]	17972	1		T2	1		T6	288		T12	263
valid_sources[0x33]	19195	1		T6	299		T12	273		T13	1
valid_sources[0x34]	20061	1		T6	295		T12	227		T14	587
valid_sources[0x35]	18784	1		T1	2		T6	237		T12	302
valid_sources[0x36]	19143	1		T6	269		T12	279		T34	1
valid_sources[0x37]	19183	1		T6	243		T12	267		T13	1
valid_sources[0x38]	17583	1		T1	1		T6	263		T10	5
valid_sources[0x39]	18573	1		T6	268		T12	270		T14	637
valid_sources[0x3a]	17032	1		T1	1		T6	264		T12	280
valid_sources[0x3b]	19067	1		T6	301		T12	270		T13	2
valid_sources[0x3c]	19022	1		T6	271		T12	256		T34	1
valid_sources[0x3d]	17276	1		T1	9		T6	279		T12	232
valid_sources[0x3e]	20880	1		T1	15		T6	288		T9	2
valid_sources[0x3f]	17650	1		T6	302		T7	3		T9	1
valid_sources[0x40]	18075	1		T1	4		T4	1		T6	270
valid_sources[0x41]	18775	1		T1	3		T6	302		T12	211
valid_sources[0x42]	19522	1		T6	287		T12	241		T13	2
valid_sources[0x43]	19145	1		T6	271		T12	292		T13	1
valid_sources[0x44]	18404	1		T6	262		T12	259		T14	725
valid_sources[0x45]	19704	1		T6	265		T12	341		T13	2
valid_sources[0x46]	17678	1		T6	263		T12	261		T13	2
valid_sources[0x47]	19041	1		T6	231		T12	265		T14	578
valid_sources[0x48]	17414	1		T1	2		T6	271		T12	273
valid_sources[0x49]	20685	1		T6	284		T12	202		T14	696
valid_sources[0x4a]	19390	1		T1	3		T6	264		T12	282
valid_sources[0x4b]	18678	1		T6	286		T12	247		T13	3
valid_sources[0x4c]	19199	1		T6	270		T12	258		T13	3
valid_sources[0x4d]	19572	1		T1	5		T6	235		T12	249
valid_sources[0x4e]	18737	1		T1	7		T6	294		T12	253
valid_sources[0x4f]	19457	1		T6	238		T12	305		T14	634
valid_sources[0x50]	18673	1		T1	5		T6	290		T12	259
valid_sources[0x51]	19718	1		T1	2		T6	242		T12	284
valid_sources[0x52]	18267	1		T5	5		T6	261		T12	237
valid_sources[0x53]	20489	1		T1	2		T6	306		T12	221
valid_sources[0x54]	18315	1		T6	277		T12	304		T13	1
valid_sources[0x55]	18021	1		T6	264		T12	255		T13	1
valid_sources[0x56]	18531	1		T6	240		T12	269		T13	1
valid_sources[0x57]	19624	1		T6	274		T12	241		T13	1
valid_sources[0x58]	18975	1		T6	313		T12	230		T13	1
valid_sources[0x59]	19051	1		T1	1		T6	293		T12	240
valid_sources[0x5a]	18423	1		T1	2		T6	274		T12	311
valid_sources[0x5b]	18075	1		T1	6		T6	239		T12	262
valid_sources[0x5c]	19226	1		T6	285		T12	243		T13	3
valid_sources[0x5d]	20617	1		T1	1		T6	244		T12	327
valid_sources[0x5e]	21788	1		T6	258		T12	245		T13	1
valid_sources[0x5f]	18969	1		T4	1		T6	314		T8	4
valid_sources[0x60]	18466	1		T6	298		T12	261		T13	1
valid_sources[0x61]	18247	1		T1	13		T6	289		T12	349
valid_sources[0x62]	17441	1		T6	293		T12	285		T13	1
valid_sources[0x63]	18340	1		T6	250		T12	261		T14	589
valid_sources[0x64]	17509	1		T1	10		T6	274		T12	225
valid_sources[0x65]	18701	1		T6	273		T12	218		T13	1
valid_sources[0x66]	20069	1		T1	2		T6	282		T7	1
valid_sources[0x67]	18009	1		T6	298		T12	274		T13	1
valid_sources[0x68]	17585	1		T1	1		T6	266		T12	272
valid_sources[0x69]	20023	1		T1	1		T6	282		T12	240
valid_sources[0x6a]	17827	1		T6	290		T12	226		T13	2
valid_sources[0x6b]	18050	1		T1	3		T6	253		T12	250
valid_sources[0x6c]	18037	1		T6	240		T12	276		T13	1
valid_sources[0x6d]	20112	1		T1	5		T6	261		T12	286
valid_sources[0x6e]	19913	1		T1	2		T2	2		T6	265
valid_sources[0x6f]	17062	1		T6	334		T9	1		T12	261
valid_sources[0x70]	18201	1		T2	1		T6	243		T12	263
valid_sources[0x71]	18697	1		T6	251		T12	282		T14	690
valid_sources[0x72]	19429	1		T4	1		T6	283		T12	244
valid_sources[0x73]	20800	1		T1	6		T6	240		T12	246
valid_sources[0x74]	19350	1		T1	4		T6	210		T12	256
valid_sources[0x75]	18509	1		T1	1		T6	284		T12	230
valid_sources[0x76]	17872	1		T6	299		T12	288		T14	672
valid_sources[0x77]	19428	1		T1	3		T6	307		T9	1
valid_sources[0x78]	18902	1		T6	274		T12	237		T14	710
valid_sources[0x79]	19486	1		T6	317		T12	303		T14	607
valid_sources[0x7a]	20429	1		T6	282		T12	232		T14	579
valid_sources[0x7b]	20072	1		T6	254		T12	306		T13	1
valid_sources[0x7c]	20158	1		T6	226		T12	245		T13	1
valid_sources[0x7d]	18638	1		T1	4		T6	276		T9	1
valid_sources[0x7e]	20341	1		T1	6		T6	248		T7	3
valid_sources[0x7f]	19310	1		T1	2		T6	299		T12	256
valid_sources[0x80]	19701	1		T6	255		T9	3		T12	225

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1133009

1

T1

23

T2

1

T4

1

values[0x0]

all_enables

biggest_size

1706005

1

T1

108

T2

9

T3

5

values[0x1]

all_enables

biggest_size

1704211

1

T1

118

T2

5

T3

5