Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	801420215	5400386	0	0
wdog_bark_thold_rd_A	801420215	108377	0	0
wdog_bite_thold_rd_A	801420215	95191	0	0
wdog_ctrl_rd_A	801420215	96273	0	0
wdog_regwen_rd_A	801420215	107726	0	0
wkup_ctrl_rd_A	801420215	95002	0	0
wkup_thold_hi_rd_A	801420215	109307	0	0
wkup_thold_lo_rd_A	801420215	95230	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	5400386	0	0
T6	205209	76884	0	0
T7	10525	0	0	0
T8	216581	0	0	0
T9	12406	0	0	0
T10	9240	0	0	0
T11	162449	0	0	0
T12	299935	74737	0	0
T13	182596	0	0	0
T14	0	189523	0	0
T24	0	121660	0	0
T35	0	251483	0	0
T36	0	339907	0	0
T37	0	41706	0	0
T38	0	51921	0	0
T39	0	119927	0	0
T40	0	246951	0	0
T41	716522	0	0	0
T42	118200	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	108377	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	6234	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	12905	0	0
T87	0	12605	0	0
T90	0	8992	0	0
T91	0	10057	0	0
T92	0	524	0	0
T93	0	4902	0	0
T94	0	4295	0	0
T95	0	7888	0	0
T96	0	5777	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	95191	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5148	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	10685	0	0
T87	0	11686	0	0
T90	0	8178	0	0
T91	0	8677	0	0
T92	0	444	0	0
T93	0	4349	0	0
T94	0	4121	0	0
T95	0	6722	0	0
T96	0	5133	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	96273	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5426	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	11296	0	0
T87	0	11995	0	0
T90	0	8376	0	0
T91	0	8651	0	0
T92	0	464	0	0
T93	0	4003	0	0
T94	0	3765	0	0
T95	0	6644	0	0
T96	0	5251	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	107726	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5591	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	12913	0	0
T87	0	13224	0	0
T90	0	9189	0	0
T91	0	9489	0	0
T92	0	516	0	0
T93	0	4991	0	0
T94	0	4661	0	0
T95	0	7675	0	0
T96	0	5559	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	95002	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5220	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	11482	0	0
T87	0	11671	0	0
T90	0	7945	0	0
T91	0	8721	0	0
T92	0	401	0	0
T93	0	4048	0	0
T94	0	3961	0	0
T95	0	6732	0	0
T96	0	4992	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	109307	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5780	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	12959	0	0
T87	0	13596	0	0
T90	0	9346	0	0
T91	0	9861	0	0
T92	0	581	0	0
T93	0	4824	0	0
T94	0	4414	0	0
T95	0	7609	0	0
T96	0	5699	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	801420215	95230	0	0
T16	184121	0	0	0
T17	741579	0	0	0
T24	487702	5134	0	0
T25	657818	0	0	0
T26	403866	0	0	0
T38	179885	0	0	0
T40	0	11461	0	0
T87	0	12023	0	0
T90	0	7698	0	0
T91	0	8333	0	0
T92	0	487	0	0
T93	0	4404	0	0
T94	0	3946	0	0
T95	0	6752	0	0
T96	0	4758	0	0
T97	8332	0	0	0
T98	369567	0	0	0
T99	23394	0	0	0
T100	37148	0	0	0