Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357331	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4321811	1		T1	181		T2	188556		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1149534	1		T1	41		T2	49655		T3	1
values[0x0]	1654704	1		T1	114		T2	72295		T3	7
values[0x1]	1874904	1		T1	117		T2	82240		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	159872	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4519270	1		T1	196		T2	197550		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17618	1		T2	730		T4	548		T5	1
valid_sources[0x01]	17030	1		T2	776		T4	551		T5	7
valid_sources[0x02]	18186	1		T2	809		T4	577		T6	865
valid_sources[0x03]	18296	1		T1	1		T2	801		T4	524
valid_sources[0x04]	17148	1		T2	797		T4	555		T6	850
valid_sources[0x05]	20115	1		T1	3		T2	796		T4	561
valid_sources[0x06]	17998	1		T1	1		T2	828		T4	546
valid_sources[0x07]	18854	1		T1	1		T2	820		T4	545
valid_sources[0x08]	17913	1		T1	4		T2	776		T4	573
valid_sources[0x09]	19638	1		T1	4		T2	777		T4	531
valid_sources[0x0a]	17584	1		T2	799		T4	582		T6	772
valid_sources[0x0b]	19182	1		T2	800		T4	550		T5	1
valid_sources[0x0c]	17938	1		T2	795		T4	554		T5	5
valid_sources[0x0d]	17737	1		T2	793		T4	579		T6	851
valid_sources[0x0e]	17422	1		T1	3		T2	831		T4	550
valid_sources[0x0f]	17262	1		T1	1		T2	740		T4	529
valid_sources[0x10]	18592	1		T2	810		T4	521		T5	4
valid_sources[0x11]	17339	1		T1	4		T2	741		T4	498
valid_sources[0x12]	17461	1		T2	764		T4	577		T6	940
valid_sources[0x13]	18263	1		T2	809		T4	502		T6	756
valid_sources[0x14]	18030	1		T2	834		T4	512		T6	887
valid_sources[0x15]	19242	1		T2	809		T4	514		T5	5
valid_sources[0x16]	19585	1		T2	795		T4	518		T6	849
valid_sources[0x17]	19531	1		T2	783		T4	551		T6	757
valid_sources[0x18]	19796	1		T2	847		T4	563		T5	2
valid_sources[0x19]	17459	1		T1	6		T2	767		T4	563
valid_sources[0x1a]	18894	1		T2	767		T4	533		T6	991
valid_sources[0x1b]	18723	1		T2	836		T4	530		T6	776
valid_sources[0x1c]	20247	1		T1	2		T2	769		T4	534
valid_sources[0x1d]	17262	1		T2	798		T4	555		T5	1
valid_sources[0x1e]	17623	1		T2	809		T4	539		T6	731
valid_sources[0x1f]	17644	1		T2	752		T4	572		T6	849
valid_sources[0x20]	16709	1		T1	1		T2	828		T4	553
valid_sources[0x21]	17047	1		T2	758		T4	550		T6	889
valid_sources[0x22]	18705	1		T2	805		T4	520		T6	1024
valid_sources[0x23]	17133	1		T2	806		T4	513		T6	805
valid_sources[0x24]	19392	1		T2	825		T4	523		T6	916
valid_sources[0x25]	19018	1		T2	773		T4	547		T5	4
valid_sources[0x26]	19120	1		T2	754		T4	558		T5	4
valid_sources[0x27]	16192	1		T1	2		T2	800		T4	535
valid_sources[0x28]	16353	1		T1	1		T2	761		T4	602
valid_sources[0x29]	20045	1		T2	764		T4	553		T5	2
valid_sources[0x2a]	18603	1		T2	777		T4	545		T6	883
valid_sources[0x2b]	17606	1		T2	844		T4	547		T5	4
valid_sources[0x2c]	19091	1		T2	792		T4	494		T6	928
valid_sources[0x2d]	18221	1		T1	3		T2	825		T4	547
valid_sources[0x2e]	19451	1		T2	807		T4	579		T5	1
valid_sources[0x2f]	17041	1		T2	801		T4	573		T6	922
valid_sources[0x30]	18790	1		T2	813		T4	536		T5	1
valid_sources[0x31]	17496	1		T1	1		T2	799		T4	536
valid_sources[0x32]	18931	1		T1	3		T2	808		T4	535
valid_sources[0x33]	18226	1		T1	1		T2	790		T4	518
valid_sources[0x34]	18115	1		T2	822		T4	539		T5	2
valid_sources[0x35]	19148	1		T1	1		T2	772		T4	536
valid_sources[0x36]	18182	1		T1	2		T2	808		T4	543
valid_sources[0x37]	18147	1		T2	797		T4	532		T6	794
valid_sources[0x38]	18117	1		T2	783		T4	511		T6	826
valid_sources[0x39]	17294	1		T1	4		T2	795		T4	534
valid_sources[0x3a]	19100	1		T2	796		T4	528		T6	935
valid_sources[0x3b]	18123	1		T2	819		T4	552		T5	1
valid_sources[0x3c]	19553	1		T2	800		T4	541		T5	1
valid_sources[0x3d]	19167	1		T2	746		T4	573		T6	877
valid_sources[0x3e]	18267	1		T2	751		T4	596		T6	816
valid_sources[0x3f]	18074	1		T2	825		T4	555		T5	2
valid_sources[0x40]	19103	1		T2	821		T4	494		T6	782
valid_sources[0x41]	20628	1		T1	4		T2	805		T4	512
valid_sources[0x42]	18839	1		T2	780		T4	533		T6	1029
valid_sources[0x43]	18374	1		T2	814		T4	537		T6	842
valid_sources[0x44]	17127	1		T1	1		T2	801		T4	566
valid_sources[0x45]	19272	1		T2	805		T4	549		T5	2
valid_sources[0x46]	19508	1		T2	762		T4	554		T5	3
valid_sources[0x47]	18534	1		T1	4		T2	733		T4	560
valid_sources[0x48]	19884	1		T2	825		T4	554		T6	827
valid_sources[0x49]	17383	1		T1	2		T2	812		T4	537
valid_sources[0x4a]	18835	1		T1	8		T2	790		T4	525
valid_sources[0x4b]	18748	1		T1	6		T2	768		T4	560
valid_sources[0x4c]	18666	1		T2	795		T4	522		T5	8
valid_sources[0x4d]	17485	1		T2	788		T4	555		T5	2
valid_sources[0x4e]	18160	1		T2	816		T4	536		T6	924
valid_sources[0x4f]	18902	1		T2	740		T4	529		T6	789
valid_sources[0x50]	17520	1		T2	801		T4	542		T6	928
valid_sources[0x51]	17759	1		T1	6		T2	769		T4	526
valid_sources[0x52]	17504	1		T2	791		T4	545		T6	850
valid_sources[0x53]	19678	1		T2	805		T4	558		T6	966
valid_sources[0x54]	19478	1		T1	1		T2	744		T4	564
valid_sources[0x55]	19956	1		T2	794		T4	564		T6	891
valid_sources[0x56]	18353	1		T2	781		T4	549		T6	980
valid_sources[0x57]	19122	1		T2	774		T4	578		T6	850
valid_sources[0x58]	17262	1		T2	814		T4	565		T5	13
valid_sources[0x59]	19855	1		T2	739		T4	563		T5	1
valid_sources[0x5a]	18060	1		T1	4		T2	830		T4	581
valid_sources[0x5b]	17798	1		T2	825		T4	529		T6	831
valid_sources[0x5c]	17981	1		T2	860		T4	571		T6	890
valid_sources[0x5d]	18411	1		T2	803		T4	582		T5	3
valid_sources[0x5e]	18169	1		T2	855		T4	570		T5	1
valid_sources[0x5f]	16803	1		T2	749		T4	549		T6	852
valid_sources[0x60]	18662	1		T1	1		T2	824		T4	525
valid_sources[0x61]	18407	1		T2	759		T4	572		T6	865
valid_sources[0x62]	17883	1		T2	802		T4	543		T6	872
valid_sources[0x63]	18367	1		T2	772		T4	529		T5	5
valid_sources[0x64]	18656	1		T2	827		T4	531		T6	875
valid_sources[0x65]	18094	1		T1	7		T2	795		T4	522
valid_sources[0x66]	18222	1		T2	825		T4	547		T6	757
valid_sources[0x67]	20439	1		T2	830		T4	550		T6	834
valid_sources[0x68]	18317	1		T1	3		T2	812		T4	553
valid_sources[0x69]	17942	1		T1	2		T2	819		T4	549
valid_sources[0x6a]	16982	1		T1	3		T2	785		T4	571
valid_sources[0x6b]	19305	1		T1	6		T2	818		T4	523
valid_sources[0x6c]	17994	1		T2	776		T4	577		T6	797
valid_sources[0x6d]	18340	1		T2	831		T4	549		T6	852
valid_sources[0x6e]	17516	1		T2	834		T4	517		T5	1
valid_sources[0x6f]	18662	1		T2	862		T4	552		T5	3
valid_sources[0x70]	19238	1		T1	2		T2	781		T4	551
valid_sources[0x71]	18540	1		T1	3		T2	807		T4	540
valid_sources[0x72]	18089	1		T1	5		T2	803		T4	538
valid_sources[0x73]	18971	1		T2	739		T4	531		T5	1
valid_sources[0x74]	17577	1		T2	813		T4	539		T6	838
valid_sources[0x75]	17484	1		T1	4		T2	777		T4	580
valid_sources[0x76]	17334	1		T2	766		T4	541		T5	4
valid_sources[0x77]	18147	1		T2	792		T4	511		T6	983
valid_sources[0x78]	17843	1		T2	813		T4	563		T6	906
valid_sources[0x79]	19108	1		T2	769		T4	527		T6	951
valid_sources[0x7a]	18030	1		T2	790		T4	535		T6	1015
valid_sources[0x7b]	18285	1		T2	835		T3	19		T4	560
valid_sources[0x7c]	17850	1		T2	791		T4	551		T6	802
valid_sources[0x7d]	18621	1		T1	3		T2	817		T4	555
valid_sources[0x7e]	18609	1		T1	2		T2	847		T4	518
valid_sources[0x7f]	19032	1		T2	784		T4	553		T5	1
valid_sources[0x80]	18156	1		T2	827		T4	566		T6	868

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077155

1

T1

25

T2

46715

T3

1

values[0x0]

all_enables

biggest_size

1623896

1

T1

78

T2

71146

T3

5

values[0x1]

all_enables

biggest_size

1620760

1

T1

78

T2

70695

T3

6