Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.56	96.15	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	644521681	5151538	0	0
wdog_bark_thold_rd_A	644521681	61195	0	0
wdog_bite_thold_rd_A	644521681	53053	0	0
wdog_ctrl_rd_A	644521681	53042	0	0
wdog_regwen_rd_A	644521681	60852	0	0
wkup_ctrl_rd_A	644521681	53142	0	0
wkup_thold_hi_rd_A	644521681	62069	0	0
wkup_thold_lo_rd_A	644521681	53327	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	5151538	0	0
T2	840769	230608	0	0
T3	40307	0	0	0
T4	629898	168181	0	0
T5	754934	0	0	0
T6	670090	239855	0	0
T7	51745	0	0	0
T8	18141	0	0	0
T9	6600	0	0	0
T10	320759	0	0	0
T11	206123	0	0	0
T15	0	194763	0	0
T30	0	48490	0	0
T31	0	60045	0	0
T32	0	209721	0	0
T33	0	111046	0	0
T34	0	60047	0	0
T35	0	218293	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	61195	0	0
T24	0	12	0	0
T48	0	12962	0	0
T49	0	6375	0	0
T50	0	12138	0	0
T74	0	28	0	0
T81	734862	0	0	0
T85	507195	11325	0	0
T86	0	4980	0	0
T87	0	6891	0	0
T88	0	5610	0	0
T89	0	23	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	53053	0	0
T24	0	38	0	0
T29	0	72	0	0
T48	0	11633	0	0
T49	0	5870	0	0
T50	0	10562	0	0
T81	734862	0	0	0
T85	507195	9957	0	0
T86	0	4502	0	0
T87	0	5428	0	0
T88	0	4268	0	0
T89	0	12	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	53042	0	0
T24	0	93	0	0
T48	0	11138	0	0
T49	0	6080	0	0
T50	0	10424	0	0
T74	0	5	0	0
T81	734862	0	0	0
T85	507195	9422	0	0
T86	0	4569	0	0
T87	0	5992	0	0
T88	0	4508	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0
T98	0	4	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	60852	0	0
T24	0	90	0	0
T48	0	12981	0	0
T49	0	6515	0	0
T50	0	11833	0	0
T74	0	13	0	0
T81	734862	0	0	0
T85	507195	11300	0	0
T86	0	5118	0	0
T87	0	6805	0	0
T88	0	5274	0	0
T89	0	18	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	53142	0	0
T24	0	37	0	0
T48	0	11135	0	0
T49	0	5655	0	0
T50	0	10628	0	0
T74	0	12	0	0
T81	734862	0	0	0
T85	507195	9739	0	0
T86	0	4371	0	0
T87	0	6251	0	0
T88	0	4443	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0
T98	0	4	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	62069	0	0
T24	0	32	0	0
T48	0	12947	0	0
T49	0	6840	0	0
T50	0	12452	0	0
T74	0	7	0	0
T81	734862	0	0	0
T85	507195	11255	0	0
T86	0	5015	0	0
T87	0	7124	0	0
T88	0	5514	0	0
T89	0	23	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	644521681	53327	0	0
T24	0	70	0	0
T48	0	11345	0	0
T49	0	5666	0	0
T50	0	10508	0	0
T74	0	5	0	0
T81	734862	0	0	0
T85	507195	9596	0	0
T86	0	4528	0	0
T87	0	6146	0	0
T88	0	4662	0	0
T89	0	9	0	0
T90	51317	0	0	0
T91	466518	0	0	0
T92	778050	0	0	0
T93	45159	0	0	0
T94	22601	0	0	0
T95	204188	0	0	0
T96	39954	0	0	0
T97	291168	0	0	0