Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355158	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4354370	1		T1	187		T2	15		T3	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1159118	1		T1	47		T2	1		T3	1
values[0x0]	1663471	1		T1	126		T2	9		T3	7
values[0x1]	1886939	1		T1	119		T2	12		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158257	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4551271	1		T1	204		T2	16		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17991	1		T8	1		T16	311		T29	1
valid_sources[0x01]	20437	1		T5	12		T7	1		T10	2
valid_sources[0x02]	17617	1		T7	4		T16	1049		T17	224
valid_sources[0x03]	18386	1		T24	1		T26	1		T16	293
valid_sources[0x04]	17681	1		T7	2		T24	1		T16	502
valid_sources[0x05]	18341	1		T16	576		T17	196		T18	709
valid_sources[0x06]	19030	1		T16	804		T29	1		T17	191
valid_sources[0x07]	18446	1		T16	469		T150	3		T17	182
valid_sources[0x08]	17971	1		T16	704		T17	240		T18	711
valid_sources[0x09]	18303	1		T7	5		T8	1		T16	196
valid_sources[0x0a]	19269	1		T7	1		T11	1		T24	1
valid_sources[0x0b]	17895	1		T16	607		T17	190		T18	736
valid_sources[0x0c]	18492	1		T16	630		T17	210		T18	705
valid_sources[0x0d]	17633	1		T7	3		T10	1		T16	493
valid_sources[0x0e]	17460	1		T7	1		T16	46		T17	207
valid_sources[0x0f]	18322	1		T1	292		T5	10		T6	1
valid_sources[0x10]	18569	1		T7	2		T26	5		T16	1075
valid_sources[0x11]	19094	1		T7	1		T16	662		T47	1
valid_sources[0x12]	18153	1		T8	3		T9	2		T16	868
valid_sources[0x13]	17917	1		T7	1		T16	434		T17	167
valid_sources[0x14]	17953	1		T5	9		T16	523		T17	209
valid_sources[0x15]	17986	1		T5	13		T7	1		T16	964
valid_sources[0x16]	17966	1		T7	3		T16	1039		T28	1
valid_sources[0x17]	18233	1		T26	4		T16	453		T150	2
valid_sources[0x18]	17781	1		T16	766		T150	4		T17	194
valid_sources[0x19]	17437	1		T7	1		T9	4		T16	392
valid_sources[0x1a]	18128	1		T7	2		T16	77		T150	6
valid_sources[0x1b]	17830	1		T7	3		T16	434		T31	1
valid_sources[0x1c]	17488	1		T7	1		T16	344		T150	15
valid_sources[0x1d]	17732	1		T2	2		T16	803		T50	3
valid_sources[0x1e]	19225	1		T7	2		T16	562		T17	194
valid_sources[0x1f]	19157	1		T7	1		T16	774		T49	1
valid_sources[0x20]	16848	1		T5	6		T10	1		T14	1
valid_sources[0x21]	16794	1		T6	1		T7	5		T16	418
valid_sources[0x22]	17006	1		T7	2		T16	220		T38	20
valid_sources[0x23]	18447	1		T16	271		T31	1		T17	238
valid_sources[0x24]	17855	1		T7	1		T9	2		T26	5
valid_sources[0x25]	17107	1		T7	1		T16	701		T28	1
valid_sources[0x26]	18943	1		T7	1		T16	925		T17	195
valid_sources[0x27]	18463	1		T5	12		T16	650		T17	203
valid_sources[0x28]	18005	1		T6	1		T7	1		T8	1
valid_sources[0x29]	17670	1		T7	2		T16	646		T27	1
valid_sources[0x2a]	18106	1		T26	5		T16	458		T50	1
valid_sources[0x2b]	19974	1		T26	5		T16	866		T17	186
valid_sources[0x2c]	18333	1		T2	2		T24	1		T16	801
valid_sources[0x2d]	18297	1		T7	2		T16	730		T47	1
valid_sources[0x2e]	19123	1		T13	1		T24	2		T16	629
valid_sources[0x2f]	19686	1		T7	3		T16	1060		T150	4
valid_sources[0x30]	17859	1		T7	1		T16	302		T150	9
valid_sources[0x31]	16827	1		T16	408		T29	1		T17	200
valid_sources[0x32]	19126	1		T7	1		T16	750		T150	4
valid_sources[0x33]	17270	1		T7	1		T16	177		T17	204
valid_sources[0x34]	19150	1		T16	797		T144	1		T17	221
valid_sources[0x35]	17935	1		T7	1		T16	360		T48	1
valid_sources[0x36]	18992	1		T7	1		T26	1		T16	600
valid_sources[0x37]	18213	1		T7	1		T16	571		T150	13
valid_sources[0x38]	18800	1		T7	2		T16	834		T29	2
valid_sources[0x39]	17797	1		T7	1		T9	1		T16	546
valid_sources[0x3a]	18415	1		T7	2		T16	976		T17	189
valid_sources[0x3b]	18511	1		T16	106		T17	192		T18	703
valid_sources[0x3c]	18904	1		T13	1		T16	564		T28	1
valid_sources[0x3d]	18116	1		T7	1		T16	161		T150	12
valid_sources[0x3e]	18254	1		T7	1		T16	677		T17	201
valid_sources[0x3f]	17748	1		T5	3		T16	422		T144	1
valid_sources[0x40]	18228	1		T16	506		T31	3		T17	205
valid_sources[0x41]	20432	1		T7	1		T14	6		T16	478
valid_sources[0x42]	17986	1		T16	370		T47	1		T212	19
valid_sources[0x43]	18711	1		T7	1		T9	1		T16	895
valid_sources[0x44]	17884	1		T7	1		T16	921		T17	222
valid_sources[0x45]	17515	1		T6	1		T7	1		T8	1
valid_sources[0x46]	17657	1		T7	1		T16	816		T17	198
valid_sources[0x47]	18658	1		T16	700		T17	187		T18	683
valid_sources[0x48]	18080	1		T7	1		T24	1		T16	827
valid_sources[0x49]	17988	1		T7	2		T16	862		T17	200
valid_sources[0x4a]	18690	1		T26	9		T16	605		T17	218
valid_sources[0x4b]	17492	1		T16	416		T197	1		T17	217
valid_sources[0x4c]	19123	1		T3	20		T7	1		T16	605
valid_sources[0x4d]	19003	1		T7	1		T16	732		T17	225
valid_sources[0x4e]	18281	1		T5	4		T9	4		T14	10
valid_sources[0x4f]	19586	1		T10	1		T16	1018		T17	220
valid_sources[0x50]	19031	1		T7	1		T16	769		T31	1
valid_sources[0x51]	19305	1		T12	4		T16	981		T28	1
valid_sources[0x52]	18368	1		T7	1		T16	455		T17	238
valid_sources[0x53]	19246	1		T9	2		T16	348		T28	1
valid_sources[0x54]	18286	1		T7	1		T16	788		T17	189
valid_sources[0x55]	17916	1		T7	6		T16	649		T17	174
valid_sources[0x56]	18911	1		T11	1		T16	1189		T17	198
valid_sources[0x57]	17948	1		T7	1		T16	284		T50	2
valid_sources[0x58]	19755	1		T16	986		T29	1		T17	213
valid_sources[0x59]	18853	1		T16	776		T17	202		T18	685
valid_sources[0x5a]	18600	1		T24	1		T16	890		T144	1
valid_sources[0x5b]	17364	1		T6	1		T7	1		T26	8
valid_sources[0x5c]	18000	1		T7	1		T16	782		T47	3
valid_sources[0x5d]	18411	1		T7	3		T16	484		T49	1
valid_sources[0x5e]	18070	1		T7	2		T16	965		T29	1
valid_sources[0x5f]	18715	1		T16	1267		T17	219		T18	679
valid_sources[0x60]	18765	1		T16	623		T47	1		T197	2
valid_sources[0x61]	18059	1		T7	2		T26	27		T16	806
valid_sources[0x62]	17042	1		T5	11		T7	5		T11	1
valid_sources[0x63]	16963	1		T7	4		T16	450		T31	1
valid_sources[0x64]	17130	1		T2	3		T7	2		T16	262
valid_sources[0x65]	19164	1		T8	1		T16	320		T48	1
valid_sources[0x66]	17356	1		T26	3		T16	355		T17	226
valid_sources[0x67]	17593	1		T7	1		T11	1		T16	707
valid_sources[0x68]	18718	1		T7	4		T16	327		T17	194
valid_sources[0x69]	18627	1		T16	685		T144	1		T17	200
valid_sources[0x6a]	17055	1		T6	1		T7	2		T16	384
valid_sources[0x6b]	18844	1		T7	2		T16	319		T17	212
valid_sources[0x6c]	18461	1		T16	327		T17	202		T18	739
valid_sources[0x6d]	18585	1		T16	678		T47	1		T28	1
valid_sources[0x6e]	18046	1		T16	216		T17	210		T116	3
valid_sources[0x6f]	19030	1		T5	11		T7	1		T13	1
valid_sources[0x70]	18276	1		T16	676		T17	203		T116	6
valid_sources[0x71]	17766	1		T7	2		T11	1		T16	626
valid_sources[0x72]	18404	1		T7	2		T16	596		T29	1
valid_sources[0x73]	18149	1		T7	3		T13	3		T26	3
valid_sources[0x74]	17676	1		T7	1		T16	270		T47	1
valid_sources[0x75]	16878	1		T2	3		T7	3		T16	326
valid_sources[0x76]	18946	1		T7	3		T16	952		T29	1
valid_sources[0x77]	18464	1		T7	3		T16	698		T50	3
valid_sources[0x78]	18116	1		T6	1		T7	1		T16	364
valid_sources[0x79]	19076	1		T6	2		T24	1		T26	10
valid_sources[0x7a]	18979	1		T16	831		T47	1		T17	227
valid_sources[0x7b]	19584	1		T26	33		T16	282		T28	1
valid_sources[0x7c]	19286	1		T6	1		T7	5		T26	1
valid_sources[0x7d]	19212	1		T5	5		T7	1		T16	677
valid_sources[0x7e]	19064	1		T7	1		T16	606		T49	1
valid_sources[0x7f]	18082	1		T7	2		T24	3		T16	627
valid_sources[0x80]	16919	1		T7	2		T16	315		T49	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1087416

1

T1

24

T5

8

T6

1

values[0x0]

all_enables

biggest_size

1633444

1

T1

84

T2

5

T3

5

values[0x1]

all_enables

biggest_size

1633510

1

T1

79

T2

10

T3

6