Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	740083926	5137903	0	0
wdog_bark_thold_rd_A	740083926	97954	0	0
wdog_bite_thold_rd_A	740083926	85297	0	0
wdog_ctrl_rd_A	740083926	85675	0	0
wdog_regwen_rd_A	740083926	97672	0	0
wkup_ctrl_rd_A	740083926	84031	0	0
wkup_thold_hi_rd_A	740083926	97329	0	0
wkup_thold_lo_rd_A	740083926	84095	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	5137903	0	0
T16	475536	173321	0	0
T17	0	62561	0	0
T18	0	199599	0	0
T27	35498	0	0	0
T28	13422	0	0	0
T29	10903	0	0	0
T30	10226	0	0	0
T38	963500	0	0	0
T40	0	64256	0	0
T41	0	222729	0	0
T42	0	105063	0	0
T43	0	114462	0	0
T44	0	64297	0	0
T45	0	87174	0	0
T46	0	103667	0	0
T47	10117	0	0	0
T48	247956	0	0	0
T49	142403	0	0	0
T50	681966	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	97954	0	0
T40	289724	6698	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	11218	0	0
T44	182943	0	0	0
T96	0	10330	0	0
T100	0	6816	0	0
T101	0	3934	0	0
T102	0	6078	0	0
T103	0	3453	0	0
T104	0	3972	0	0
T105	0	17227	0	0
T106	0	2260	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	85297	0	0
T40	289724	5771	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	9728	0	0
T44	182943	0	0	0
T96	0	9719	0	0
T100	0	6160	0	0
T101	0	3146	0	0
T102	0	4853	0	0
T103	0	3016	0	0
T104	0	3688	0	0
T105	0	15071	0	0
T106	0	1737	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	85675	0	0
T40	289724	5747	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	10506	0	0
T44	182943	0	0	0
T96	0	9332	0	0
T100	0	5820	0	0
T101	0	3343	0	0
T102	0	5295	0	0
T103	0	3029	0	0
T104	0	3493	0	0
T105	0	14414	0	0
T106	0	1862	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	97672	0	0
T40	289724	6338	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	11356	0	0
T44	182943	0	0	0
T96	0	10452	0	0
T100	0	6669	0	0
T101	0	3899	0	0
T102	0	5984	0	0
T103	0	3375	0	0
T104	0	4041	0	0
T105	0	17119	0	0
T106	0	2019	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	84031	0	0
T40	289724	5704	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	9772	0	0
T44	182943	0	0	0
T96	0	9250	0	0
T100	0	5627	0	0
T101	0	3263	0	0
T102	0	5143	0	0
T103	0	2883	0	0
T104	0	3472	0	0
T105	0	14483	0	0
T106	0	1836	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	97329	0	0
T40	289724	6669	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	11080	0	0
T44	182943	0	0	0
T96	0	10267	0	0
T100	0	7036	0	0
T101	0	3765	0	0
T102	0	5823	0	0
T103	0	3409	0	0
T104	0	4020	0	0
T105	0	17157	0	0
T106	0	2131	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	740083926	84095	0	0
T40	289724	5271	0	0
T41	846657	0	0	0
T42	294331	0	0	0
T43	502745	9831	0	0
T44	182943	0	0	0
T96	0	9403	0	0
T100	0	5851	0	0
T101	0	3351	0	0
T102	0	5224	0	0
T103	0	3077	0	0
T104	0	3733	0	0
T105	0	14796	0	0
T106	0	1760	0	0
T107	716018	0	0	0
T108	9675	0	0	0
T109	144286	0	0	0
T110	15002	0	0	0
T111	268621	0	0	0