Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	707320525	5217650	0	0
wdog_bark_thold_rd_A	707320525	118219	0	0
wdog_bite_thold_rd_A	707320525	103894	0	0
wdog_ctrl_rd_A	707320525	103440	0	0
wdog_regwen_rd_A	707320525	119295	0	0
wkup_ctrl_rd_A	707320525	105561	0	0
wkup_thold_hi_rd_A	707320525	118696	0	0
wkup_thold_lo_rd_A	707320525	105024	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	5217650	0	0
T6	222520	70102	0	0
T7	116384	395540	0	0
T8	211891	56412	0	0
T9	50961	0	0	0
T10	706082	0	0	0
T11	209722	0	0	0
T12	35050	0	0	0
T39	0	237685	0	0
T40	0	183430	0	0
T41	0	219738	0	0
T42	0	130610	0	0
T43	0	257983	0	0
T44	0	129102	0	0
T45	0	224856	0	0
T46	57971	0	0	0
T47	594012	0	0	0
T48	45186	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	118219	0	0
T40	775260	9417	0	0
T41	988424	21342	0	0
T44	0	12446	0	0
T68	0	2655	0	0
T87	0	6719	0	0
T89	0	12645	0	0
T90	0	13677	0	0
T91	0	8670	0	0
T92	0	13215	0	0
T93	0	5870	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	103894	0	0
T40	775260	8312	0	0
T41	988424	19376	0	0
T44	0	10966	0	0
T68	0	2161	0	0
T87	0	5953	0	0
T89	0	10848	0	0
T90	0	11795	0	0
T91	0	7802	0	0
T92	0	11378	0	0
T93	0	5162	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	103440	0	0
T40	775260	8501	0	0
T41	988424	18862	0	0
T44	0	10480	0	0
T68	0	2303	0	0
T87	0	5667	0	0
T89	0	10954	0	0
T90	0	12095	0	0
T91	0	7370	0	0
T92	0	11648	0	0
T93	0	5161	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	119295	0	0
T40	775260	9617	0	0
T41	988424	21908	0	0
T44	0	12749	0	0
T68	0	2423	0	0
T87	0	6774	0	0
T89	0	12344	0	0
T90	0	13773	0	0
T91	0	8320	0	0
T92	0	12757	0	0
T93	0	6625	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	105561	0	0
T40	775260	8020	0	0
T41	988424	19345	0	0
T44	0	10920	0	0
T68	0	2113	0	0
T87	0	6015	0	0
T89	0	11193	0	0
T90	0	12654	0	0
T91	0	7774	0	0
T92	0	11284	0	0
T93	0	5307	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	118696	0	0
T40	775260	9681	0	0
T41	988424	21667	0	0
T44	0	12384	0	0
T68	0	2414	0	0
T87	0	6837	0	0
T89	0	12226	0	0
T90	0	13697	0	0
T91	0	8858	0	0
T92	0	13252	0	0
T93	0	6254	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	707320525	105024	0	0
T40	775260	8510	0	0
T41	988424	19491	0	0
T44	0	10598	0	0
T68	0	2207	0	0
T87	0	6008	0	0
T89	0	10776	0	0
T90	0	12421	0	0
T91	0	7554	0	0
T92	0	11693	0	0
T93	0	5432	0	0
T94	10879	0	0	0
T95	229051	0	0	0
T96	14937	0	0	0
T97	923171	0	0	0
T98	764468	0	0	0
T99	20888	0	0	0
T100	56952	0	0	0
T101	142051	0	0	0