Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	351111	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4319427	1		T1	17		T2	12		T3	316225

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1146806	1		T1	1		T2	1		T3	83350
values[0x0]	1651033	1		T1	10		T2	6		T3	120265
values[0x1]	1872699	1		T1	11		T2	12		T3	136824

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156532	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4514006	1		T1	17		T2	12		T3	330067

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19402	1		T3	1299		T5	217		T7	447
valid_sources[0x01]	16913	1		T3	1427		T5	77		T7	461
valid_sources[0x02]	17988	1		T3	1321		T5	110		T7	407
valid_sources[0x03]	17910	1		T3	1351		T5	78		T7	460
valid_sources[0x04]	19309	1		T3	1362		T5	106		T7	463
valid_sources[0x05]	18402	1		T3	1314		T5	194		T7	437
valid_sources[0x06]	18799	1		T3	1297		T5	102		T7	475
valid_sources[0x07]	18010	1		T2	1		T3	1338		T5	84
valid_sources[0x08]	17795	1		T3	1299		T5	237		T7	429
valid_sources[0x09]	18716	1		T3	1348		T5	323		T7	473
valid_sources[0x0a]	18078	1		T3	1338		T5	107		T7	448
valid_sources[0x0b]	17808	1		T2	1		T3	1295		T5	114
valid_sources[0x0c]	17684	1		T3	1338		T5	77		T7	456
valid_sources[0x0d]	18318	1		T3	1253		T5	105		T7	459
valid_sources[0x0e]	19266	1		T3	1288		T5	80		T7	449
valid_sources[0x0f]	18113	1		T3	1328		T5	88		T7	444
valid_sources[0x10]	18075	1		T3	1329		T5	118		T7	400
valid_sources[0x11]	17542	1		T3	1259		T5	121		T7	464
valid_sources[0x12]	18838	1		T3	1376		T5	68		T7	454
valid_sources[0x13]	18769	1		T3	1347		T5	91		T7	459
valid_sources[0x14]	18205	1		T3	1341		T5	54		T7	468
valid_sources[0x15]	17426	1		T3	1243		T5	87		T7	485
valid_sources[0x16]	18701	1		T3	1310		T5	166		T7	466
valid_sources[0x17]	18103	1		T3	1394		T5	132		T7	479
valid_sources[0x18]	18782	1		T3	1291		T5	122		T7	459
valid_sources[0x19]	17723	1		T3	1287		T5	109		T7	430
valid_sources[0x1a]	19120	1		T3	1277		T5	70		T7	490
valid_sources[0x1b]	17835	1		T1	7		T3	1314		T5	134
valid_sources[0x1c]	17671	1		T3	1378		T5	101		T7	438
valid_sources[0x1d]	17681	1		T3	1282		T5	100		T7	428
valid_sources[0x1e]	18353	1		T3	1332		T5	193		T7	489
valid_sources[0x1f]	18652	1		T3	1329		T5	66		T7	427
valid_sources[0x20]	18284	1		T3	1346		T5	122		T7	463
valid_sources[0x21]	17943	1		T3	1370		T5	80		T7	440
valid_sources[0x22]	17299	1		T3	1375		T5	119		T7	462
valid_sources[0x23]	19111	1		T2	1		T3	1339		T5	110
valid_sources[0x24]	18522	1		T3	1303		T5	95		T7	456
valid_sources[0x25]	17898	1		T3	1351		T5	109		T7	453
valid_sources[0x26]	18037	1		T3	1297		T5	90		T7	467
valid_sources[0x27]	17283	1		T3	1275		T5	87		T7	446
valid_sources[0x28]	17802	1		T3	1313		T4	1		T5	109
valid_sources[0x29]	18283	1		T3	1363		T5	190		T7	468
valid_sources[0x2a]	17564	1		T3	1335		T5	134		T7	463
valid_sources[0x2b]	18152	1		T3	1378		T5	47		T7	464
valid_sources[0x2c]	18225	1		T3	1373		T5	151		T7	449
valid_sources[0x2d]	17501	1		T3	1387		T5	127		T7	461
valid_sources[0x2e]	18722	1		T3	1278		T5	95		T7	485
valid_sources[0x2f]	18203	1		T3	1332		T5	155		T7	471
valid_sources[0x30]	18196	1		T3	1344		T5	162		T7	456
valid_sources[0x31]	17312	1		T3	1328		T4	1		T5	88
valid_sources[0x32]	17876	1		T3	1319		T5	182		T7	455
valid_sources[0x33]	17756	1		T3	1298		T5	86		T7	435
valid_sources[0x34]	17695	1		T3	1295		T5	111		T7	491
valid_sources[0x35]	18749	1		T3	1336		T5	95		T7	444
valid_sources[0x36]	18046	1		T3	1236		T5	97		T7	430
valid_sources[0x37]	18633	1		T3	1306		T5	124		T7	478
valid_sources[0x38]	19322	1		T3	1332		T5	107		T7	436
valid_sources[0x39]	18478	1		T3	1289		T5	147		T7	459
valid_sources[0x3a]	18552	1		T3	1306		T5	79		T7	455
valid_sources[0x3b]	17673	1		T3	1349		T5	101		T7	446
valid_sources[0x3c]	18292	1		T3	1329		T4	1		T5	87
valid_sources[0x3d]	18117	1		T3	1280		T5	98		T7	464
valid_sources[0x3e]	18002	1		T3	1342		T5	129		T7	471
valid_sources[0x3f]	17621	1		T3	1272		T5	178		T7	440
valid_sources[0x40]	18189	1		T3	1297		T5	124		T7	425
valid_sources[0x41]	18592	1		T3	1280		T5	71		T7	428
valid_sources[0x42]	17829	1		T3	1338		T5	93		T7	463
valid_sources[0x43]	17509	1		T3	1348		T5	96		T7	478
valid_sources[0x44]	19540	1		T3	1318		T5	107		T7	486
valid_sources[0x45]	17894	1		T3	1350		T5	104		T7	429
valid_sources[0x46]	18090	1		T3	1303		T5	87		T7	444
valid_sources[0x47]	19125	1		T3	1350		T5	99		T7	444
valid_sources[0x48]	17713	1		T3	1321		T5	74		T7	450
valid_sources[0x49]	18220	1		T3	1358		T5	184		T7	457
valid_sources[0x4a]	18389	1		T3	1355		T5	66		T7	476
valid_sources[0x4b]	18546	1		T3	1309		T5	88		T7	446
valid_sources[0x4c]	18632	1		T3	1360		T5	117		T7	467
valid_sources[0x4d]	18434	1		T3	1401		T5	119		T7	423
valid_sources[0x4e]	18309	1		T3	1367		T5	70		T7	472
valid_sources[0x4f]	18424	1		T3	1302		T5	159		T7	439
valid_sources[0x50]	18124	1		T3	1273		T5	185		T7	438
valid_sources[0x51]	18877	1		T3	1311		T5	77		T7	460
valid_sources[0x52]	17160	1		T3	1330		T5	111		T7	448
valid_sources[0x53]	19290	1		T3	1325		T5	119		T7	469
valid_sources[0x54]	17658	1		T3	1323		T5	133		T7	440
valid_sources[0x55]	18877	1		T3	1323		T5	78		T7	463
valid_sources[0x56]	18103	1		T3	1358		T5	61		T7	454
valid_sources[0x57]	18465	1		T3	1267		T5	181		T7	458
valid_sources[0x58]	18435	1		T3	1373		T4	2		T5	118
valid_sources[0x59]	18612	1		T3	1363		T5	121		T7	449
valid_sources[0x5a]	18962	1		T3	1287		T5	90		T7	458
valid_sources[0x5b]	18338	1		T3	1349		T5	103		T7	427
valid_sources[0x5c]	17956	1		T3	1298		T5	76		T7	459
valid_sources[0x5d]	18387	1		T3	1348		T5	83		T7	442
valid_sources[0x5e]	16995	1		T3	1253		T5	88		T7	452
valid_sources[0x5f]	18461	1		T3	1348		T4	2		T5	70
valid_sources[0x60]	18328	1		T3	1380		T5	120		T7	449
valid_sources[0x61]	18202	1		T3	1299		T5	102		T7	476
valid_sources[0x62]	17279	1		T3	1344		T5	118		T7	452
valid_sources[0x63]	17887	1		T3	1298		T5	110		T7	415
valid_sources[0x64]	18056	1		T3	1334		T5	79		T7	460
valid_sources[0x65]	18778	1		T3	1315		T5	92		T7	456
valid_sources[0x66]	17811	1		T3	1340		T5	64		T7	457
valid_sources[0x67]	18063	1		T3	1389		T5	127		T7	502
valid_sources[0x68]	18154	1		T3	1339		T5	128		T7	466
valid_sources[0x69]	17456	1		T3	1346		T5	124		T7	437
valid_sources[0x6a]	18240	1		T3	1347		T5	121		T7	460
valid_sources[0x6b]	19037	1		T3	1317		T5	145		T7	471
valid_sources[0x6c]	18689	1		T3	1352		T5	107		T7	483
valid_sources[0x6d]	18251	1		T3	1374		T5	161		T7	467
valid_sources[0x6e]	17785	1		T3	1313		T5	132		T7	460
valid_sources[0x6f]	18001	1		T3	1319		T5	126		T7	435
valid_sources[0x70]	18847	1		T3	1344		T5	169		T7	432
valid_sources[0x71]	18123	1		T3	1329		T5	129		T7	480
valid_sources[0x72]	18872	1		T3	1318		T5	172		T7	449
valid_sources[0x73]	16915	1		T3	1358		T5	213		T7	455
valid_sources[0x74]	17247	1		T3	1303		T5	127		T7	438
valid_sources[0x75]	17391	1		T3	1351		T5	132		T7	459
valid_sources[0x76]	18193	1		T3	1387		T5	128		T7	423
valid_sources[0x77]	18225	1		T3	1369		T5	169		T7	475
valid_sources[0x78]	18204	1		T3	1365		T4	1		T5	137
valid_sources[0x79]	18204	1		T3	1283		T5	163		T7	467
valid_sources[0x7a]	17948	1		T1	2		T3	1352		T5	122
valid_sources[0x7b]	18159	1		T3	1329		T5	127		T7	417
valid_sources[0x7c]	18615	1		T3	1326		T5	109		T7	437
valid_sources[0x7d]	17594	1		T3	1366		T5	99		T7	460
valid_sources[0x7e]	19852	1		T3	1342		T5	78		T7	440
valid_sources[0x7f]	17547	1		T3	1404		T5	153		T7	427
valid_sources[0x80]	18039	1		T1	2		T3	1333		T5	139

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1076364

1

T1

1

T3

78660

T5

7002

values[0x0]

all_enables

biggest_size

1621459

1

T1

6

T2

5

T3

118558

values[0x1]

all_enables

biggest_size

1621604

1

T1

10

T2

7

T3

119007