Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	733332200	5099925	0	0
wdog_bark_thold_rd_A	733332200	111784	0	0
wdog_bite_thold_rd_A	733332200	96353	0	0
wdog_ctrl_rd_A	733332200	97089	0	0
wdog_regwen_rd_A	733332200	112922	0	0
wkup_ctrl_rd_A	733332200	97840	0	0
wkup_thold_hi_rd_A	733332200	112486	0	0
wkup_thold_lo_rd_A	733332200	97420	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	5099925	0	0
T3	154191	378066	0	0
T4	355624	0	0	0
T5	866397	28177	0	0
T6	4196	0	0	0
T7	656596	123173	0	0
T8	124900	47394	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T12	0	25805	0	0
T21	0	79591	0	0
T27	53368	0	0	0
T29	0	68604	0	0
T38	0	92573	0	0
T39	0	115419	0	0
T40	0	64510	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	111784	0	0
T3	154191	19281	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	2214	0	0
T78	0	3124	0	0
T79	0	17017	0	0
T80	0	8897	0	0
T81	0	3526	0	0
T82	0	10824	0	0
T83	0	9051	0	0
T84	0	6355	0	0
T85	0	3521	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	96353	0	0
T3	154191	16506	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	1912	0	0
T78	0	2955	0	0
T79	0	14687	0	0
T80	0	7748	0	0
T81	0	3337	0	0
T82	0	9228	0	0
T83	0	7797	0	0
T84	0	5300	0	0
T85	0	3323	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	97089	0	0
T3	154191	17281	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	2081	0	0
T78	0	2907	0	0
T79	0	14609	0	0
T80	0	7670	0	0
T81	0	3084	0	0
T82	0	9227	0	0
T83	0	8230	0	0
T84	0	5370	0	0
T85	0	3270	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	112922	0	0
T3	154191	19475	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	2201	0	0
T78	0	3362	0	0
T79	0	18126	0	0
T80	0	9015	0	0
T81	0	3513	0	0
T82	0	10988	0	0
T83	0	9207	0	0
T84	0	6273	0	0
T85	0	3685	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	97840	0	0
T3	154191	17059	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	1807	0	0
T78	0	2769	0	0
T79	0	15294	0	0
T80	0	7840	0	0
T81	0	2810	0	0
T82	0	9407	0	0
T83	0	8166	0	0
T84	0	5567	0	0
T85	0	3215	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	112486	0	0
T3	154191	20061	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	2250	0	0
T78	0	3195	0	0
T79	0	17841	0	0
T80	0	9294	0	0
T81	0	3591	0	0
T82	0	10787	0	0
T83	0	9052	0	0
T84	0	6475	0	0
T85	0	3485	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733332200	97420	0	0
T3	154191	17071	0	0
T4	355624	0	0	0
T5	866397	0	0	0
T6	4196	0	0	0
T7	656596	0	0	0
T8	124900	0	0	0
T9	160934	0	0	0
T10	136864	0	0	0
T11	198586	0	0	0
T27	53368	0	0	0
T77	0	2164	0	0
T78	0	2901	0	0
T79	0	14763	0	0
T80	0	7573	0	0
T81	0	3108	0	0
T82	0	9523	0	0
T83	0	7869	0	0
T84	0	5456	0	0
T85	0	3217	0	0