Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	803733379	4994811	0	0
wdog_bark_thold_rd_A	803733379	128821	0	0
wdog_bite_thold_rd_A	803733379	111290	0	0
wdog_ctrl_rd_A	803733379	113250	0	0
wdog_regwen_rd_A	803733379	129575	0	0
wkup_ctrl_rd_A	803733379	114362	0	0
wkup_thold_hi_rd_A	803733379	128867	0	0
wkup_thold_lo_rd_A	803733379	111185	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	4994811	0	0
T11	431261	97739	0	0
T12	197299	51573	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	247788	0	0
T23	140002	50972	0	0
T27	0	186044	0	0
T31	0	68188	0	0
T35	0	51341	0	0
T41	0	163196	0	0
T42	0	48614	0	0
T43	0	147010	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	128821	0	0
T11	431261	9719	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2745	0	0
T42	0	4526	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	7611	0	0
T59	0	24099	0	0
T74	0	7155	0	0
T95	0	3480	0	0
T96	0	9299	0	0
T97	0	8343	0	0
T98	0	16941	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	111290	0	0
T11	431261	7892	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2532	0	0
T42	0	4286	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	7059	0	0
T59	0	20579	0	0
T74	0	6203	0	0
T95	0	3119	0	0
T96	0	7525	0	0
T97	0	7439	0	0
T98	0	14888	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	113250	0	0
T11	431261	7967	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2389	0	0
T42	0	4347	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	6990	0	0
T59	0	20830	0	0
T74	0	6449	0	0
T95	0	3104	0	0
T96	0	7792	0	0
T97	0	7439	0	0
T98	0	14908	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	129575	0	0
T11	431261	9286	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2926	0	0
T42	0	4888	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	7798	0	0
T59	0	23615	0	0
T74	0	7502	0	0
T95	0	3730	0	0
T96	0	9380	0	0
T97	0	8288	0	0
T98	0	17389	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	114362	0	0
T11	431261	8377	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2592	0	0
T42	0	4210	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	6733	0	0
T59	0	20850	0	0
T74	0	6367	0	0
T95	0	3284	0	0
T96	0	8261	0	0
T97	0	7034	0	0
T98	0	15426	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	128867	0	0
T11	431261	9160	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2917	0	0
T42	0	4898	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	8120	0	0
T59	0	23361	0	0
T74	0	6887	0	0
T95	0	3662	0	0
T96	0	8768	0	0
T97	0	8284	0	0
T98	0	17566	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	803733379	111185	0	0
T11	431261	7562	0	0
T12	197299	0	0	0
T13	117515	0	0	0
T14	145334	0	0	0
T15	26915	0	0	0
T16	712269	0	0	0
T23	140002	0	0	0
T35	0	2383	0	0
T42	0	4115	0	0
T44	48782	0	0	0
T45	106248	0	0	0
T46	44834	0	0	0
T56	0	7314	0	0
T59	0	19985	0	0
T74	0	6314	0	0
T95	0	3369	0	0
T96	0	7897	0	0
T97	0	6839	0	0
T98	0	14925	0	0