Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	365399	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4493977	1		T1	166		T2	16		T3	120761

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1196198	1		T1	45		T2	1		T3	31814
values[0x0]	1718756	1		T1	108		T2	9		T3	46016
values[0x1]	1944422	1		T1	107		T2	10		T3	52418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	162992	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4696384	1		T1	182		T2	16		T3	126179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18625	1		T1	1		T3	486		T4	7
valid_sources[0x01]	18770	1		T3	559		T5	447		T13	301
valid_sources[0x02]	19817	1		T1	1		T3	524		T4	2
valid_sources[0x03]	18323	1		T3	476		T5	460		T13	422
valid_sources[0x04]	18702	1		T1	2		T3	515		T4	1
valid_sources[0x05]	19132	1		T3	479		T4	2		T5	460
valid_sources[0x06]	17721	1		T3	499		T4	1		T5	452
valid_sources[0x07]	20413	1		T1	2		T3	567		T5	478
valid_sources[0x08]	19176	1		T3	462		T4	3		T5	457
valid_sources[0x09]	18333	1		T3	595		T5	464		T13	415
valid_sources[0x0a]	19647	1		T1	1		T3	496		T4	3
valid_sources[0x0b]	17063	1		T1	2		T3	470		T4	2
valid_sources[0x0c]	18155	1		T1	2		T3	525		T4	1
valid_sources[0x0d]	19277	1		T3	526		T5	478		T13	226
valid_sources[0x0e]	18334	1		T1	2		T3	484		T5	487
valid_sources[0x0f]	17774	1		T1	5		T3	442		T4	2
valid_sources[0x10]	18101	1		T3	521		T4	1		T5	497
valid_sources[0x11]	18555	1		T1	1		T2	20		T3	518
valid_sources[0x12]	17518	1		T1	3		T3	521		T5	396
valid_sources[0x13]	19613	1		T1	2		T3	495		T4	3
valid_sources[0x14]	21654	1		T3	471		T5	470		T13	884
valid_sources[0x15]	18136	1		T3	406		T5	460		T13	288
valid_sources[0x16]	18470	1		T3	476		T5	446		T13	333
valid_sources[0x17]	18547	1		T3	535		T4	4		T5	444
valid_sources[0x18]	20048	1		T3	540		T5	499		T13	670
valid_sources[0x19]	19524	1		T3	477		T4	2		T5	447
valid_sources[0x1a]	19577	1		T3	446		T4	2		T5	491
valid_sources[0x1b]	18835	1		T1	3		T3	574		T5	419
valid_sources[0x1c]	19323	1		T3	525		T4	4		T5	430
valid_sources[0x1d]	19919	1		T3	471		T5	462		T13	800
valid_sources[0x1e]	18847	1		T3	564		T4	1		T5	482
valid_sources[0x1f]	18492	1		T3	508		T5	433		T13	182
valid_sources[0x20]	18472	1		T1	2		T3	427		T5	427
valid_sources[0x21]	19512	1		T3	484		T4	2		T5	458
valid_sources[0x22]	20744	1		T3	584		T4	1		T5	469
valid_sources[0x23]	18469	1		T3	558		T4	2		T5	446
valid_sources[0x24]	20306	1		T3	517		T4	2		T5	474
valid_sources[0x25]	18438	1		T3	582		T5	408		T13	87
valid_sources[0x26]	18142	1		T3	495		T4	1		T5	439
valid_sources[0x27]	18307	1		T1	4		T3	519		T4	5
valid_sources[0x28]	20056	1		T1	4		T3	500		T4	1
valid_sources[0x29]	18667	1		T3	507		T5	440		T13	4
valid_sources[0x2a]	18615	1		T1	2		T3	493		T4	2
valid_sources[0x2b]	18507	1		T1	2		T3	448		T4	1
valid_sources[0x2c]	17897	1		T1	3		T3	518		T4	1
valid_sources[0x2d]	17785	1		T3	591		T4	1		T5	456
valid_sources[0x2e]	19678	1		T3	549		T4	3		T5	412
valid_sources[0x2f]	20606	1		T1	3		T3	532		T4	7
valid_sources[0x30]	17837	1		T1	1		T3	487		T5	466
valid_sources[0x31]	18678	1		T1	1		T3	540		T4	1
valid_sources[0x32]	18305	1		T3	494		T5	458		T13	92
valid_sources[0x33]	19302	1		T3	573		T4	4		T5	461
valid_sources[0x34]	20023	1		T3	568		T5	464		T10	1
valid_sources[0x35]	19419	1		T3	502		T5	464		T13	819
valid_sources[0x36]	20341	1		T3	488		T4	1		T5	427
valid_sources[0x37]	19210	1		T1	1		T3	505		T4	1
valid_sources[0x38]	21485	1		T1	1		T3	545		T5	469
valid_sources[0x39]	18318	1		T1	1		T3	521		T4	1
valid_sources[0x3a]	20617	1		T3	472		T4	1		T5	472
valid_sources[0x3b]	18598	1		T3	484		T4	1		T5	456
valid_sources[0x3c]	18095	1		T3	523		T4	1		T5	471
valid_sources[0x3d]	18668	1		T3	518		T5	441		T13	130
valid_sources[0x3e]	18411	1		T1	1		T3	537		T4	1
valid_sources[0x3f]	19276	1		T1	3		T3	520		T4	3
valid_sources[0x40]	18408	1		T1	2		T3	433		T4	2
valid_sources[0x41]	17983	1		T3	480		T4	1		T5	443
valid_sources[0x42]	18725	1		T1	3		T3	430		T4	1
valid_sources[0x43]	19790	1		T1	2		T3	494		T5	475
valid_sources[0x44]	18148	1		T3	528		T5	410		T13	313
valid_sources[0x45]	19771	1		T1	2		T3	504		T4	2
valid_sources[0x46]	20511	1		T1	4		T3	519		T4	1
valid_sources[0x47]	17605	1		T1	2		T3	497		T5	441
valid_sources[0x48]	18185	1		T1	1		T3	496		T4	2
valid_sources[0x49]	20453	1		T1	3		T3	536		T4	2
valid_sources[0x4a]	19546	1		T3	565		T5	447		T8	5
valid_sources[0x4b]	20788	1		T1	5		T3	512		T5	464
valid_sources[0x4c]	17769	1		T3	507		T4	1		T5	448
valid_sources[0x4d]	20340	1		T1	1		T3	522		T4	2
valid_sources[0x4e]	19205	1		T3	468		T5	425		T28	1
valid_sources[0x4f]	17921	1		T3	495		T4	1		T5	473
valid_sources[0x50]	19843	1		T3	486		T4	1		T5	481
valid_sources[0x51]	19934	1		T3	472		T4	1		T5	474
valid_sources[0x52]	18410	1		T1	3		T3	505		T5	438
valid_sources[0x53]	18735	1		T3	553		T4	2		T5	452
valid_sources[0x54]	18092	1		T3	508		T4	1		T5	454
valid_sources[0x55]	18718	1		T3	519		T4	1		T5	486
valid_sources[0x56]	18097	1		T3	542		T4	3		T5	418
valid_sources[0x57]	18568	1		T3	549		T5	467		T13	316
valid_sources[0x58]	19671	1		T3	542		T4	1		T5	451
valid_sources[0x59]	19366	1		T3	472		T4	1		T5	475
valid_sources[0x5a]	18283	1		T3	523		T4	1		T5	428
valid_sources[0x5b]	19232	1		T1	4		T3	476		T5	476
valid_sources[0x5c]	19760	1		T3	474		T4	1		T5	472
valid_sources[0x5d]	17451	1		T3	503		T5	447		T13	197
valid_sources[0x5e]	18845	1		T3	420		T5	439		T7	2
valid_sources[0x5f]	19832	1		T1	3		T3	536		T4	2
valid_sources[0x60]	19005	1		T1	3		T3	503		T5	475
valid_sources[0x61]	18400	1		T3	509		T4	1		T5	489
valid_sources[0x62]	19723	1		T3	546		T4	4		T5	447
valid_sources[0x63]	19255	1		T3	517		T5	415		T13	162
valid_sources[0x64]	19374	1		T3	496		T5	446		T13	972
valid_sources[0x65]	20068	1		T3	463		T5	518		T7	3
valid_sources[0x66]	19151	1		T1	7		T3	481		T5	462
valid_sources[0x67]	18576	1		T3	533		T4	1		T5	474
valid_sources[0x68]	18575	1		T1	1		T3	536		T4	1
valid_sources[0x69]	19663	1		T1	1		T3	504		T4	1
valid_sources[0x6a]	19282	1		T3	535		T4	2		T5	463
valid_sources[0x6b]	17959	1		T1	1		T3	469		T5	427
valid_sources[0x6c]	18099	1		T3	486		T4	3		T5	487
valid_sources[0x6d]	18028	1		T3	487		T4	1		T5	455
valid_sources[0x6e]	19198	1		T1	1		T3	511		T4	1
valid_sources[0x6f]	18507	1		T3	592		T4	5		T5	469
valid_sources[0x70]	18090	1		T1	1		T3	477		T4	1
valid_sources[0x71]	18325	1		T3	561		T5	472		T13	289
valid_sources[0x72]	19491	1		T3	528		T5	416		T13	345
valid_sources[0x73]	18398	1		T1	1		T3	509		T4	2
valid_sources[0x74]	19270	1		T1	1		T3	435		T4	2
valid_sources[0x75]	18875	1		T1	2		T3	572		T5	438
valid_sources[0x76]	18602	1		T1	1		T3	493		T5	440
valid_sources[0x77]	20467	1		T1	2		T3	468		T4	2
valid_sources[0x78]	18860	1		T3	525		T5	507		T13	197
valid_sources[0x79]	19543	1		T1	5		T3	519		T5	474
valid_sources[0x7a]	17228	1		T3	500		T4	2		T5	460
valid_sources[0x7b]	18991	1		T1	1		T3	513		T4	1
valid_sources[0x7c]	19346	1		T3	429		T5	410		T13	703
valid_sources[0x7d]	19185	1		T3	493		T4	3		T5	453
valid_sources[0x7e]	18892	1		T1	1		T3	490		T4	5
valid_sources[0x7f]	18464	1		T3	484		T4	2		T5	444
valid_sources[0x80]	18322	1		T1	2		T3	483		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1121709

1

T1

23

T2

1

T3

30032

values[0x0]

all_enables

biggest_size

1688484

1

T1

73

T2

7

T3

45308

values[0x1]

all_enables

biggest_size

1683784

1

T1

70

T2

8

T3

45421