Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	676820918	5339620	0	0
wdog_bark_thold_rd_A	676820918	123671	0	0
wdog_bite_thold_rd_A	676820918	107390	0	0
wdog_ctrl_rd_A	676820918	108023	0	0
wdog_regwen_rd_A	676820918	123527	0	0
wkup_ctrl_rd_A	676820918	108664	0	0
wkup_thold_hi_rd_A	676820918	123910	0	0
wkup_thold_lo_rd_A	676820918	108268	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	5339620	0	0
T3	595688	138767	0	0
T4	302281	0	0	0
T5	498466	132249	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T13	0	138217	0	0
T26	0	212888	0	0
T30	0	124903	0	0
T31	0	76450	0	0
T40	0	148949	0	0
T41	0	195634	0	0
T42	0	33348	0	0
T43	0	287342	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	123671	0	0
T3	595688	14493	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3756	0	0
T40	0	15201	0	0
T41	0	9545	0	0
T42	0	1732	0	0
T47	0	18090	0	0
T78	0	10987	0	0
T79	0	2566	0	0
T80	0	2256	0	0
T81	0	6130	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	107390	0	0
T3	595688	12365	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3418	0	0
T40	0	13119	0	0
T41	0	8564	0	0
T42	0	1540	0	0
T47	0	14960	0	0
T78	0	9797	0	0
T79	0	2104	0	0
T80	0	2106	0	0
T81	0	5794	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	108023	0	0
T3	595688	12283	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3395	0	0
T40	0	13499	0	0
T41	0	8481	0	0
T42	0	1558	0	0
T47	0	15697	0	0
T78	0	9697	0	0
T79	0	2236	0	0
T80	0	1924	0	0
T81	0	5704	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	123527	0	0
T3	595688	13832	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	4077	0	0
T40	0	15392	0	0
T41	0	9773	0	0
T42	0	1825	0	0
T47	0	18192	0	0
T78	0	10897	0	0
T79	0	2540	0	0
T80	0	2068	0	0
T81	0	6641	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	108664	0	0
T3	595688	12280	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3533	0	0
T40	0	13275	0	0
T41	0	8617	0	0
T42	0	1589	0	0
T47	0	15508	0	0
T78	0	9696	0	0
T79	0	2214	0	0
T80	0	1984	0	0
T81	0	6131	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	123910	0	0
T3	595688	13978	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3887	0	0
T40	0	15525	0	0
T41	0	10157	0	0
T42	0	1799	0	0
T47	0	17432	0	0
T78	0	10842	0	0
T79	0	2485	0	0
T80	0	2420	0	0
T81	0	6520	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676820918	108268	0	0
T3	595688	12079	0	0
T4	302281	0	0	0
T5	498466	0	0	0
T6	346996	0	0	0
T7	525870	0	0	0
T8	12548	0	0	0
T9	43935	0	0	0
T10	15330	0	0	0
T11	195288	0	0	0
T12	5254	0	0	0
T31	0	3323	0	0
T40	0	13291	0	0
T41	0	8407	0	0
T42	0	1816	0	0
T47	0	15795	0	0
T78	0	10131	0	0
T79	0	2131	0	0
T80	0	1941	0	0
T81	0	5755	0	0