Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	384870	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4696733	1		T1	14		T2	189		T3	15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1247977	1		T1	1		T2	41		T3	1
values[0x0]	1794712	1		T1	11		T2	108		T3	9
values[0x1]	2038914	1		T1	8		T2	145		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	171299	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4910304	1		T1	14		T2	220		T3	15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19283	1		T2	1		T3	1		T11	1215
valid_sources[0x01]	19732	1		T11	1189		T13	214		T14	156
valid_sources[0x02]	18541	1		T11	1204		T12	2		T13	205
valid_sources[0x03]	20628	1		T11	1225		T29	1		T13	225
valid_sources[0x04]	20059	1		T2	6		T9	1		T11	1337
valid_sources[0x05]	17625	1		T7	1		T11	1261		T13	238
valid_sources[0x06]	20197	1		T2	1		T11	1309		T29	1
valid_sources[0x07]	20117	1		T11	1326		T12	1		T13	227
valid_sources[0x08]	18586	1		T2	3		T11	1330		T12	3
valid_sources[0x09]	20315	1		T2	2		T11	1379		T12	3
valid_sources[0x0a]	20488	1		T2	2		T11	1168		T13	184
valid_sources[0x0b]	19578	1		T2	2		T11	1164		T12	4
valid_sources[0x0c]	19681	1		T11	1289		T13	215		T14	268
valid_sources[0x0d]	18804	1		T8	2		T11	1321		T12	5
valid_sources[0x0e]	19940	1		T3	1		T10	8		T11	1353
valid_sources[0x0f]	19773	1		T2	1		T11	1313		T13	233
valid_sources[0x10]	19987	1		T11	1163		T13	225		T14	201
valid_sources[0x11]	21234	1		T2	1		T11	1286		T12	1
valid_sources[0x12]	21711	1		T2	1		T11	1292		T12	1
valid_sources[0x13]	19040	1		T8	1		T11	1307		T12	3
valid_sources[0x14]	18760	1		T5	5		T7	2		T11	1301
valid_sources[0x15]	20196	1		T2	2		T11	1173		T12	1
valid_sources[0x16]	19232	1		T2	1		T5	1		T11	1229
valid_sources[0x17]	21548	1		T11	1239		T12	2		T13	232
valid_sources[0x18]	20222	1		T11	1183		T13	205		T14	86
valid_sources[0x19]	20042	1		T2	1		T9	2		T11	1395
valid_sources[0x1a]	20120	1		T2	2		T5	1		T7	1
valid_sources[0x1b]	19308	1		T2	1		T11	1247		T12	1
valid_sources[0x1c]	19856	1		T11	1327		T13	246		T14	168
valid_sources[0x1d]	18673	1		T2	3		T11	1240		T13	238
valid_sources[0x1e]	21375	1		T2	1		T11	1407		T12	1
valid_sources[0x1f]	19226	1		T2	1		T11	1241		T13	201
valid_sources[0x20]	21362	1		T2	1		T11	1434		T13	232
valid_sources[0x21]	22293	1		T2	1		T11	1207		T12	2
valid_sources[0x22]	20115	1		T2	1		T11	1313		T12	1
valid_sources[0x23]	19265	1		T2	3		T11	1129		T12	5
valid_sources[0x24]	19535	1		T2	3		T7	1		T11	1214
valid_sources[0x25]	17779	1		T11	1291		T12	2		T13	245
valid_sources[0x26]	19082	1		T2	1		T8	2		T11	1286
valid_sources[0x27]	19182	1		T2	1		T11	1413		T29	1
valid_sources[0x28]	20737	1		T2	2		T11	1277		T12	1
valid_sources[0x29]	20084	1		T2	4		T8	3		T11	1228
valid_sources[0x2a]	18884	1		T3	1		T11	1095		T29	1
valid_sources[0x2b]	20187	1		T2	1		T11	1253		T12	3
valid_sources[0x2c]	18251	1		T11	1303		T13	240		T14	38
valid_sources[0x2d]	21262	1		T11	1129		T13	243		T14	416
valid_sources[0x2e]	20162	1		T2	1		T11	1223		T13	210
valid_sources[0x2f]	20077	1		T2	1		T11	1279		T13	224
valid_sources[0x30]	20307	1		T11	1126		T13	235		T14	20
valid_sources[0x31]	21565	1		T11	1278		T13	221		T14	155
valid_sources[0x32]	18561	1		T2	1		T11	1153		T12	1
valid_sources[0x33]	19312	1		T2	5		T5	1		T11	1152
valid_sources[0x34]	20395	1		T2	2		T11	1266		T12	1
valid_sources[0x35]	20003	1		T2	2		T8	1		T11	1260
valid_sources[0x36]	18702	1		T2	1		T11	1313		T29	1
valid_sources[0x37]	21150	1		T2	2		T11	1356		T13	238
valid_sources[0x38]	20516	1		T11	1043		T12	1		T13	264
valid_sources[0x39]	21229	1		T2	4		T11	1212		T13	218
valid_sources[0x3a]	18357	1		T2	1		T11	1126		T12	1
valid_sources[0x3b]	21293	1		T9	1		T11	1349		T13	206
valid_sources[0x3c]	18933	1		T2	1		T4	20		T11	1291
valid_sources[0x3d]	20258	1		T7	1		T11	1072		T12	2
valid_sources[0x3e]	19459	1		T2	3		T11	1193		T12	1
valid_sources[0x3f]	19733	1		T11	1195		T13	225		T14	442
valid_sources[0x40]	20717	1		T2	2		T9	2		T11	1318
valid_sources[0x41]	22064	1		T2	1		T3	1		T11	1185
valid_sources[0x42]	18508	1		T2	1		T11	1114		T12	3
valid_sources[0x43]	21303	1		T11	1295		T12	3		T13	233
valid_sources[0x44]	19235	1		T1	1		T2	1		T11	1253
valid_sources[0x45]	19586	1		T11	1253		T13	209		T14	12
valid_sources[0x46]	20163	1		T11	1209		T13	209		T14	168
valid_sources[0x47]	18231	1		T2	1		T7	1		T8	4
valid_sources[0x48]	20027	1		T2	1		T3	1		T11	1299
valid_sources[0x49]	19112	1		T11	1397		T13	234		T14	168
valid_sources[0x4a]	18274	1		T11	1299		T12	2		T13	228
valid_sources[0x4b]	18637	1		T7	1		T11	1199		T12	1
valid_sources[0x4c]	18754	1		T2	1		T11	1297		T13	227
valid_sources[0x4d]	21809	1		T2	1		T11	1334		T13	224
valid_sources[0x4e]	22310	1		T2	3		T11	1343		T13	236
valid_sources[0x4f]	19315	1		T2	1		T11	1227		T12	1
valid_sources[0x50]	20195	1		T11	1270		T12	1		T13	222
valid_sources[0x51]	18156	1		T2	1		T3	1		T11	1387
valid_sources[0x52]	19906	1		T2	2		T9	2		T11	1229
valid_sources[0x53]	18635	1		T11	1392		T12	2		T13	214
valid_sources[0x54]	22256	1		T2	1		T11	1310		T13	253
valid_sources[0x55]	19882	1		T2	1		T7	1		T11	1200
valid_sources[0x56]	20788	1		T1	3		T11	1226		T12	2
valid_sources[0x57]	19196	1		T2	2		T11	1215		T13	240
valid_sources[0x58]	20842	1		T11	1224		T12	1		T13	221
valid_sources[0x59]	21388	1		T2	1		T8	1		T11	1340
valid_sources[0x5a]	20473	1		T2	3		T7	2		T11	1203
valid_sources[0x5b]	19223	1		T2	2		T11	1360		T12	4
valid_sources[0x5c]	18217	1		T2	1		T11	1218		T13	217
valid_sources[0x5d]	17994	1		T9	1		T11	1236		T12	1
valid_sources[0x5e]	22401	1		T2	3		T7	1		T11	1259
valid_sources[0x5f]	18982	1		T2	1		T11	1171		T12	2
valid_sources[0x60]	20399	1		T2	5		T11	1324		T12	1
valid_sources[0x61]	18048	1		T2	1		T3	1		T11	1393
valid_sources[0x62]	20348	1		T10	3		T11	1320		T29	3
valid_sources[0x63]	20818	1		T11	1315		T13	172		T14	55
valid_sources[0x64]	22066	1		T2	1		T11	1223		T13	218
valid_sources[0x65]	19525	1		T2	4		T10	3		T11	1153
valid_sources[0x66]	20073	1		T2	3		T9	2		T11	1241
valid_sources[0x67]	20772	1		T2	1		T11	1347		T12	2
valid_sources[0x68]	19731	1		T3	1		T11	1324		T12	2
valid_sources[0x69]	19557	1		T3	1		T11	1176		T12	3
valid_sources[0x6a]	21609	1		T2	3		T11	1157		T12	3
valid_sources[0x6b]	18384	1		T2	3		T11	1310		T29	1
valid_sources[0x6c]	19313	1		T2	1		T9	1		T11	1141
valid_sources[0x6d]	21143	1		T2	2		T11	1212		T12	6
valid_sources[0x6e]	19843	1		T11	1137		T13	212		T14	201
valid_sources[0x6f]	20037	1		T2	2		T11	1222		T13	227
valid_sources[0x70]	17945	1		T2	2		T11	1178		T13	208
valid_sources[0x71]	19657	1		T2	1		T11	1156		T13	228
valid_sources[0x72]	21962	1		T2	1		T3	2		T11	1313
valid_sources[0x73]	19145	1		T11	1195		T12	4		T13	217
valid_sources[0x74]	19053	1		T11	1248		T12	1		T13	224
valid_sources[0x75]	18580	1		T1	3		T2	2		T11	1210
valid_sources[0x76]	20636	1		T2	1		T3	1		T11	1179
valid_sources[0x77]	19875	1		T2	1		T11	1287		T13	216
valid_sources[0x78]	19639	1		T11	1101		T12	1		T13	203
valid_sources[0x79]	18758	1		T2	1		T11	1300		T12	3
valid_sources[0x7a]	18490	1		T1	2		T2	2		T11	1235
valid_sources[0x7b]	20994	1		T2	2		T11	1308		T13	217
valid_sources[0x7c]	21207	1		T11	1172		T12	1		T13	207
valid_sources[0x7d]	19083	1		T2	1		T11	1213		T12	4
valid_sources[0x7e]	19782	1		T2	1		T11	1127		T12	2
valid_sources[0x7f]	19628	1		T2	1		T3	1		T11	1174
valid_sources[0x80]	20409	1		T1	1		T2	2		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1170337

1

T1

1

T2

18

T3

1

values[0x0]

all_enables

biggest_size

1762417

1

T1

8

T2

83

T3

8

values[0x1]

all_enables

biggest_size

1763979

1

T1

5

T2

88

T3

6