Unified Coverage Report :: Module :: aon_timer_csr_assert_fpv

Module : aon_timer_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_aon_timer_csr_assert_0/aon_timer_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.aon_timer_csr_assert	100.00						100.00

---

Module Instance : tb.dut.aon_timer_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	66.67	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : aon_timer_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	679339112	5612136	0	0
wdog_bark_thold_rd_A	679339112	101603	0	0
wdog_bite_thold_rd_A	679339112	87726	0	0
wdog_ctrl_rd_A	679339112	88735	0	0
wdog_regwen_rd_A	679339112	101942	0	0
wkup_ctrl_rd_A	679339112	88354	0	0
wkup_thold_hi_rd_A	679339112	102112	0	0
wkup_thold_lo_rd_A	679339112	88438	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	5612136	0	0
T11	136831	377510	0	0
T12	145702	0	0	0
T13	229055	61807	0	0
T14	220021	51408	0	0
T24	0	209039	0	0
T29	17165	0	0	0
T30	46305	0	0	0
T31	0	234036	0	0
T38	0	84414	0	0
T39	0	129678	0	0
T40	0	134404	0	0
T41	0	79492	0	0
T42	0	77226	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0

wdog_bark_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	101603	0	0
T14	220021	5566	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	13466	0	0
T41	0	8005	0	0
T42	0	7719	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	6774	0	0
T89	0	3747	0	0
T90	0	15930	0	0
T91	0	9628	0	0
T92	0	7862	0	0
T93	0	6752	0	0

wdog_bite_thold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	87726	0	0
T14	220021	4772	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	11336	0	0
T41	0	7209	0	0
T42	0	6584	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	5713	0	0
T89	0	3007	0	0
T90	0	13993	0	0
T91	0	8370	0	0
T92	0	6444	0	0
T93	0	5537	0	0

wdog_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	88735	0	0
T14	220021	4728	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	11717	0	0
T41	0	7585	0	0
T42	0	7009	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	5679	0	0
T89	0	2990	0	0
T90	0	13428	0	0
T91	0	8140	0	0
T92	0	6980	0	0
T93	0	5896	0	0

wdog_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	101942	0	0
T14	220021	5296	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	14029	0	0
T41	0	8473	0	0
T42	0	7841	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	6851	0	0
T89	0	3449	0	0
T90	0	15968	0	0
T91	0	9436	0	0
T92	0	7953	0	0
T93	0	6208	0	0

wkup_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	88354	0	0
T14	220021	4945	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	12053	0	0
T41	0	7134	0	0
T42	0	7031	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	5633	0	0
T89	0	3022	0	0
T90	0	13788	0	0
T91	0	8106	0	0
T92	0	6838	0	0
T93	0	5464	0	0

wkup_thold_hi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	102112	0	0
T14	220021	5112	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	13602	0	0
T41	0	8411	0	0
T42	0	8074	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	6571	0	0
T89	0	3626	0	0
T90	0	16528	0	0
T91	0	9117	0	0
T92	0	7991	0	0
T93	0	6623	0	0

wkup_thold_lo_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	679339112	88438	0	0
T14	220021	4343	0	0
T30	46305	0	0	0
T31	852627	0	0	0
T32	202673	0	0	0
T40	0	11797	0	0
T41	0	6969	0	0
T42	0	7005	0	0
T43	45335	0	0	0
T44	12902	0	0	0
T45	310630	0	0	0
T46	207253	0	0	0
T47	955191	0	0	0
T48	415670	0	0	0
T55	0	5810	0	0
T89	0	3086	0	0
T90	0	14090	0	0
T91	0	8188	0	0
T92	0	6910	0	0
T93	0	5632	0	0