Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_aon_timer_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	428779	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	5264108	1		T1	13		T2	34463		T3	14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1399984	1		T1	1		T2	9282		T3	1
values[0x0]	2011228	1		T1	8		T2	13071		T3	6
values[0x1]	2281675	1		T1	11		T2	14996		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	190242	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	5502645	1		T1	14		T2	35980		T3	14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22749	1		T2	131		T5	360		T6	2
valid_sources[0x01]	22317	1		T2	185		T5	1032		T6	4
valid_sources[0x02]	22275	1		T2	148		T3	2		T5	937
valid_sources[0x03]	22772	1		T2	114		T5	512		T6	1
valid_sources[0x04]	21432	1		T2	146		T5	446		T6	4
valid_sources[0x05]	23027	1		T2	176		T5	512		T6	1
valid_sources[0x06]	22307	1		T2	197		T5	645		T7	394
valid_sources[0x07]	21238	1		T2	109		T5	458		T7	311
valid_sources[0x08]	21091	1		T2	161		T5	540		T6	3
valid_sources[0x09]	22806	1		T2	169		T3	1		T5	753
valid_sources[0x0a]	20837	1		T2	186		T5	752		T7	516
valid_sources[0x0b]	20416	1		T2	177		T5	231		T6	11
valid_sources[0x0c]	23383	1		T2	128		T5	921		T6	3
valid_sources[0x0d]	23698	1		T1	9		T2	158		T5	735
valid_sources[0x0e]	21820	1		T2	124		T5	447		T6	7
valid_sources[0x0f]	22482	1		T2	145		T5	575		T6	1
valid_sources[0x10]	22479	1		T2	158		T5	1270		T7	163
valid_sources[0x11]	24034	1		T2	158		T5	1333		T7	1222
valid_sources[0x12]	21828	1		T2	132		T3	2		T5	100
valid_sources[0x13]	22758	1		T2	140		T5	593		T6	3
valid_sources[0x14]	22686	1		T2	118		T5	900		T7	153
valid_sources[0x15]	22044	1		T2	144		T5	965		T7	715
valid_sources[0x16]	22100	1		T2	156		T5	613		T7	521
valid_sources[0x17]	22056	1		T2	125		T5	882		T7	290
valid_sources[0x18]	22184	1		T2	159		T5	764		T7	479
valid_sources[0x19]	21670	1		T2	136		T5	911		T6	1
valid_sources[0x1a]	21857	1		T2	135		T5	1088		T7	550
valid_sources[0x1b]	22539	1		T2	164		T5	1045		T6	4
valid_sources[0x1c]	23054	1		T2	136		T5	763		T6	1
valid_sources[0x1d]	22222	1		T2	161		T5	352		T7	195
valid_sources[0x1e]	21768	1		T2	125		T5	591		T7	745
valid_sources[0x1f]	23177	1		T2	179		T5	774		T7	537
valid_sources[0x20]	22067	1		T2	155		T5	571		T7	393
valid_sources[0x21]	23217	1		T2	129		T5	658		T7	483
valid_sources[0x22]	22160	1		T2	151		T5	707		T7	277
valid_sources[0x23]	22483	1		T2	171		T5	520		T7	718
valid_sources[0x24]	21809	1		T2	135		T5	902		T7	556
valid_sources[0x25]	21369	1		T2	132		T5	661		T7	523
valid_sources[0x26]	22373	1		T2	140		T5	476		T7	378
valid_sources[0x27]	22488	1		T2	130		T5	1019		T6	7
valid_sources[0x28]	22472	1		T1	7		T2	121		T5	211
valid_sources[0x29]	21536	1		T2	134		T3	2		T5	386
valid_sources[0x2a]	21491	1		T2	157		T5	537		T6	3
valid_sources[0x2b]	21080	1		T2	200		T5	454		T6	2
valid_sources[0x2c]	22978	1		T2	168		T5	951		T7	525
valid_sources[0x2d]	24486	1		T2	137		T5	586		T6	2
valid_sources[0x2e]	22785	1		T2	133		T5	1480		T6	1
valid_sources[0x2f]	21871	1		T2	176		T5	768		T7	389
valid_sources[0x30]	22112	1		T2	159		T5	342		T7	462
valid_sources[0x31]	21934	1		T2	146		T5	852		T7	166
valid_sources[0x32]	23849	1		T2	167		T5	894		T7	230
valid_sources[0x33]	21523	1		T2	117		T5	616		T6	2
valid_sources[0x34]	22929	1		T2	149		T5	1078		T7	139
valid_sources[0x35]	20867	1		T2	109		T5	945		T7	473
valid_sources[0x36]	21706	1		T2	144		T5	786		T7	417
valid_sources[0x37]	22588	1		T2	127		T5	765		T7	283
valid_sources[0x38]	21738	1		T2	146		T5	370		T7	397
valid_sources[0x39]	22623	1		T2	160		T5	591		T6	1
valid_sources[0x3a]	22230	1		T2	111		T5	881		T6	3
valid_sources[0x3b]	21965	1		T2	176		T5	948		T7	350
valid_sources[0x3c]	22761	1		T2	130		T5	769		T6	1
valid_sources[0x3d]	23152	1		T2	121		T5	717		T6	3
valid_sources[0x3e]	22798	1		T2	168		T5	452		T7	337
valid_sources[0x3f]	20699	1		T2	117		T5	620		T6	2
valid_sources[0x40]	21877	1		T2	154		T5	693		T7	37
valid_sources[0x41]	21620	1		T2	117		T5	287		T6	2
valid_sources[0x42]	23022	1		T2	159		T5	1016		T6	1
valid_sources[0x43]	21636	1		T2	118		T5	76		T6	1
valid_sources[0x44]	22950	1		T2	175		T5	800		T6	2
valid_sources[0x45]	23410	1		T2	169		T5	1841		T6	1
valid_sources[0x46]	22550	1		T2	133		T5	128		T7	637
valid_sources[0x47]	22158	1		T2	127		T5	700		T7	527
valid_sources[0x48]	21895	1		T2	138		T5	547		T7	469
valid_sources[0x49]	23010	1		T2	145		T5	887		T7	444
valid_sources[0x4a]	22072	1		T2	173		T5	514		T6	7
valid_sources[0x4b]	22941	1		T2	153		T5	1162		T7	635
valid_sources[0x4c]	21472	1		T2	179		T3	1		T5	1443
valid_sources[0x4d]	21722	1		T2	171		T5	392		T6	2
valid_sources[0x4e]	22436	1		T2	183		T5	451		T6	4
valid_sources[0x4f]	23224	1		T2	146		T5	758		T6	1
valid_sources[0x50]	22757	1		T2	141		T5	1083		T7	772
valid_sources[0x51]	22602	1		T2	135		T5	1518		T6	1
valid_sources[0x52]	21013	1		T2	141		T5	655		T6	2
valid_sources[0x53]	21540	1		T2	130		T5	735		T6	2
valid_sources[0x54]	22600	1		T2	136		T5	611		T7	342
valid_sources[0x55]	22420	1		T2	124		T5	1120		T7	477
valid_sources[0x56]	21477	1		T2	126		T5	641		T7	160
valid_sources[0x57]	22512	1		T2	153		T5	853		T7	753
valid_sources[0x58]	22661	1		T2	127		T5	861		T6	1
valid_sources[0x59]	21455	1		T2	123		T5	419		T7	367
valid_sources[0x5a]	21832	1		T2	146		T5	784		T6	4
valid_sources[0x5b]	21189	1		T2	125		T5	618		T6	1
valid_sources[0x5c]	21346	1		T2	145		T3	2		T5	487
valid_sources[0x5d]	23756	1		T2	165		T5	1300		T7	249
valid_sources[0x5e]	22177	1		T2	154		T5	550		T7	496
valid_sources[0x5f]	23160	1		T2	152		T5	636		T6	1
valid_sources[0x60]	23354	1		T2	139		T5	830		T6	1
valid_sources[0x61]	21564	1		T2	146		T5	669		T7	285
valid_sources[0x62]	21504	1		T2	159		T5	432		T6	1
valid_sources[0x63]	22545	1		T2	133		T5	641		T6	9
valid_sources[0x64]	22403	1		T2	163		T5	757		T6	1
valid_sources[0x65]	22775	1		T2	192		T5	277		T7	609
valid_sources[0x66]	21326	1		T2	157		T5	726		T6	2
valid_sources[0x67]	22532	1		T2	145		T5	586		T6	2
valid_sources[0x68]	22012	1		T2	125		T5	521		T6	4
valid_sources[0x69]	22090	1		T2	167		T5	1138		T7	422
valid_sources[0x6a]	22448	1		T2	95		T5	491		T6	2
valid_sources[0x6b]	23666	1		T2	154		T5	1545		T7	494
valid_sources[0x6c]	21117	1		T2	153		T5	597		T7	201
valid_sources[0x6d]	21365	1		T2	115		T5	553		T7	397
valid_sources[0x6e]	21805	1		T2	150		T5	739		T6	4
valid_sources[0x6f]	21895	1		T2	157		T5	758		T7	583
valid_sources[0x70]	21250	1		T2	156		T5	824		T7	655
valid_sources[0x71]	23455	1		T2	143		T5	573		T7	1055
valid_sources[0x72]	23394	1		T2	133		T5	947		T6	2
valid_sources[0x73]	21135	1		T2	144		T5	1038		T6	2
valid_sources[0x74]	22316	1		T2	171		T5	673		T7	169
valid_sources[0x75]	22387	1		T2	149		T5	713		T7	408
valid_sources[0x76]	22051	1		T1	1		T2	128		T5	1092
valid_sources[0x77]	23652	1		T2	192		T5	947		T7	453
valid_sources[0x78]	20509	1		T2	128		T5	281		T6	2
valid_sources[0x79]	23188	1		T2	131		T5	720		T7	749
valid_sources[0x7a]	21859	1		T2	139		T5	582		T6	4
valid_sources[0x7b]	21958	1		T2	138		T5	720		T7	229
valid_sources[0x7c]	23361	1		T2	132		T5	523		T7	618
valid_sources[0x7d]	22570	1		T2	183		T3	1		T5	662
valid_sources[0x7e]	20483	1		T2	137		T3	1		T5	1125
valid_sources[0x7f]	22365	1		T2	140		T5	1025		T7	532
valid_sources[0x80]	22241	1		T2	132		T5	1028		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1313885

1

T2

8682

T4

1

T5

43390

values[0x0]

all_enables

biggest_size

1975386

1

T1

6

T2

12777

T3

5

values[0x1]

all_enables

biggest_size

1974837

1

T1

7

T2

13004

T3

9